clk: ingenic: Add missing flag for UDC clock

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Paul Cercueil and committed by

Stephen Boyd 7 years ago 2b555a4b 574f4e80

+1 -1

1 changed file

expand all

drivers

clk

ingenic

jz4740-cgu.c

+1 -1

drivers/clk/ingenic/jz4740-cgu.c

··· 161 161 }, 162 162 163 163 [JZ4740_CLK_UDC] = { 164 - "udc", CGU_CLK_MUX | CGU_CLK_DIV, 164 + "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, 165 165 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, 166 166 .mux = { CGU_REG_CPCCR, 29, 1 }, 167 167 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },