tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu:Add pcie gen5 support in pcie capability.

Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Feifei Xu and committed by
Alex Deucher 2b3a1f51 366468ff

+16 -2
+14 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 4793 4793 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | 4794 4794 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); 4795 4795 } else { 4796 - if (speed_cap == PCIE_SPEED_16_0GT) 4796 + if (speed_cap == PCIE_SPEED_32_0GT) 4797 + adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | 4798 + CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | 4799 + CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | 4800 + CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | 4801 + CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); 4802 + else if (speed_cap == PCIE_SPEED_16_0GT) 4797 4803 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | 4798 4804 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | 4799 4805 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | ··· 4819 4813 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | 4820 4814 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); 4821 4815 } else { 4822 - if (platform_speed_cap == PCIE_SPEED_16_0GT) 4816 + if (platform_speed_cap == PCIE_SPEED_32_0GT) 4817 + adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | 4818 + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 4819 + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | 4820 + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | 4821 + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); 4822 + else if (platform_speed_cap == PCIE_SPEED_16_0GT) 4823 4823 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | 4824 4824 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 4825 4825 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+2
drivers/gpu/drm/amd/include/amd_pcie.h
··· 28 28 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000 29 29 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000 30 30 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000 31 + #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00100000 31 32 #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000 32 33 #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16 33 34 ··· 37 36 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002 38 37 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004 39 38 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008 39 + #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00000010 40 40 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF 41 41 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 42 42