tjh.dev
+1
-1
arch/arm/boot/dts/imx6sx-pinfunc.h
+1
-1
arch/arm/boot/dts/imx6sx-pinfunc.h
···
1026
1026
#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
1027
1027
#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
1028
1028
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4
1029
-
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0
1029
+
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0
1030
1030
#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
1031
1031
#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
1032
1032
#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
+1
-1
arch/arm64/boot/dts/freescale/imx8mp.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp.dtsi
···
702
702
reg = <0x30bd0000 0x10000>;
703
703
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
704
704
clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
705
-
<&clk IMX8MP_CLK_SDMA1_ROOT>;
705
+
<&clk IMX8MP_CLK_AHB>;
706
706
clock-names = "ipg", "ahb";
707
707
#dma-cells = <3>;
708
708
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+1
-1
arch/arm64/boot/dts/freescale/imx8mq.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mq.dtsi
···
423
423
tmu: tmu@30260000 {
424
424
compatible = "fsl,imx8mq-tmu";
425
425
reg = <0x30260000 0x10000>;
426
-
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
426
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
427
427
clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
428
428
little-endian;
429
429
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;