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Revert "arm64: dts: Add support for Unisoc's UMS512"

The patch uses the "dt-bindings/clock/sprd,ums512-clk.h header, which
is not merged yet. This caused a build regression, and it means the
patch was not ready to get merged anyway.

This reverts commit 23410de5796cd49abb3f9b6d377822e18298e0a0.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 2a9c7b90 8071974c

+1 -1253
+1 -2
arch/arm64/boot/dts/sprd/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ 3 3 sp9860g-1h10.dtb \ 4 - sp9863a-1h10.dtb \ 5 - ums512-1h10.dtb 4 + sp9863a-1h10.dtb
-263
arch/arm64/boot/dts/sprd/sc2730.dtsi
··· 1 - // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 - /* 3 - * Unisoc SC2730 PMIC dts file 4 - * 5 - * Copyright (C) 2021, Unisoc Inc. 6 - */ 7 - 8 - &adi_bus { 9 - sc2730_pmic: pmic@0 { 10 - compatible = "sprd,sc2730"; 11 - reg = <0>; 12 - spi-max-frequency = <26000000>; 13 - interrupt-controller; 14 - #interrupt-cells = <1>; 15 - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 16 - #address-cells = <1>; 17 - #size-cells = <0>; 18 - 19 - regulators@1800 { 20 - compatible = "sprd,sc2730-regulator"; 21 - reg = <0x1800>; 22 - 23 - vddcpu: DCDC_CPU { 24 - regulator-name = "vddcpu"; 25 - regulator-min-microvolt = <200000>; 26 - regulator-max-microvolt = <1596875>; 27 - regulator-ramp-delay = <25000>; 28 - regulator-always-on; 29 - }; 30 - 31 - vddgpu: DCDC_GPU { 32 - regulator-name = "vddgpu"; 33 - regulator-min-microvolt = <200000>; 34 - regulator-max-microvolt = <1596875>; 35 - regulator-ramp-delay = <25000>; 36 - regulator-always-on; 37 - }; 38 - 39 - vddcore: DCDC_CORE { 40 - regulator-name = "vddcore"; 41 - regulator-min-microvolt = <200000>; 42 - regulator-max-microvolt = <1596875>; 43 - regulator-ramp-delay = <25000>; 44 - regulator-always-on; 45 - }; 46 - 47 - vddmodem: DCDC_MODEM { 48 - regulator-name = "vddmodem"; 49 - regulator-min-microvolt = <200000>; 50 - regulator-max-microvolt = <1596875>; 51 - regulator-ramp-delay = <25000>; 52 - regulator-always-on; 53 - }; 54 - 55 - vddmem: DCDC_MEM { 56 - regulator-name = "vddmem"; 57 - regulator-min-microvolt = <400000>; 58 - regulator-max-microvolt = <1593750>; 59 - regulator-ramp-delay = <25000>; 60 - regulator-always-on; 61 - }; 62 - 63 - vddmemq: DCDC_MEMQ { 64 - regulator-name = "vddmemq"; 65 - regulator-min-microvolt = <400000>; 66 - regulator-max-microvolt = <1596875>; 67 - regulator-ramp-delay = <25000>; 68 - regulator-always-on; 69 - }; 70 - 71 - vddgen0: DCDC_GEN0 { 72 - regulator-name = "vddgen0"; 73 - regulator-min-microvolt = <1220000>; 74 - regulator-max-microvolt = <2410625>; 75 - regulator-ramp-delay = <25000>; 76 - regulator-always-on; 77 - }; 78 - 79 - vddgen1: DCDC_GEN1 { 80 - regulator-name = "vddgen1"; 81 - regulator-min-microvolt = <850000>; 82 - regulator-max-microvolt = <1643750>; 83 - regulator-ramp-delay = <25000>; 84 - regulator-always-on; 85 - }; 86 - 87 - vddsram: DCDC_SRAM { 88 - regulator-name = "vddsram"; 89 - regulator-min-microvolt = <200000>; 90 - regulator-max-microvolt = <1596875>; 91 - regulator-ramp-delay = <25000>; 92 - regulator-always-on; 93 - }; 94 - 95 - avdd18: LDO_AVDD18 { 96 - regulator-name = "avdd18"; 97 - regulator-min-microvolt = <1175000>; 98 - regulator-max-microvolt = <1805000>; 99 - regulator-ramp-delay = <25000>; 100 - regulator-always-on; 101 - }; 102 - 103 - vddrf18: LDO_VDDRF18 { 104 - regulator-name = "vddrf18"; 105 - regulator-min-microvolt = <1175000>; 106 - regulator-max-microvolt = <1805000>; 107 - regulator-ramp-delay = <25000>; 108 - regulator-always-on; 109 - }; 110 - 111 - vddcamio: LDO_VDDCAMIO { 112 - regulator-name = "vddcamio"; 113 - regulator-min-microvolt = <1200000>; 114 - regulator-max-microvolt = <1830000>; 115 - regulator-ramp-delay = <25000>; 116 - }; 117 - 118 - vddwcn: LDO_VDDWCN { 119 - regulator-name = "vddwcn"; 120 - regulator-min-microvolt = <900000>; 121 - regulator-max-microvolt = <1845000>; 122 - regulator-ramp-delay = <25000>; 123 - }; 124 - 125 - vddcamd1: LDO_VDDCAMD1 { 126 - regulator-name = "vddcamd1"; 127 - regulator-min-microvolt = <900000>; 128 - regulator-max-microvolt = <1365000>; 129 - regulator-ramp-delay = <25000>; 130 - }; 131 - 132 - vddcamd0: LDO_VDDCAMD0 { 133 - regulator-name = "vddcamd0"; 134 - regulator-min-microvolt = <900000>; 135 - regulator-max-microvolt = <1365000>; 136 - regulator-ramp-delay = <25000>; 137 - }; 138 - 139 - vddrf1v25: LDO_VDDRF1V25 { 140 - regulator-name = "vddrf1v25"; 141 - regulator-min-microvolt = <900000>; 142 - regulator-max-microvolt = <1365000>; 143 - regulator-ramp-delay = <25000>; 144 - regulator-always-on; 145 - }; 146 - 147 - avdd12: LDO_AVDD12 { 148 - regulator-name = "avdd12"; 149 - regulator-min-microvolt = <900000>; 150 - regulator-max-microvolt = <1365000>; 151 - regulator-ramp-delay = <25000>; 152 - regulator-always-on; 153 - }; 154 - 155 - vddcama0: LDO_VDDCAMA0 { 156 - regulator-name = "vddcama0"; 157 - regulator-min-microvolt = <1200000>; 158 - regulator-max-microvolt = <3750000>; 159 - regulator-ramp-delay = <25000>; 160 - }; 161 - 162 - vddcama1: LDO_VDDCAMA1 { 163 - regulator-name = "vddcama1"; 164 - regulator-min-microvolt = <1200000>; 165 - regulator-max-microvolt = <3750000>; 166 - regulator-ramp-delay = <25000>; 167 - }; 168 - 169 - vddcammot: LDO_VDDCAMMOT { 170 - regulator-name = "vddcammot"; 171 - regulator-min-microvolt = <1200000>; 172 - regulator-max-microvolt = <3750000>; 173 - regulator-ramp-delay = <25000>; 174 - }; 175 - 176 - vddsim2: LDO_VDDSIM2 { 177 - regulator-name = "vddsim2"; 178 - regulator-min-microvolt = <1200000>; 179 - regulator-max-microvolt = <3750000>; 180 - regulator-ramp-delay = <25000>; 181 - }; 182 - 183 - vddemmccore: LDO_VDDEMMCCORE { 184 - regulator-name = "vddemmccore"; 185 - regulator-min-microvolt = <1200000>; 186 - regulator-max-microvolt = <3750000>; 187 - regulator-ramp-delay = <25000>; 188 - }; 189 - 190 - vddsdcore: LDO_VDDSDCORE { 191 - regulator-name = "vddsdcore"; 192 - regulator-min-microvolt = <1200000>; 193 - regulator-max-microvolt = <3750000>; 194 - regulator-ramp-delay = <25000>; 195 - }; 196 - 197 - vddsdio: LDO_VDDSDIO { 198 - regulator-name = "vddsdio"; 199 - regulator-min-microvolt = <1200000>; 200 - regulator-max-microvolt = <3750000>; 201 - regulator-ramp-delay = <25000>; 202 - }; 203 - 204 - vdd28: LDO_VDD28 { 205 - regulator-name = "vdd28"; 206 - regulator-min-microvolt = <1200000>; 207 - regulator-max-microvolt = <3750000>; 208 - regulator-ramp-delay = <25000>; 209 - regulator-always-on; 210 - }; 211 - 212 - vddwifipa: LDO_VDDWIFIPA { 213 - regulator-name = "vddwifipa"; 214 - regulator-min-microvolt = <1200000>; 215 - regulator-max-microvolt = <3750000>; 216 - regulator-ramp-delay = <25000>; 217 - }; 218 - 219 - vdd18_dcxo: LDO_VDD18_DCXO { 220 - regulator-name = "vdd18_dcxo"; 221 - regulator-min-microvolt = <1200000>; 222 - regulator-max-microvolt = <3750000>; 223 - regulator-ramp-delay = <25000>; 224 - regulator-always-on; 225 - }; 226 - 227 - vddusb33: LDO_VDDUSB33 { 228 - regulator-name = "vddusb33"; 229 - regulator-min-microvolt = <1200000>; 230 - regulator-max-microvolt = <3750000>; 231 - regulator-ramp-delay = <25000>; 232 - }; 233 - 234 - vddldo0: LDO_VDDLDO0 { 235 - regulator-name = "vddldo0"; 236 - regulator-min-microvolt = <1200000>; 237 - regulator-max-microvolt = <3750000>; 238 - regulator-ramp-delay = <25000>; 239 - }; 240 - 241 - vddldo1: LDO_VDDLDO1 { 242 - regulator-name = "vddldo1"; 243 - regulator-min-microvolt = <1200000>; 244 - regulator-max-microvolt = <3750000>; 245 - regulator-ramp-delay = <25000>; 246 - }; 247 - 248 - vddldo2: LDO_VDDLDO2 { 249 - regulator-name = "vddldo2"; 250 - regulator-min-microvolt = <1200000>; 251 - regulator-max-microvolt = <3750000>; 252 - regulator-ramp-delay = <25000>; 253 - }; 254 - 255 - vddkpled: LDO_VDDKPLED { 256 - regulator-name = "vddkpled"; 257 - regulator-min-microvolt = <1200000>; 258 - regulator-max-microvolt = <3750000>; 259 - regulator-ramp-delay = <25000>; 260 - }; 261 - }; 262 - }; 263 - };
-69
arch/arm64/boot/dts/sprd/ums512-1h10.dts
··· 1 - // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 - /* 3 - * Unisoc UMS512-1h10 boards DTS file 4 - * 5 - * Copyright (C) 2021, Unisoc Inc. 6 - */ 7 - 8 - /dts-v1/; 9 - 10 - #include <dt-bindings/gpio/gpio.h> 11 - #include "ums512.dtsi" 12 - #include "sc2730.dtsi" 13 - 14 - / { 15 - model = "Unisoc UMS512-1H10 Board"; 16 - 17 - compatible = "sprd,ums512-1h10", "sprd,ums512"; 18 - 19 - sprd,sc-id = <512 1 0x20000>; 20 - 21 - aliases { 22 - serial0 = &uart0; 23 - serial1 = &uart1; 24 - }; 25 - 26 - memory@80000000 { 27 - device_type = "memory"; 28 - reg = <0x0 0x80000000 0x0 0x80000000>; 29 - }; 30 - 31 - chosen { 32 - stdout-path = "serial1:115200n8"; 33 - bootargs = "earlycon"; 34 - }; 35 - }; 36 - 37 - &uart0 { 38 - status = "okay"; 39 - }; 40 - 41 - &uart1 { 42 - status = "okay"; 43 - }; 44 - 45 - /* SD card */ 46 - &sdio0 { 47 - status = "okay"; 48 - bus-width = <4>; 49 - no-sdio; 50 - no-mmc; 51 - sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>; 52 - sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>; 53 - sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>; 54 - sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>; 55 - vmmc-supply = <&vddsdcore>; 56 - vqmmc-supply = <&vddsdio>; 57 - sd-uhs-sdr104; 58 - sd-uhs-sdr50; 59 - }; 60 - 61 - /* EMMC storage */ 62 - &sdio3 { 63 - status = "okay"; 64 - bus-width = <8>; 65 - no-sdio; 66 - no-sd; 67 - non-removable; 68 - cap-mmc-hw-reset; 69 - };
-919
arch/arm64/boot/dts/sprd/ums512.dtsi
··· 1 - // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 - /* 3 - * Unisoc UMS512 SoC DTS file 4 - * 5 - * Copyright (C) 2021, Unisoc Inc. 6 - */ 7 - 8 - #include <dt-bindings/clock/sprd,ums512-clk.h> 9 - #include <dt-bindings/interrupt-controller/arm-gic.h> 10 - 11 - / { 12 - interrupt-parent = <&gic>; 13 - #address-cells = <2>; 14 - #size-cells = <2>; 15 - 16 - cpus { 17 - #address-cells = <2>; 18 - #size-cells = <0>; 19 - 20 - cpu-map { 21 - cluster0 { 22 - core0 { 23 - cpu = <&CPU0>; 24 - }; 25 - core1 { 26 - cpu = <&CPU1>; 27 - }; 28 - core2 { 29 - cpu = <&CPU2>; 30 - }; 31 - core3 { 32 - cpu = <&CPU3>; 33 - }; 34 - core4 { 35 - cpu = <&CPU4>; 36 - }; 37 - core5 { 38 - cpu = <&CPU5>; 39 - }; 40 - core6 { 41 - cpu = <&CPU6>; 42 - }; 43 - core7 { 44 - cpu = <&CPU7>; 45 - }; 46 - }; 47 - }; 48 - 49 - CPU0: cpu@0 { 50 - device_type = "cpu"; 51 - compatible = "arm,cortex-a55"; 52 - reg = <0x0 0x0>; 53 - enable-method = "psci"; 54 - cpu-idle-states = <&CORE_PD>; 55 - }; 56 - 57 - CPU1: cpu@100 { 58 - device_type = "cpu"; 59 - compatible = "arm,cortex-a55"; 60 - reg = <0x0 0x100>; 61 - enable-method = "psci"; 62 - cpu-idle-states = <&CORE_PD>; 63 - }; 64 - 65 - CPU2: cpu@200 { 66 - device_type = "cpu"; 67 - compatible = "arm,cortex-a55"; 68 - reg = <0x0 0x200>; 69 - enable-method = "psci"; 70 - cpu-idle-states = <&CORE_PD>; 71 - }; 72 - 73 - CPU3: cpu@300 { 74 - device_type = "cpu"; 75 - compatible = "arm,cortex-a55"; 76 - reg = <0x0 0x300>; 77 - enable-method = "psci"; 78 - cpu-idle-states = <&CORE_PD>; 79 - }; 80 - 81 - CPU4: cpu@400 { 82 - device_type = "cpu"; 83 - compatible = "arm,cortex-a55"; 84 - reg = <0x0 0x400>; 85 - enable-method = "psci"; 86 - cpu-idle-states = <&CORE_PD>; 87 - }; 88 - 89 - CPU5: cpu@500 { 90 - device_type = "cpu"; 91 - compatible = "arm,cortex-a55"; 92 - reg = <0x0 0x500>; 93 - enable-method = "psci"; 94 - cpu-idle-states = <&CORE_PD>; 95 - }; 96 - 97 - CPU6: cpu@600 { 98 - device_type = "cpu"; 99 - compatible = "arm,cortex-a55"; 100 - reg = <0x0 0x600>; 101 - enable-method = "psci"; 102 - cpu-idle-states = <&CORE_PD>; 103 - }; 104 - 105 - CPU7: cpu@700 { 106 - device_type = "cpu"; 107 - compatible = "arm,cortex-a55"; 108 - reg = <0x0 0x700>; 109 - enable-method = "psci"; 110 - cpu-idle-states = <&CORE_PD>; 111 - }; 112 - }; 113 - 114 - idle-states { 115 - entry-method = "psci"; 116 - CORE_PD: core-pd { 117 - compatible = "arm,idle-state"; 118 - entry-latency-us = <4000>; 119 - exit-latency-us = <4000>; 120 - min-residency-us = <10000>; 121 - local-timer-stop; 122 - arm,psci-suspend-param = <0x00010000>; 123 - }; 124 - }; 125 - 126 - psci { 127 - compatible = "arm,psci-0.2"; 128 - method = "smc"; 129 - }; 130 - 131 - timer { 132 - compatible = "arm,armv8-timer"; 133 - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ 134 - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ 135 - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ 136 - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ 137 - }; 138 - 139 - pmu { 140 - compatible = "arm,armv8-pmuv3"; 141 - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 142 - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 143 - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 144 - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 145 - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 146 - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 147 - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 148 - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 149 - }; 150 - 151 - soc: soc { 152 - compatible = "simple-bus"; 153 - #address-cells = <2>; 154 - #size-cells = <2>; 155 - ranges; 156 - 157 - gic: interrupt-controller@12000000 { 158 - compatible = "arm,gic-v3"; 159 - #interrupt-cells = <3>; 160 - #address-cells = <2>; 161 - #size-cells = <2>; 162 - ranges; 163 - redistributor-stride = <0x0 0x20000>; /* 128KB stride */ 164 - #redistributor-regions = <1>; 165 - interrupt-controller; 166 - reg = <0x0 0x12000000 0 0x20000>, /* GICD */ 167 - <0x0 0x12040000 0 0x100000>; /* GICR */ 168 - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 169 - }; 170 - 171 - ap_ahb_regs: syscon@20100000 { 172 - compatible = "sprd,ums512-glbregs", "syscon", 173 - "simple-mfd"; 174 - reg = <0 0x20100000 0 0x4000>; 175 - #address-cells = <1>; 176 - #size-cells = <1>; 177 - ranges = <0 0 0x20100000 0x4000>; 178 - 179 - apahb_gate: clock-controller@0 { 180 - compatible = "sprd,ums512-apahb-gate"; 181 - reg = <0x0 0x3000>; 182 - clocks = <&ext_26m>; 183 - clock-names = "ext-26m"; 184 - #clock-cells = <1>; 185 - }; 186 - }; 187 - 188 - pub_apb_regs: syscon@31050000 { 189 - compatible = "sprd,ums512-glbregs", "syscon", 190 - "simple-mfd"; 191 - reg = <0 0x31050000 0 0x9000>; 192 - }; 193 - 194 - top_dvfs_apb_regs: syscon@322a0000 { 195 - compatible = "sprd,ums512-glbregs", "syscon", 196 - "simple-mfd"; 197 - reg = <0 0x322a0000 0 0x8000>; 198 - }; 199 - 200 - ap_intc0_regs: syscon@32310000 { 201 - compatible = "sprd,ums512-glbregs", "syscon", 202 - "simple-mfd"; 203 - reg = <0 0x32310000 0 0x1000>; 204 - }; 205 - 206 - ap_intc1_regs: syscon@32320000 { 207 - compatible = "sprd,ums512-glbregs", "syscon", 208 - "simple-mfd"; 209 - reg = <0 0x32320000 0 0x1000>; 210 - }; 211 - 212 - ap_intc2_regs: syscon@32330000 { 213 - compatible = "sprd,ums512-glbregs", "syscon", 214 - "simple-mfd"; 215 - reg = <0 0x32330000 0 0x1000>; 216 - }; 217 - 218 - ap_intc3_regs: syscon@32340000 { 219 - compatible = "sprd,ums512-glbregs", "syscon", 220 - "simple-mfd"; 221 - reg = <0 0x32340000 0 0x1000>; 222 - }; 223 - 224 - ap_intc4_regs: syscon@32350000 { 225 - compatible = "sprd,ums512-glbregs", "syscon", 226 - "simple-mfd"; 227 - reg = <0 0x32350000 0 0x1000>; 228 - }; 229 - 230 - ap_intc5_regs: syscon@32360000 { 231 - compatible = "sprd,ums512-glbregs", "syscon", 232 - "simple-mfd"; 233 - reg = <0 0x32360000 0 0x1000>; 234 - }; 235 - 236 - anlg_phy_g0_regs: syscon@32390000 { 237 - compatible = "sprd,ums512-glbregs", "syscon", 238 - "simple-mfd"; 239 - reg = <0 0x32390000 0 0x3000>; 240 - #address-cells = <1>; 241 - #size-cells = <1>; 242 - ranges = <0 0 0x32390000 0x3000>; 243 - 244 - dpll0: clock-controller@0 { 245 - compatible = "sprd,ums512-g0-pll"; 246 - reg = <0x0 0x100>; 247 - #clock-cells = <1>; 248 - }; 249 - }; 250 - 251 - anlg_phy_g2_regs: syscon@323b0000 { 252 - compatible = "sprd,ums512-glbregs", "syscon", 253 - "simple-mfd"; 254 - reg = <0 0x323b0000 0 0x3000>; 255 - #address-cells = <1>; 256 - #size-cells = <1>; 257 - ranges = <0 0 0x323b0000 0x3000>; 258 - 259 - mpll1: clock-controller@0 { 260 - compatible = "sprd,ums512-g2-pll"; 261 - reg = <0x0 0x100>; 262 - #clock-cells = <1>; 263 - }; 264 - }; 265 - 266 - anlg_phy_g3_regs: syscon@323c0000 { 267 - compatible = "sprd,ums512-glbregs", "syscon", 268 - "simple-mfd"; 269 - reg = <0 0x323c0000 0 0x3000>; 270 - #address-cells = <1>; 271 - #size-cells = <1>; 272 - ranges = <0 0 0x323c0000 0x3000>; 273 - 274 - pll1: clock-controller@0 { 275 - compatible = "sprd,ums512-g3-pll"; 276 - reg = <0x0 0x3000>; 277 - clocks = <&ext_26m>; 278 - clock-names = "ext-26m"; 279 - #clock-cells = <1>; 280 - }; 281 - }; 282 - 283 - anlg_phy_gc_regs: syscon@323e0000 { 284 - compatible = "sprd,ums512-glbregs", "syscon", 285 - "simple-mfd"; 286 - reg = <0 0x323e0000 0 0x3000>; 287 - #address-cells = <1>; 288 - #size-cells = <1>; 289 - ranges = <0 0 0x323e0000 0x3000>; 290 - 291 - pll2: clock-controller@0 { 292 - compatible = "sprd,ums512-gc-pll"; 293 - reg = <0x0 0x100>; 294 - clock-names = "ext-26m"; 295 - #clock-cells = <1>; 296 - }; 297 - }; 298 - 299 - anlg_phy_g10_regs: syscon@323f0000 { 300 - compatible = "sprd,ums512-glbregs", "syscon", 301 - "simple-mfd"; 302 - reg = <0 0x323f0000 0 0x3000>; 303 - }; 304 - 305 - aon_apb_regs: syscon@327d0000 { 306 - compatible = "sprd,ums512-glbregs", "syscon", 307 - "simple-mfd"; 308 - reg = <0 0x327d0000 0 0x3000>; 309 - #address-cells = <1>; 310 - #size-cells = <1>; 311 - ranges = <0 0 0x327d0000 0x3000>; 312 - 313 - aonapb_gate: clock-controller@0 { 314 - compatible = "sprd,ums512-aon-gate"; 315 - reg = <0x0 0x3000>; 316 - clocks = <&ext_26m>; 317 - clock-names = "ext-26m"; 318 - #clock-cells = <1>; 319 - }; 320 - }; 321 - 322 - pmu_apb_regs: syscon@327e0000 { 323 - compatible = "sprd,ums512-glbregs", "syscon", 324 - "simple-mfd"; 325 - reg = <0 0x327e0000 0 0x3000>; 326 - #address-cells = <1>; 327 - #size-cells = <1>; 328 - ranges = <0 0 0x327e0000 0x3000>; 329 - 330 - pmu_gate: clock-controller@0 { 331 - compatible = "sprd,ums512-pmu-gate"; 332 - reg = <0x0 0x3000>; 333 - clocks = <&ext_26m>; 334 - clock-names = "ext-26m"; 335 - #clock-cells = <1>; 336 - }; 337 - }; 338 - 339 - audcp_apb_regs: syscon@3350d000 { 340 - compatible = "sprd,ums512-glbregs", "syscon", 341 - "simple-mfd"; 342 - reg = <0 0x3350d000 0 0x1000>; 343 - #address-cells = <1>; 344 - #size-cells = <1>; 345 - ranges = <0 0 0x3350d000 0x1000>; 346 - 347 - audcpapb_gate: clock-controller@0 { 348 - compatible = "sprd,ums512-audcpapb-gate"; 349 - reg = <0x0 0x300>; 350 - #clock-cells = <1>; 351 - }; 352 - }; 353 - 354 - audcp_ahb_regs: syscon@335e0000 { 355 - compatible = "sprd,ums512-glbregs", "syscon", 356 - "simple-mfd"; 357 - reg = <0 0x335e0000 0 0x1000>; 358 - #address-cells = <1>; 359 - #size-cells = <1>; 360 - ranges = <0 0 0x335e0000 0x1000>; 361 - 362 - audcpahb_gate: clock-controller@0 { 363 - compatible = "sprd,ums512-audcpahb-gate"; 364 - reg = <0x0 0x300>; 365 - #clock-cells = <1>; 366 - }; 367 - }; 368 - 369 - gpu_apb_regs: syscon@60100000 { 370 - compatible = "sprd,ums512-glbregs", "syscon", 371 - "simple-mfd"; 372 - reg = <0 0x60100000 0 0x3000>; 373 - #address-cells = <1>; 374 - #size-cells = <1>; 375 - ranges = <0 0 0x60100000 0x3000>; 376 - 377 - gpu_clk: clock-controller@0 { 378 - compatible = "sprd,ums512-gpu-clk"; 379 - clocks = <&ext_26m>; 380 - clock-names = "ext-26m"; 381 - reg = <0x0 0x100>; 382 - #clock-cells = <1>; 383 - }; 384 - }; 385 - 386 - gpu_dvfs_apb_regs: syscon@60110000 { 387 - compatible = "sprd,ums512-glbregs", "syscon", 388 - "simple-mfd"; 389 - reg = <0 0x60110000 0 0x3000>; 390 - }; 391 - 392 - mm_ahb_regs: syscon@62200000 { 393 - compatible = "sprd,ums512-glbregs", "syscon", 394 - "simple-mfd"; 395 - reg = <0 0x62200000 0 0x3000>; 396 - #address-cells = <1>; 397 - #size-cells = <1>; 398 - ranges = <0 0 0x62200000 0x3000>; 399 - 400 - mm_gate: clock-controller@0 { 401 - compatible = "sprd,ums512-mm-gate-clk"; 402 - reg = <0x0 0x3000>; 403 - #clock-cells = <1>; 404 - }; 405 - }; 406 - 407 - ap_apb_regs: syscon@71000000 { 408 - compatible = "sprd,ums512-glbregs", "syscon", 409 - "simple-mfd"; 410 - reg = <0 0x71000000 0 0x3000>; 411 - #address-cells = <1>; 412 - #size-cells = <1>; 413 - ranges = <0 0 0x71000000 0x3000>; 414 - 415 - apapb_gate: clock-controller@0 { 416 - compatible = "sprd,ums512-apapb-gate"; 417 - reg = <0x0 0x3000>; 418 - #clock-cells = <1>; 419 - }; 420 - }; 421 - 422 - ap_clk: clock-controller@20200000 { 423 - compatible = "sprd,ums512-ap-clk"; 424 - reg = <0 0x20200000 0 0x1000>; 425 - clocks = <&ext_26m>; 426 - clock-names = "ext-26m"; 427 - #clock-cells = <1>; 428 - }; 429 - 430 - aon_clk: clock-controller@32080000 { 431 - compatible = "sprd,ums512-aonapb-clk"; 432 - reg = <0 0x32080000 0 0x1000>; 433 - clocks = <&ext_26m>, <&ext_32k>, 434 - <&ext_4m>, <&rco_100m>; 435 - clock-names = "ext-26m", "ext-32k", 436 - "ext-4m", "rco-100m"; 437 - #clock-cells = <1>; 438 - }; 439 - 440 - mm_clk: clock-controller@62100000 { 441 - compatible = "sprd,ums512-mm-clk"; 442 - reg = <0 0x62100000 0 0x1000>; 443 - clocks = <&ext_26m>; 444 - clock-names = "ext-26m"; 445 - #clock-cells = <1>; 446 - }; 447 - 448 - /* SoC Funnel */ 449 - funnel@3c002000 { 450 - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 451 - reg = <0 0x3c002000 0 0x1000>; 452 - clocks = <&ext_26m>; 453 - clock-names = "apb_pclk"; 454 - 455 - out-ports { 456 - port { 457 - funnel_soc_out_port: endpoint { 458 - remote-endpoint = <&etb_in>; 459 - }; 460 - }; 461 - }; 462 - 463 - in-ports { 464 - #address-cells = <1>; 465 - #size-cells = <0>; 466 - 467 - port@1 { 468 - reg = <1>; 469 - funnel_soc_in_port: endpoint { 470 - remote-endpoint = 471 - <&funnel_corinth_out_port>; 472 - }; 473 - }; 474 - }; 475 - }; 476 - 477 - /* SoC ETF */ 478 - soc_etb: etb@3c003000 { 479 - compatible = "arm,coresight-tmc", "arm,primecell"; 480 - reg = <0 0x3c003000 0 0x1000>; 481 - clocks = <&ext_26m>; 482 - clock-names = "apb_pclk"; 483 - 484 - in-ports { 485 - port { 486 - etb_in: endpoint { 487 - remote-endpoint = 488 - <&funnel_soc_out_port>; 489 - }; 490 - }; 491 - }; 492 - }; 493 - 494 - /* AP-CPU Funnel for core3/4/5/7 */ 495 - funnel@3e001000 { 496 - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 497 - reg = <0 0x3e001000 0 0x1000>; 498 - clocks = <&ext_26m>; 499 - clock-names = "apb_pclk"; 500 - 501 - out-ports { 502 - port { 503 - funnel_corinth_lit_out_port: endpoint { 504 - remote-endpoint = 505 - <&corinth_etf_lit_in>; 506 - }; 507 - }; 508 - }; 509 - 510 - in-ports { 511 - #address-cells = <1>; 512 - #size-cells = <0>; 513 - 514 - port@0 { 515 - reg = <0>; 516 - funnel_core_in_port3: endpoint { 517 - remote-endpoint = <&etm3_out>; 518 - }; 519 - }; 520 - 521 - port@1 { 522 - reg = <1>; 523 - funnel_core_in_port4: endpoint { 524 - remote-endpoint = <&etm4_out>; 525 - }; 526 - }; 527 - 528 - port@2 { 529 - reg = <2>; 530 - funnel_core_in_port5: endpoint { 531 - remote-endpoint = <&etm5_out>; 532 - }; 533 - }; 534 - 535 - port@3 { 536 - reg = <3>; 537 - funnel_core_in_port7: endpoint { 538 - remote-endpoint = <&etm7_out>; 539 - }; 540 - }; 541 - }; 542 - }; 543 - 544 - /* AP-CPU ETF for little cores */ 545 - etf@3e002000 { 546 - compatible = "arm,coresight-tmc", "arm,primecell"; 547 - reg = <0 0x3e002000 0 0x1000>; 548 - clocks = <&ext_26m>; 549 - clock-names = "apb_pclk"; 550 - 551 - out-ports { 552 - port { 553 - corinth_etf_lit_out: endpoint { 554 - remote-endpoint = 555 - <&funnel_corinth_from_lit_in_port>; 556 - }; 557 - }; 558 - }; 559 - 560 - in-ports { 561 - port { 562 - corinth_etf_lit_in: endpoint { 563 - remote-endpoint = 564 - <&funnel_corinth_lit_out_port>; 565 - }; 566 - }; 567 - }; 568 - }; 569 - 570 - /* AP-CPU ETF for big cores */ 571 - etf@3e003000 { 572 - compatible = "arm,coresight-tmc", "arm,primecell"; 573 - reg = <0 0x3e003000 0 0x1000>; 574 - clocks = <&ext_26m>; 575 - clock-names = "apb_pclk"; 576 - 577 - out-ports { 578 - port { 579 - corinth_etf_big_out: endpoint { 580 - remote-endpoint = 581 - <&funnel_corinth_from_big_in_port>; 582 - }; 583 - }; 584 - }; 585 - 586 - in-ports { 587 - port { 588 - corinth_etf_big_in: endpoint { 589 - remote-endpoint = 590 - <&funnel_corinth_big_out_port>; 591 - }; 592 - }; 593 - }; 594 - }; 595 - 596 - /* Funnel to SoC */ 597 - funnel@3e004000 { 598 - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 599 - reg = <0 0x3e004000 0 0x1000>; 600 - clocks = <&ext_26m>; 601 - clock-names = "apb_pclk"; 602 - 603 - out-ports { 604 - port { 605 - funnel_corinth_out_port: endpoint { 606 - remote-endpoint = 607 - <&funnel_soc_in_port>; 608 - }; 609 - }; 610 - }; 611 - 612 - in-ports { 613 - #address-cells = <1>; 614 - #size-cells = <0>; 615 - 616 - port@0 { 617 - reg = <0>; 618 - funnel_corinth_from_lit_in_port: endpoint { 619 - remote-endpoint = <&corinth_etf_lit_out>; 620 - }; 621 - }; 622 - 623 - port@1 { 624 - reg = <1>; 625 - funnel_corinth_from_big_in_port: endpoint { 626 - remote-endpoint = <&corinth_etf_big_out>; 627 - }; 628 - }; 629 - }; 630 - }; 631 - 632 - /* AP-CPU Funnel for core0/1/2/6 */ 633 - funnel@3e005000 { 634 - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 635 - reg = <0 0x3e005000 0 0x1000>; 636 - clocks = <&ext_26m>; 637 - clock-names = "apb_pclk"; 638 - 639 - out-ports { 640 - port { 641 - funnel_corinth_big_out_port: endpoint { 642 - remote-endpoint = <&corinth_etf_big_in>; 643 - }; 644 - }; 645 - }; 646 - 647 - in-ports { 648 - #address-cells = <1>; 649 - #size-cells = <0>; 650 - 651 - port@0 { 652 - reg = <0>; 653 - funnel_core_in_port0: endpoint { 654 - remote-endpoint = <&etm0_out>; 655 - }; 656 - }; 657 - 658 - port@1 { 659 - reg = <1>; 660 - funnel_core_in_port1: endpoint { 661 - remote-endpoint = <&etm1_out>; 662 - }; 663 - }; 664 - 665 - port@2 { 666 - reg = <2>; 667 - funnel_core_in_port2: endpoint { 668 - remote-endpoint = <&etm2_out>; 669 - }; 670 - }; 671 - 672 - port@3 { 673 - reg = <3>; 674 - funnel_core_in_port6: endpoint { 675 - remote-endpoint = <&etm6_out>; 676 - }; 677 - }; 678 - }; 679 - }; 680 - 681 - etm0: etm@3f040000 { 682 - compatible = "arm,coresight-etm4x", "arm,primecell"; 683 - reg = <0 0x3f040000 0 0x1000>; 684 - cpu = <&CPU0>; 685 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 686 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 687 - 688 - out-ports { 689 - port { 690 - etm0_out: endpoint { 691 - remote-endpoint = 692 - <&funnel_core_in_port0>; 693 - }; 694 - }; 695 - }; 696 - }; 697 - 698 - etm1: etm@3f140000 { 699 - compatible = "arm,coresight-etm4x", "arm,primecell"; 700 - reg = <0 0x3f140000 0 0x1000>; 701 - cpu = <&CPU1>; 702 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 703 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 704 - 705 - out-ports { 706 - port { 707 - etm1_out: endpoint { 708 - remote-endpoint = 709 - <&funnel_core_in_port1>; 710 - }; 711 - }; 712 - }; 713 - }; 714 - 715 - etm2: etm@3f240000 { 716 - compatible = "arm,coresight-etm4x", "arm,primecell"; 717 - reg = <0 0x3f240000 0 0x1000>; 718 - cpu = <&CPU2>; 719 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 720 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 721 - 722 - out-ports { 723 - port { 724 - etm2_out: endpoint { 725 - remote-endpoint = 726 - <&funnel_core_in_port2>; 727 - }; 728 - }; 729 - }; 730 - }; 731 - 732 - etm3: etm@3f340000 { 733 - compatible = "arm,coresight-etm4x", "arm,primecell"; 734 - reg = <0 0x3f340000 0 0x1000>; 735 - cpu = <&CPU3>; 736 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 737 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 738 - 739 - out-ports { 740 - port { 741 - etm3_out: endpoint { 742 - remote-endpoint = 743 - <&funnel_core_in_port3>; 744 - }; 745 - }; 746 - }; 747 - }; 748 - 749 - etm4: etm@3f440000 { 750 - compatible = "arm,coresight-etm4x", "arm,primecell"; 751 - reg = <0 0x3f440000 0 0x1000>; 752 - cpu = <&CPU4>; 753 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 754 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 755 - 756 - out-ports { 757 - port { 758 - etm4_out: endpoint { 759 - remote-endpoint = 760 - <&funnel_core_in_port4>; 761 - }; 762 - }; 763 - }; 764 - }; 765 - 766 - etm5: etm@3f540000 { 767 - compatible = "arm,coresight-etm4x", "arm,primecell"; 768 - reg = <0 0x3f540000 0 0x1000>; 769 - cpu = <&CPU5>; 770 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 771 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 772 - 773 - out-ports { 774 - port { 775 - etm5_out: endpoint { 776 - remote-endpoint = 777 - <&funnel_core_in_port5>; 778 - }; 779 - }; 780 - }; 781 - }; 782 - 783 - etm6: etm@3f640000 { 784 - compatible = "arm,coresight-etm4x", "arm,primecell"; 785 - reg = <0 0x3f640000 0 0x1000>; 786 - cpu = <&CPU6>; 787 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 788 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 789 - 790 - out-ports { 791 - port { 792 - etm6_out: endpoint { 793 - remote-endpoint = 794 - <&funnel_core_in_port6>; 795 - }; 796 - }; 797 - }; 798 - }; 799 - 800 - etm7: etm@3f740000 { 801 - compatible = "arm,coresight-etm4x", "arm,primecell"; 802 - reg = <0 0x3f740000 0 0x1000>; 803 - cpu = <&CPU7>; 804 - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; 805 - clock-names = "apb_pclk", "clk_cs", "cs_src"; 806 - 807 - out-ports { 808 - port { 809 - etm7_out: endpoint { 810 - remote-endpoint = 811 - <&funnel_core_in_port7>; 812 - }; 813 - }; 814 - }; 815 - }; 816 - 817 - 818 - apb@70000000 { 819 - compatible = "simple-bus"; 820 - #address-cells = <1>; 821 - #size-cells = <1>; 822 - ranges = <0 0x0 0x70000000 0x10000000>; 823 - 824 - uart0: serial@0 { 825 - compatible = "sprd,ums512-uart", 826 - "sprd,sc9836-uart"; 827 - reg = <0x0 0x100>; 828 - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 829 - clocks = <&ext_26m>; 830 - status = "disabled"; 831 - }; 832 - 833 - uart1: serial@100000 { 834 - compatible = "sprd,ums512-uart", 835 - "sprd,sc9836-uart"; 836 - reg = <0x100000 0x100>; 837 - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 838 - clocks = <&ext_26m>; 839 - status = "disabled"; 840 - }; 841 - }; 842 - 843 - ap-apb { 844 - compatible = "simple-bus"; 845 - #address-cells = <2>; 846 - #size-cells = <2>; 847 - ranges; 848 - 849 - sdio0: sdio@71100000 { 850 - compatible = "sprd,sdhci-r11"; 851 - reg = <0 0x71100000 0 0x1000>; 852 - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 853 - clock-names = "sdio", "enable"; 854 - clocks = <&ap_clk CLK_SDIO0_2X>, 855 - <&apapb_gate CLK_SDIO0_EB>; 856 - assigned-clocks = <&ap_clk CLK_SDIO0_2X>; 857 - assigned-clock-parents = <&pll1 CLK_RPLL>; 858 - status = "disabled"; 859 - }; 860 - 861 - sdio3: sdio@71400000 { 862 - compatible = "sprd,sdhci-r11"; 863 - reg = <0 0x71400000 0 0x1000>; 864 - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 865 - clock-names = "sdio", "enable"; 866 - clocks = <&ap_clk CLK_EMMC_2X>, 867 - <&apapb_gate CLK_EMMC_EB>; 868 - assigned-clocks = <&ap_clk CLK_EMMC_2X>; 869 - assigned-clock-parents = <&pll1 CLK_RPLL>; 870 - status = "disabled"; 871 - }; 872 - }; 873 - 874 - aon { 875 - compatible = "simple-bus"; 876 - #address-cells = <2>; 877 - #size-cells = <2>; 878 - ranges; 879 - 880 - adi_bus: spi@32100000 { 881 - compatible = "sprd,ums512-adi"; 882 - reg = <0 0x32100000 0 0x100000>; 883 - #address-cells = <1>; 884 - #size-cells = <0>; 885 - sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>, 886 - <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>, 887 - <35 0x19b8>, <39 0x19ac>; 888 - }; 889 - }; 890 - }; 891 - 892 - ext_26m: ext-26m { 893 - compatible = "fixed-clock"; 894 - #clock-cells = <0>; 895 - clock-frequency = <26000000>; 896 - clock-output-names = "ext-26m"; 897 - }; 898 - 899 - ext_32k: ext-32k { 900 - compatible = "fixed-clock"; 901 - #clock-cells = <0>; 902 - clock-frequency = <32768>; 903 - clock-output-names = "ext-32k"; 904 - }; 905 - 906 - ext_4m: ext-4m { 907 - compatible = "fixed-clock"; 908 - #clock-cells = <0>; 909 - clock-frequency = <4000000>; 910 - clock-output-names = "ext-4m"; 911 - }; 912 - 913 - rco_100m: rco-100m { 914 - compatible = "fixed-clock"; 915 - #clock-cells = <0>; 916 - clock-frequency = <100000000>; 917 - clock-output-names = "rco-100m"; 918 - }; 919 - };