drm/amd/display: Add NBIO reg offsets to DC

[Why&How]
Add a field to store the NBIO IP offset for use with runtime offset
calculation

Reviewed-by: Rodrigo Siqueira <[e-mail]>
Acked-by: Solomon Chiu <[e-mail]>
Signed-off-by: Aurabindo Pillai <[e-mail]>
Tested-by: Daniel Wheeler <[e-mail]>
Signed-off-by: Alex Deucher <[e-mail]>

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

···
 	init_data.flags.enable_mipi_converter_optimization = true;
 
 	init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
+	init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
 
 	INIT_LIST_HEAD(&adev->dm.da_list);
 

drivers/gpu/drm/amd/display/dc/core/dc.c

···
 	dc_ctx->dc_stream_id_count = 0;
 	dc_ctx->dce_environment = init_params->dce_environment;
 	dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
+	dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
 
 	/* Create logger */
 
···
 	}
 
 	dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
+	dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
 
 	/* Populate versioning information */
 	dc->versions.dc_ver = DC_VER;

drivers/gpu/drm/amd/display/dc/dc.h

···
 	struct vm_helper *vm_helper;
 
 	uint32_t *dcn_reg_offsets;
+	uint32_t *nbio_reg_offsets;
 };
 
 enum frame_buffer_mode {
···
 	 * before them.
 	 */
 	uint32_t *dcn_reg_offsets;
+	uint32_t *nbio_reg_offsets;
 };
 
 struct dc_callback_init {

drivers/gpu/drm/amd/display/dc/dc_types.h

···
 	struct cp_psp cp_psp;
 #endif
 	uint32_t *dcn_reg_offsets;
+	uint32_t *nbio_reg_offsets;
 };
 
 /* DSC DPCD capabilities */