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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
mtd: nand/fsmc: Remove sparse warnings and errors
This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va
[...]
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
authored by
Vipin Kumar
and committed by
David Woodhouse
2a5dbead
4774fb0a
+109
-121
+45
-46
drivers/mtd/nand/fsmc_nand.c
+45
-46
drivers/mtd/nand/fsmc_nand.c
···
360
360
struct nand_chip *this = mtd->priv;
361
361
struct fsmc_nand_data *host = container_of(mtd,
362
362
struct fsmc_nand_data, mtd);
363
-
struct fsmc_regs *regs = host->regs_va;
363
+
void *__iomem *regs = host->regs_va;
364
364
unsigned int bank = host->bank;
365
365
366
366
if (ctrl & NAND_CTRL_CHANGE) {
367
+
u32 pc;
368
+
367
369
if (ctrl & NAND_CLE) {
368
-
this->IO_ADDR_R = (void __iomem *)host->cmd_va;
369
-
this->IO_ADDR_W = (void __iomem *)host->cmd_va;
370
+
this->IO_ADDR_R = host->cmd_va;
371
+
this->IO_ADDR_W = host->cmd_va;
370
372
} else if (ctrl & NAND_ALE) {
371
-
this->IO_ADDR_R = (void __iomem *)host->addr_va;
372
-
this->IO_ADDR_W = (void __iomem *)host->addr_va;
373
+
this->IO_ADDR_R = host->addr_va;
374
+
this->IO_ADDR_W = host->addr_va;
373
375
} else {
374
-
this->IO_ADDR_R = (void __iomem *)host->data_va;
375
-
this->IO_ADDR_W = (void __iomem *)host->data_va;
376
+
this->IO_ADDR_R = host->data_va;
377
+
this->IO_ADDR_W = host->data_va;
376
378
}
377
379
378
-
if (ctrl & NAND_NCE) {
379
-
writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE,
380
-
®s->bank_regs[bank].pc);
381
-
} else {
382
-
writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE,
383
-
®s->bank_regs[bank].pc);
384
-
}
380
+
pc = readl(FSMC_NAND_REG(regs, bank, PC));
381
+
if (ctrl & NAND_NCE)
382
+
pc |= FSMC_ENABLE;
383
+
else
384
+
pc &= ~FSMC_ENABLE;
385
+
writel(pc, FSMC_NAND_REG(regs, bank, PC));
385
386
}
386
387
387
388
mb();
···
397
396
* This routine initializes timing parameters related to NAND memory access in
398
397
* FSMC registers
399
398
*/
400
-
static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
399
+
static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
401
400
uint32_t busw, struct fsmc_nand_timings *timings)
402
401
{
403
402
uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
···
425
424
tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
426
425
427
426
if (busw)
428
-
writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc);
427
+
writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
429
428
else
430
-
writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc);
429
+
writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
431
430
432
-
writel(readl(®s->bank_regs[bank].pc) | tclr | tar,
433
-
®s->bank_regs[bank].pc);
434
-
writel(thiz | thold | twait | tset, ®s->bank_regs[bank].comm);
435
-
writel(thiz | thold | twait | tset, ®s->bank_regs[bank].attrib);
431
+
writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
432
+
FSMC_NAND_REG(regs, bank, PC));
433
+
writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
434
+
writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
436
435
}
437
436
438
437
/*
···
442
441
{
443
442
struct fsmc_nand_data *host = container_of(mtd,
444
443
struct fsmc_nand_data, mtd);
445
-
struct fsmc_regs *regs = host->regs_va;
444
+
void __iomem *regs = host->regs_va;
446
445
uint32_t bank = host->bank;
447
446
448
-
writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
449
-
®s->bank_regs[bank].pc);
450
-
writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN,
451
-
®s->bank_regs[bank].pc);
452
-
writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN,
453
-
®s->bank_regs[bank].pc);
447
+
writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
448
+
FSMC_NAND_REG(regs, bank, PC));
449
+
writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
450
+
FSMC_NAND_REG(regs, bank, PC));
451
+
writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
452
+
FSMC_NAND_REG(regs, bank, PC));
454
453
}
455
454
456
455
/*
···
463
462
{
464
463
struct fsmc_nand_data *host = container_of(mtd,
465
464
struct fsmc_nand_data, mtd);
466
-
struct fsmc_regs *regs = host->regs_va;
465
+
void __iomem *regs = host->regs_va;
467
466
uint32_t bank = host->bank;
468
467
uint32_t ecc_tmp;
469
468
unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
470
469
471
470
do {
472
-
if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY)
471
+
if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
473
472
break;
474
473
else
475
474
cond_resched();
···
480
479
return -ETIMEDOUT;
481
480
}
482
481
483
-
ecc_tmp = readl(®s->bank_regs[bank].ecc1);
482
+
ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
484
483
ecc[0] = (uint8_t) (ecc_tmp >> 0);
485
484
ecc[1] = (uint8_t) (ecc_tmp >> 8);
486
485
ecc[2] = (uint8_t) (ecc_tmp >> 16);
487
486
ecc[3] = (uint8_t) (ecc_tmp >> 24);
488
487
489
-
ecc_tmp = readl(®s->bank_regs[bank].ecc2);
488
+
ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
490
489
ecc[4] = (uint8_t) (ecc_tmp >> 0);
491
490
ecc[5] = (uint8_t) (ecc_tmp >> 8);
492
491
ecc[6] = (uint8_t) (ecc_tmp >> 16);
493
492
ecc[7] = (uint8_t) (ecc_tmp >> 24);
494
493
495
-
ecc_tmp = readl(®s->bank_regs[bank].ecc3);
494
+
ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
496
495
ecc[8] = (uint8_t) (ecc_tmp >> 0);
497
496
ecc[9] = (uint8_t) (ecc_tmp >> 8);
498
497
ecc[10] = (uint8_t) (ecc_tmp >> 16);
499
498
ecc[11] = (uint8_t) (ecc_tmp >> 24);
500
499
501
-
ecc_tmp = readl(®s->bank_regs[bank].sts);
500
+
ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
502
501
ecc[12] = (uint8_t) (ecc_tmp >> 16);
503
502
504
503
return 0;
···
514
513
{
515
514
struct fsmc_nand_data *host = container_of(mtd,
516
515
struct fsmc_nand_data, mtd);
517
-
struct fsmc_regs *regs = host->regs_va;
516
+
void __iomem *regs = host->regs_va;
518
517
uint32_t bank = host->bank;
519
518
uint32_t ecc_tmp;
520
519
521
-
ecc_tmp = readl(®s->bank_regs[bank].ecc1);
520
+
ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
522
521
ecc[0] = (uint8_t) (ecc_tmp >> 0);
523
522
ecc[1] = (uint8_t) (ecc_tmp >> 8);
524
523
ecc[2] = (uint8_t) (ecc_tmp >> 16);
···
772
771
struct fsmc_nand_data *host = container_of(mtd,
773
772
struct fsmc_nand_data, mtd);
774
773
struct nand_chip *chip = mtd->priv;
775
-
struct fsmc_regs *regs = host->regs_va;
774
+
void __iomem *regs = host->regs_va;
776
775
unsigned int bank = host->bank;
777
776
uint32_t err_idx[8];
778
777
uint32_t num_err, i;
779
778
uint32_t ecc1, ecc2, ecc3, ecc4;
780
779
781
-
num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF;
780
+
num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
782
781
783
782
/* no bit flipping */
784
783
if (likely(num_err == 0))
···
821
820
* uint64_t array and error offset indexes are populated in err_idx
822
821
* array
823
822
*/
824
-
ecc1 = readl(®s->bank_regs[bank].ecc1);
825
-
ecc2 = readl(®s->bank_regs[bank].ecc2);
826
-
ecc3 = readl(®s->bank_regs[bank].ecc3);
827
-
ecc4 = readl(®s->bank_regs[bank].sts);
823
+
ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
824
+
ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
825
+
ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
826
+
ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
828
827
829
828
err_idx[0] = (ecc1 >> 0) & 0x1FFF;
830
829
err_idx[1] = (ecc1 >> 13) & 0x1FFF;
···
864
863
struct fsmc_nand_data *host;
865
864
struct mtd_info *mtd;
866
865
struct nand_chip *nand;
867
-
struct fsmc_regs *regs;
868
866
struct resource *res;
869
867
dma_cap_mask_t mask;
870
868
int ret = 0;
···
976
976
if (host->mode == USE_DMA_ACCESS)
977
977
init_completion(&host->dma_access_complete);
978
978
979
-
regs = host->regs_va;
980
-
981
979
/* Link all private pointers */
982
980
mtd = &host->mtd;
983
981
nand = &host->nand;
···
1025
1027
break;
1026
1028
}
1027
1029
1028
-
fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
1030
+
fsmc_nand_setup(host->regs_va, host->bank,
1031
+
nand->options & NAND_BUSWIDTH_16,
1029
1032
host->dev_timings);
1030
1033
1031
1034
if (AMBA_REV_BITS(host->pid) >= 8) {
+64
-75
include/linux/mtd/fsmc.h
+64
-75
include/linux/mtd/fsmc.h
···
32
32
#define FSMC_FLASH_WIDTH8 1
33
33
#define FSMC_FLASH_WIDTH16 2
34
34
35
-
struct fsmc_nor_bank_regs {
36
-
uint32_t ctrl;
37
-
uint32_t ctrl_tim;
38
-
};
35
+
/* fsmc controller registers for NOR flash */
36
+
#define CTRL 0x0
37
+
/* ctrl register definitions */
38
+
#define BANK_ENABLE (1 << 0)
39
+
#define MUXED (1 << 1)
40
+
#define NOR_DEV (2 << 2)
41
+
#define WIDTH_8 (0 << 4)
42
+
#define WIDTH_16 (1 << 4)
43
+
#define RSTPWRDWN (1 << 6)
44
+
#define WPROT (1 << 7)
45
+
#define WRT_ENABLE (1 << 12)
46
+
#define WAIT_ENB (1 << 13)
39
47
40
-
/* ctrl register definitions */
41
-
#define BANK_ENABLE (1 << 0)
42
-
#define MUXED (1 << 1)
43
-
#define NOR_DEV (2 << 2)
44
-
#define WIDTH_8 (0 << 4)
45
-
#define WIDTH_16 (1 << 4)
46
-
#define RSTPWRDWN (1 << 6)
47
-
#define WPROT (1 << 7)
48
-
#define WRT_ENABLE (1 << 12)
49
-
#define WAIT_ENB (1 << 13)
48
+
#define CTRL_TIM 0x4
49
+
/* ctrl_tim register definitions */
50
50
51
-
/* ctrl_tim register definitions */
52
-
53
-
struct fsmc_nand_bank_regs {
54
-
uint32_t pc;
55
-
uint32_t sts;
56
-
uint32_t comm;
57
-
uint32_t attrib;
58
-
uint32_t ioata;
59
-
uint32_t ecc1;
60
-
uint32_t ecc2;
61
-
uint32_t ecc3;
62
-
};
63
-
51
+
#define FSMC_NOR_BANK_SZ 0x8
64
52
#define FSMC_NOR_REG_SIZE 0x40
65
53
66
-
struct fsmc_regs {
67
-
struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
68
-
uint8_t reserved_1[0x40 - 0x20];
69
-
struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
70
-
uint8_t reserved_2[0xfe0 - 0xc0];
71
-
uint32_t peripid0; /* 0xfe0 */
72
-
uint32_t peripid1; /* 0xfe4 */
73
-
uint32_t peripid2; /* 0xfe8 */
74
-
uint32_t peripid3; /* 0xfec */
75
-
uint32_t pcellid0; /* 0xff0 */
76
-
uint32_t pcellid1; /* 0xff4 */
77
-
uint32_t pcellid2; /* 0xff8 */
78
-
uint32_t pcellid3; /* 0xffc */
79
-
};
54
+
#define FSMC_NOR_REG(base, bank, reg) (base + \
55
+
FSMC_NOR_BANK_SZ * (bank) + \
56
+
reg)
57
+
58
+
/* fsmc controller registers for NAND flash */
59
+
#define PC 0x00
60
+
/* pc register definitions */
61
+
#define FSMC_RESET (1 << 0)
62
+
#define FSMC_WAITON (1 << 1)
63
+
#define FSMC_ENABLE (1 << 2)
64
+
#define FSMC_DEVTYPE_NAND (1 << 3)
65
+
#define FSMC_DEVWID_8 (0 << 4)
66
+
#define FSMC_DEVWID_16 (1 << 4)
67
+
#define FSMC_ECCEN (1 << 6)
68
+
#define FSMC_ECCPLEN_512 (0 << 7)
69
+
#define FSMC_ECCPLEN_256 (1 << 7)
70
+
#define FSMC_TCLR_1 (1)
71
+
#define FSMC_TCLR_SHIFT (9)
72
+
#define FSMC_TCLR_MASK (0xF)
73
+
#define FSMC_TAR_1 (1)
74
+
#define FSMC_TAR_SHIFT (13)
75
+
#define FSMC_TAR_MASK (0xF)
76
+
#define STS 0x04
77
+
/* sts register definitions */
78
+
#define FSMC_CODE_RDY (1 << 15)
79
+
#define COMM 0x08
80
+
/* comm register definitions */
81
+
#define FSMC_TSET_0 0
82
+
#define FSMC_TSET_SHIFT 0
83
+
#define FSMC_TSET_MASK 0xFF
84
+
#define FSMC_TWAIT_6 6
85
+
#define FSMC_TWAIT_SHIFT 8
86
+
#define FSMC_TWAIT_MASK 0xFF
87
+
#define FSMC_THOLD_4 4
88
+
#define FSMC_THOLD_SHIFT 16
89
+
#define FSMC_THOLD_MASK 0xFF
90
+
#define FSMC_THIZ_1 1
91
+
#define FSMC_THIZ_SHIFT 24
92
+
#define FSMC_THIZ_MASK 0xFF
93
+
#define ATTRIB 0x0C
94
+
#define IOATA 0x10
95
+
#define ECC1 0x14
96
+
#define ECC2 0x18
97
+
#define ECC3 0x1C
98
+
#define FSMC_NAND_BANK_SZ 0x20
99
+
100
+
#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
101
+
(FSMC_NAND_BANK_SZ * (bank)) + \
102
+
reg)
80
103
81
104
#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
82
-
83
-
/* pc register definitions */
84
-
#define FSMC_RESET (1 << 0)
85
-
#define FSMC_WAITON (1 << 1)
86
-
#define FSMC_ENABLE (1 << 2)
87
-
#define FSMC_DEVTYPE_NAND (1 << 3)
88
-
#define FSMC_DEVWID_8 (0 << 4)
89
-
#define FSMC_DEVWID_16 (1 << 4)
90
-
#define FSMC_ECCEN (1 << 6)
91
-
#define FSMC_ECCPLEN_512 (0 << 7)
92
-
#define FSMC_ECCPLEN_256 (1 << 7)
93
-
#define FSMC_TCLR_1 (1)
94
-
#define FSMC_TCLR_SHIFT (9)
95
-
#define FSMC_TCLR_MASK (0xF)
96
-
#define FSMC_TAR_1 (1)
97
-
#define FSMC_TAR_SHIFT (13)
98
-
#define FSMC_TAR_MASK (0xF)
99
-
100
-
/* sts register definitions */
101
-
#define FSMC_CODE_RDY (1 << 15)
102
-
103
-
/* comm register definitions */
104
-
#define FSMC_TSET_0 0
105
-
#define FSMC_TSET_SHIFT 0
106
-
#define FSMC_TSET_MASK 0xFF
107
-
#define FSMC_TWAIT_6 6
108
-
#define FSMC_TWAIT_SHIFT 8
109
-
#define FSMC_TWAIT_MASK 0xFF
110
-
#define FSMC_THOLD_4 4
111
-
#define FSMC_THOLD_SHIFT 16
112
-
#define FSMC_THOLD_MASK 0xFF
113
-
#define FSMC_THIZ_1 1
114
-
#define FSMC_THIZ_SHIFT 24
115
-
#define FSMC_THIZ_MASK 0xFF
116
105
117
106
/*
118
107
* There are 13 bytes of ecc for every 512 byte block in FSMC version 8