powerpc/8xx: Remove CPU6 ERRATA Workaround

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

CPU6 ERRATA affects only MPC860 revisions prior to C.0. Manufacturing
of those revisiosn was stopped in 1999-2000.
Therefore, it has been almost 20 years since this ERRATA has been
fixed in the silicon.

This patch removes the workaround for that ERRATA.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

authored by

Christophe Leroy and committed by

Michael Ellerman 8 years ago 2a45addd 9a3b849b

+12 -137

4 changed files

expand all

arch

powerpc

configs

mpc866_ads_defconfig

include

asm

reg_8xx.h

kernel

head_8xx.S

platforms

8xx

Kconfig

-1

arch/powerpc/configs/mpc866_ads_defconfig

··· 13 13 CONFIG_PARTITION_ADVANCED=y 14 14 CONFIG_MPC86XADS=y 15 15 CONFIG_8xx_COPYBACK=y 16 - CONFIG_8xx_CPU6=y 17 16 CONFIG_GEN_RTC=y 18 17 CONFIG_HZ_1000=y 19 18 CONFIG_MATH_EMULATION=y

-82

arch/powerpc/include/asm/reg_8xx.h

··· 66 66 #define DC_DFWT 0x40000000 /* Data cache is forced write through */ 67 67 #define DC_LES 0x20000000 /* Caches are little endian mode */ 68 68 69 - #ifdef CONFIG_8xx_CPU6 70 - #define do_mtspr_cpu6(rn, rn_addr, v) \ 71 - do { \ 72 - int _reg_cpu6 = rn_addr, _tmp_cpu6; \ 73 - asm volatile("stw %0, %1;" \ 74 - "lwz %0, %1;" \ 75 - "mtspr " __stringify(rn) ",%2" : \ 76 - : "r" (_reg_cpu6), "m"(_tmp_cpu6), \ 77 - "r" ((unsigned long)(v)) \ 78 - : "memory"); \ 79 - } while (0) 80 - 81 - #define do_mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ 82 - : "r" ((unsigned long)(v)) \ 83 - : "memory") 84 - #define mtspr(rn, v) \ 85 - do { \ 86 - if (rn == SPRN_IMMR) \ 87 - do_mtspr_cpu6(rn, 0x3d30, v); \ 88 - else if (rn == SPRN_IC_CST) \ 89 - do_mtspr_cpu6(rn, 0x2110, v); \ 90 - else if (rn == SPRN_IC_ADR) \ 91 - do_mtspr_cpu6(rn, 0x2310, v); \ 92 - else if (rn == SPRN_IC_DAT) \ 93 - do_mtspr_cpu6(rn, 0x2510, v); \ 94 - else if (rn == SPRN_DC_CST) \ 95 - do_mtspr_cpu6(rn, 0x3110, v); \ 96 - else if (rn == SPRN_DC_ADR) \ 97 - do_mtspr_cpu6(rn, 0x3310, v); \ 98 - else if (rn == SPRN_DC_DAT) \ 99 - do_mtspr_cpu6(rn, 0x3510, v); \ 100 - else if (rn == SPRN_MI_CTR) \ 101 - do_mtspr_cpu6(rn, 0x2180, v); \ 102 - else if (rn == SPRN_MI_AP) \ 103 - do_mtspr_cpu6(rn, 0x2580, v); \ 104 - else if (rn == SPRN_MI_EPN) \ 105 - do_mtspr_cpu6(rn, 0x2780, v); \ 106 - else if (rn == SPRN_MI_TWC) \ 107 - do_mtspr_cpu6(rn, 0x2b80, v); \ 108 - else if (rn == SPRN_MI_RPN) \ 109 - do_mtspr_cpu6(rn, 0x2d80, v); \ 110 - else if (rn == SPRN_MI_CAM) \ 111 - do_mtspr_cpu6(rn, 0x2190, v); \ 112 - else if (rn == SPRN_MI_RAM0) \ 113 - do_mtspr_cpu6(rn, 0x2390, v); \ 114 - else if (rn == SPRN_MI_RAM1) \ 115 - do_mtspr_cpu6(rn, 0x2590, v); \ 116 - else if (rn == SPRN_MD_CTR) \ 117 - do_mtspr_cpu6(rn, 0x3180, v); \ 118 - else if (rn == SPRN_M_CASID) \ 119 - do_mtspr_cpu6(rn, 0x3380, v); \ 120 - else if (rn == SPRN_MD_AP) \ 121 - do_mtspr_cpu6(rn, 0x3580, v); \ 122 - else if (rn == SPRN_MD_EPN) \ 123 - do_mtspr_cpu6(rn, 0x3780, v); \ 124 - else if (rn == SPRN_M_TWB) \ 125 - do_mtspr_cpu6(rn, 0x3980, v); \ 126 - else if (rn == SPRN_MD_TWC) \ 127 - do_mtspr_cpu6(rn, 0x3b80, v); \ 128 - else if (rn == SPRN_MD_RPN) \ 129 - do_mtspr_cpu6(rn, 0x3d80, v); \ 130 - else if (rn == SPRN_M_TW) \ 131 - do_mtspr_cpu6(rn, 0x3f80, v); \ 132 - else if (rn == SPRN_MD_CAM) \ 133 - do_mtspr_cpu6(rn, 0x3190, v); \ 134 - else if (rn == SPRN_MD_RAM0) \ 135 - do_mtspr_cpu6(rn, 0x3390, v); \ 136 - else if (rn == SPRN_MD_RAM1) \ 137 - do_mtspr_cpu6(rn, 0x3590, v); \ 138 - else if (rn == SPRN_DEC) \ 139 - do_mtspr_cpu6(rn, 0x2c00, v); \ 140 - else if (rn == SPRN_TBWL) \ 141 - do_mtspr_cpu6(rn, 0x3880, v); \ 142 - else if (rn == SPRN_TBWU) \ 143 - do_mtspr_cpu6(rn, 0x3a80, v); \ 144 - else if (rn == SPRN_DPDR) \ 145 - do_mtspr_cpu6(rn, 0x2d30, v); \ 146 - else \ 147 - do_mtspr(rn, v); \ 148 - } while (0) 149 - #endif 150 - 151 69 #endif /* _ASM_POWERPC_REG_8xx_H */

+12 -42

arch/powerpc/kernel/head_8xx.S

··· 33 33 #include <asm/fixmap.h> 34 34 #include <asm/export.h> 35 35 36 - /* Macro to make the code more readable. */ 37 - #ifdef CONFIG_8xx_CPU6 38 - #define SPRN_MI_TWC_ADDR 0x2b80 39 - #define SPRN_MI_RPN_ADDR 0x2d80 40 - #define SPRN_MD_TWC_ADDR 0x3b80 41 - #define SPRN_MD_RPN_ADDR 0x3d80 42 - 43 - #define MTSPR_CPU6(spr, reg, treg) \ 44 - li treg, spr##_ADDR; \ 45 - stw treg, 12(r0); \ 46 - lwz treg, 12(r0); \ 47 - mtspr spr, reg 48 - #else 49 - #define MTSPR_CPU6(spr, reg, treg) \ 50 - mtspr spr, reg 51 - #endif 52 - 53 36 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000 54 37 /* By simply checking Address >= 0x80000000, we know if its a kernel address */ 55 38 #define SIMPLE_KERNEL_ADDRESS 1 ··· 309 326 #endif 310 327 311 328 InstructionTLBMiss: 312 - #if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 329 + #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 313 330 mtspr SPRN_SPRG_SCRATCH2, r3 314 331 #endif 315 332 EXCEPTION_PROLOG_0 ··· 376 393 /* Insert the APG into the TWC from the Linux PTE. */ 377 394 rlwimi r11, r10, 0, 25, 26 378 395 /* Load the MI_TWC with the attributes for this "segment." */ 379 - MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ 396 + mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 380 397 381 398 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES) 382 399 rlwimi r10, r11, 1, MI_SPS16K ··· 398 415 #else 399 416 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */ 400 417 #endif 401 - MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ 418 + mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 402 419 403 420 /* Restore registers */ 404 - #if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 421 + #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) 405 422 mfspr r3, SPRN_SPRG_SCRATCH2 406 423 #endif 407 424 EXCEPTION_EPILOG_0 ··· 495 512 * It is bit 25 in the Linux PTE and bit 30 in the TWC 496 513 */ 497 514 rlwimi r11, r10, 32-5, 30, 30 498 - MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 515 + mtspr SPRN_MD_TWC, r11 499 516 500 517 /* In 4k pages mode, SPS (bit 28) in RPN must match PS[1] (bit 29) 501 518 * In 16k pages mode, SPS is always 1 */ ··· 529 546 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 530 547 #endif 531 548 rlwimi r10, r11, 0, 20, 20 /* clear 20 */ 532 - MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ 549 + mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 533 550 534 551 /* Restore registers */ 535 552 mfspr r3, SPRN_SPRG_SCRATCH2 ··· 667 684 mtcr r3 668 685 /* Set 512k byte guarded page and mark it valid */ 669 686 li r10, MD_PS512K | MD_GUARDED | MD_SVALID 670 - MTSPR_CPU6(SPRN_MD_TWC, r10, r11) 687 + mtspr SPRN_MD_TWC, r10 671 688 mfspr r10, SPRN_IMMR /* Get current IMMR */ 672 689 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ 673 690 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 674 691 _PAGE_PRESENT | _PAGE_NO_CACHE 675 - MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 692 + mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 676 693 677 694 li r11, RPN_PATTERN 678 695 mtspr SPRN_DAR, r11 /* Tag DAR */ ··· 684 701 mtcr r3 685 702 /* Set 8M byte page and mark it valid */ 686 703 li r11, MD_PS8MEG | MD_SVALID 687 - MTSPR_CPU6(SPRN_MD_TWC, r11, r3) 704 + mtspr SPRN_MD_TWC, r11 688 705 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 689 706 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 690 707 _PAGE_PRESENT 691 - MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */ 708 + mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 692 709 693 710 li r11, RPN_PATTERN 694 711 mtspr SPRN_DAR, r11 /* Tag DAR */ ··· 701 718 mtcr r3 702 719 /* Set 8M byte page and mark it valid */ 703 720 li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC 704 - MTSPR_CPU6(SPRN_MI_TWC, r11, r3) 721 + mtspr SPRN_MI_TWC, r11 705 722 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */ 706 723 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ 707 724 _PAGE_PRESENT 708 - MTSPR_CPU6(SPRN_MI_RPN, r10, r11) /* Update TLB entry */ 725 + mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 709 726 710 727 mfspr r3, SPRN_SPRG_SCRATCH2 711 728 EXCEPTION_EPILOG_0 ··· 916 933 */ 917 934 lis r6, swapper_pg_dir@ha 918 935 tophys(r6,r6) 919 - #ifdef CONFIG_8xx_CPU6 920 - lis r4, cpu6_errata_word@h 921 - ori r4, r4, cpu6_errata_word@l 922 - li r3, 0x3f80 923 - stw r3, 12(r4) 924 - lwz r3, 12(r4) 925 - #endif 926 936 mtspr SPRN_M_TW, r6 927 937 lis r4,2f@h 928 938 ori r4,r4,2f@l ··· 1069 1093 */ 1070 1094 abatron_pteptrs: 1071 1095 .space 8 1072 - 1073 - #ifdef CONFIG_8xx_CPU6 1074 - .globl cpu6_errata_word 1075 - cpu6_errata_word: 1076 - .space 16 1077 - #endif 1078 1096 1079 1097 #ifdef CONFIG_PPC_8xx_PERF_EVENT 1080 1098 .globl itlb_miss_counter

-12

arch/powerpc/platforms/8xx/Kconfig

··· 116 116 117 117 If in doubt, say Y here. 118 118 119 - config 8xx_CPU6 120 - bool "CPU6 Silicon Errata (860 Pre Rev. C)" 121 - help 122 - MPC860 CPUs, prior to Rev C have some bugs in the silicon, which 123 - require workarounds for Linux (and most other OSes to work). If you 124 - get a BUG() very early in boot, this might fix the problem. For 125 - more details read the document entitled "MPC860 Family Device Errata 126 - Reference" on Freescale's website. This option also incurs a 127 - performance hit. 128 - 129 - If in doubt, say N here. 130 - 131 119 config 8xx_CPU15 132 120 bool "CPU15 Silicon Errata" 133 121 depends on !HUGETLB_PAGE