Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'riscv-for-linus-6.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

- A fix for cacheinfo DT probing to avoid reading non-boolean
properties as booleans.

- A fix for cpufeature to use bitmap_equal() instead of memcmp(), so
unused bits are ignored.

- Fixes for cmpxchg and futex cmpxchg that properly encode the sign
extension requirements on inline asm, which results in spurious
successes. This manifests in at least inode_set_ctime_current, but is
likely just a disaster waiting to happen.

- A fix for the rseq selftests, which was using an invalid constraint.

- A pair of fixes for signal frame size handling:

- We were reserving space for an extra empty extension context
header on systems with extended signal context, thus resulting in
unnecessarily large allocations.

- We weren't properly checking for available extensions before
calculating the signal stack size, which resulted in undersized
stack allocations on some systems (at least those with T-Head
custom vectors).

Also, we've added Alex as a reviewer. He's been helping out a ton
lately, thanks!

* tag 'riscv-for-linus-6.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
MAINTAINERS: Add myself as a riscv reviewer
riscv: signal: fix signal_minsigstksz
riscv: signal: fix signal frame size
rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm
riscv/futex: sign extend compare value in atomic cmpxchg
riscv/atomic: Do proper sign extension also for unsigned in arch_cmpxchg
riscv: cpufeature: use bitmap_equal() instead of memcmp()
riscv: cacheinfo: Use of_property_present() for non-boolean properties

+15 -20
+1
MAINTAINERS
··· 20328 20328 M: Paul Walmsley <paul.walmsley@sifive.com> 20329 20329 M: Palmer Dabbelt <palmer@dabbelt.com> 20330 20330 M: Albert Ou <aou@eecs.berkeley.edu> 20331 + R: Alexandre Ghiti <alex@ghiti.fr> 20331 20332 L: linux-riscv@lists.infradead.org 20332 20333 S: Supported 20333 20334 Q: https://patchwork.kernel.org/project/linux-riscv/list/
+1 -1
arch/riscv/include/asm/cmpxchg.h
··· 231 231 __arch_cmpxchg(".w", ".w" sc_sfx, ".w" cas_sfx, \ 232 232 sc_prepend, sc_append, \ 233 233 cas_prepend, cas_append, \ 234 - __ret, __ptr, (long), __old, __new); \ 234 + __ret, __ptr, (long)(int)(long), __old, __new); \ 235 235 break; \ 236 236 case 8: \ 237 237 __arch_cmpxchg(".d", ".d" sc_sfx, ".d" cas_sfx, \
+1 -1
arch/riscv/include/asm/futex.h
··· 93 93 _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %[r]) \ 94 94 _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %[r]) \ 95 95 : [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp) 96 - : [ov] "Jr" (oldval), [nv] "Jr" (newval) 96 + : [ov] "Jr" ((long)(int)oldval), [nv] "Jr" (newval) 97 97 : "memory"); 98 98 __disable_user_access(); 99 99
+6 -6
arch/riscv/kernel/cacheinfo.c
··· 108 108 if (!np) 109 109 return -ENOENT; 110 110 111 - if (of_property_read_bool(np, "cache-size")) 111 + if (of_property_present(np, "cache-size")) 112 112 ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); 113 - if (of_property_read_bool(np, "i-cache-size")) 113 + if (of_property_present(np, "i-cache-size")) 114 114 ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); 115 - if (of_property_read_bool(np, "d-cache-size")) 115 + if (of_property_present(np, "d-cache-size")) 116 116 ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); 117 117 118 118 prev = np; ··· 125 125 break; 126 126 if (level <= levels) 127 127 break; 128 - if (of_property_read_bool(np, "cache-size")) 128 + if (of_property_present(np, "cache-size")) 129 129 ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); 130 - if (of_property_read_bool(np, "i-cache-size")) 130 + if (of_property_present(np, "i-cache-size")) 131 131 ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); 132 - if (of_property_read_bool(np, "d-cache-size")) 132 + if (of_property_present(np, "d-cache-size")) 133 133 ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); 134 134 levels = level; 135 135 }
+1 -1
arch/riscv/kernel/cpufeature.c
··· 479 479 if (bit < RISCV_ISA_EXT_BASE) 480 480 *this_hwcap |= isa2hwcap[bit]; 481 481 } 482 - } while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa))); 482 + } while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX)); 483 483 } 484 484 485 485 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
+1 -1
arch/riscv/kernel/setup.c
··· 322 322 323 323 riscv_init_cbo_blocksizes(); 324 324 riscv_fill_hwcap(); 325 - init_rt_signal_env(); 326 325 apply_boot_alternatives(); 326 + init_rt_signal_env(); 327 327 328 328 if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && 329 329 riscv_isa_extension_available(NULL, ZICBOM))
-6
arch/riscv/kernel/signal.c
··· 215 215 if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) 216 216 total_context_size += riscv_v_sc_size; 217 217 } 218 - /* 219 - * Preserved a __riscv_ctx_hdr for END signal context header if an 220 - * extension uses __riscv_extra_ext_header 221 - */ 222 - if (total_context_size) 223 - total_context_size += sizeof(struct __riscv_ctx_hdr); 224 218 225 219 frame_size += total_context_size; 226 220
+3 -3
tools/testing/selftests/rseq/rseq-riscv-bits.h
··· 243 243 #ifdef RSEQ_COMPARE_TWICE 244 244 RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]") 245 245 #endif 246 - RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3) 246 + RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3) 247 247 RSEQ_INJECT_ASM(4) 248 248 RSEQ_ASM_DEFINE_ABORT(4, abort) 249 249 : /* gcc asm goto does not allow outputs */ ··· 251 251 [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD), 252 252 [rseq_cs] "m" (rseq_get_abi()->rseq_cs.arch.ptr), 253 253 [ptr] "r" (ptr), 254 - [off] "er" (off), 255 - [inc] "er" (inc) 254 + [off] "r" (off), 255 + [inc] "r" (inc) 256 256 RSEQ_INJECT_INPUT 257 257 : "memory", RSEQ_ASM_TMP_REG_1 258 258 RSEQ_INJECT_CLOBBER
+1 -1
tools/testing/selftests/rseq/rseq-riscv.h
··· 158 158 "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \ 159 159 "333:\n" 160 160 161 - #define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label) \ 161 + #define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \ 162 162 "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \ 163 163 RSEQ_ASM_OP_R_ADD(off) \ 164 164 REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \