commit 29e92f483603d97dd1d2bafcb32101287dfac4ad · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] pxa: spitz wants PXA27x UDC definitions
[ARM] pxa: fix pxafb build when cpufreq is enabled
[ARM] fix parenthesis in include/asm-arm/arch-omap/control.h
[ARM] colibri: fix support for DM9000 ethernet device
[ARM] arm/kernel/arthur.c: add MODULE_LICENSE
[ARM] 5037/1: Orion: fix DNS323/Kurobox Pro PCI initialisation
[ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode
[ARM] export copy_page
[ARM] 5026/1: locomo: add .settype for gpio and several small fixes
ARM: OMAP: Fixed comments on global PRM register usage
ARM: OMAP: Add PARENT_CONTROLS_CLOCK flag to dpll5_m2_ck
ARM: OMAP: PRCM fixes to ssi clock handling
ARM: OMAP: Add fuctional clock enabler for iva2
ARM: OMAP: Fix 34xx to use correct shift values for gpio2-6 fclks
ARM: OMAP: Keymap fix for palmte and palmz71
ARM: OMAP: Fix Unbalanced enable for IRQ in omap mailbox
ARM: OMAP: DMA: Fix incorrect channel linking
ARM: OMAP: Warn on disabling clocks with no users
ARM: OMAP: Add calls to omap2_set_globals_*()
ARM: OMAP: Update MMC header to fix compile

Linus Torvalds 17 years ago 29e92f48 08c18964

+142 -74

31 changed files

expand all

unified split

arch

arm

common

locomo.c

kernel

armksyms.c

arthur.c

mach-omap1

board-palmte.c

board-palmz71.c

mach-omap2

board-2430sdp.c

board-apollon.c

board-generic.c

board-h4.c

clock.c

clock34xx.h

cm-regbits-34xx.h

mailbox.c

prm.h

mach-orion5x

dns323-setup.c

kurobox_pro-setup.c

mach-pxa

colibri.c

spitz.c

proc-arm925.S

proc-arm926.S

proc-arm940.S

proc-arm946.S

plat-omap

clock.c

dma.c

mailbox.c

drivers

video

pxafb.c

include

asm-arm

arch-omap

common.h

control.h

mmc.h

arch-sa1100

irqs.h

hardware

locomo.h

+48 -18

arch/arm/common/locomo.c

··· 321 321 locomo_writel(r, mapbase + LOCOMO_GIE); 322 322 } 323 323 324 + static int GPIO_IRQ_rising_edge; 325 + static int GPIO_IRQ_falling_edge; 326 + 327 + static int locomo_gpio_type(unsigned int irq, unsigned int type) 328 + { 329 + unsigned int mask; 330 + void __iomem *mapbase = get_irq_chip_data(irq); 331 + 332 + mask = 1 << (irq - LOCOMO_IRQ_GPIO_START); 333 + 334 + if (type == IRQT_PROBE) { 335 + if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) 336 + return 0; 337 + type = __IRQT_RISEDGE | __IRQT_FALEDGE; 338 + } 339 + 340 + if (type & __IRQT_RISEDGE) 341 + GPIO_IRQ_rising_edge |= mask; 342 + else 343 + GPIO_IRQ_rising_edge &= ~mask; 344 + if (type & __IRQT_FALEDGE) 345 + GPIO_IRQ_falling_edge |= mask; 346 + else 347 + GPIO_IRQ_falling_edge &= ~mask; 348 + locomo_writel(GPIO_IRQ_rising_edge, mapbase + LOCOMO_GRIE); 349 + locomo_writel(GPIO_IRQ_falling_edge, mapbase + LOCOMO_GFIE); 350 + 351 + return 0; 352 + } 353 + 324 354 static struct irq_chip locomo_gpio_chip = { 325 - .name = "LOCOMO-gpio", 326 - .ack = locomo_gpio_ack_irq, 327 - .mask = locomo_gpio_mask_irq, 328 - .unmask = locomo_gpio_unmask_irq, 355 + .name = "LOCOMO-gpio", 356 + .ack = locomo_gpio_ack_irq, 357 + .mask = locomo_gpio_mask_irq, 358 + .unmask = locomo_gpio_unmask_irq, 359 + .set_type = locomo_gpio_type, 329 360 }; 330 361 331 362 static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc) ··· 481 450 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); 482 451 set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase); 483 452 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); 484 - set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE); 485 453 486 454 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); 487 455 set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase); 488 456 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler); 489 - set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE); 490 457 491 458 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip); 492 459 set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase); 493 460 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler); 494 - set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE); 495 461 496 462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip); 497 463 set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase); 498 464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); 499 - set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE); 500 465 501 466 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ 502 467 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); ··· 515 488 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE); 516 489 517 490 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */ 518 - for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) { 491 + for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 4; irq++) { 519 492 set_irq_chip(irq, &locomo_spi_chip); 520 493 set_irq_chip_data(irq, irqbase); 521 494 set_irq_handler(irq, handle_edge_irq); ··· 601 574 602 575 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ 603 576 locomo_writel(0x00, lchip->base + LOCOMO_GPO); 604 - save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPICT); /* SPI */ 577 + save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */ 605 578 locomo_writel(0x40, lchip->base + LOCOMO_SPICT); 606 579 save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */ 607 580 locomo_writel(0x00, lchip->base + LOCOMO_GPE); 608 581 save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */ 609 582 locomo_writel(0x00, lchip->base + LOCOMO_ASD); 610 - save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPIMD); /* SPI */ 611 - locomo_writel(0x3C14, lchip->base + LOCOMO_SPIMD); 583 + save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */ 584 + locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); 612 585 613 586 locomo_writel(0x00, lchip->base + LOCOMO_PAIF); 614 587 locomo_writel(0x00, lchip->base + LOCOMO_DAC); 615 588 locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC); 616 589 617 - if ( (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88) ) 590 + if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88)) 618 591 locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */ 619 592 else 620 593 /* 18MHz already enabled, so no wait */ ··· 643 616 spin_lock_irqsave(&lchip->lock, flags); 644 617 645 618 locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO); 646 - locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPICT); 619 + locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT); 647 620 locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE); 648 621 locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD); 649 - locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPIMD); 622 + locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); 650 623 651 624 locomo_writel(0x00, lchip->base + LOCOMO_C32K); 652 625 locomo_writel(0x90, lchip->base + LOCOMO_TADC); ··· 715 688 716 689 /* GPIO */ 717 690 locomo_writel(0, lchip->base + LOCOMO_GPO); 718 - locomo_writel( (LOCOMO_GPIO(2) | LOCOMO_GPIO(3) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14)) 691 + locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14)) 719 692 , lchip->base + LOCOMO_GPE); 720 - locomo_writel( (LOCOMO_GPIO(2) | LOCOMO_GPIO(3) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14)) 693 + locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14)) 721 694 , lchip->base + LOCOMO_GPD); 722 695 locomo_writel(0, lchip->base + LOCOMO_GIE); 723 696 ··· 860 833 spin_lock_irqsave(&lchip->lock, flags); 861 834 862 835 r = locomo_readl(lchip->base + LOCOMO_GPD); 863 - r &= ~bits; 836 + if (dir) 837 + r |= bits; 838 + else 839 + r &= ~bits; 864 840 locomo_writel(r, lchip->base + LOCOMO_GPD); 865 841 866 842 r = locomo_readl(lchip->base + LOCOMO_GPE);

arch/arm/kernel/armksyms.c

··· 179 179 EXPORT_SYMBOL(_find_first_bit_be); 180 180 EXPORT_SYMBOL(_find_next_bit_be); 181 181 #endif 182 + 183 + EXPORT_SYMBOL(copy_page);

arch/arm/kernel/arthur.c

··· 90 90 91 91 module_init(arthur_init); 92 92 module_exit(arthur_exit); 93 + 94 + MODULE_LICENSE("GPL");

+1 -1

arch/arm/mach-omap1/board-palmte.c

··· 63 63 KEY(1, 1, KEY_DOWN), 64 64 KEY(1, 2, KEY_UP), 65 65 KEY(1, 3, KEY_RIGHT), 66 - KEY(1, 4, KEY_CENTER), 66 + KEY(1, 4, KEY_ENTER), 67 67 0, 68 68 }; 69 69

+1 -1

arch/arm/mach-omap1/board-palmz71.c

··· 65 65 KEY(1, 1, KEY_DOWN), 66 66 KEY(1, 2, KEY_UP), 67 67 KEY(1, 3, KEY_RIGHT), 68 - KEY(1, 4, KEY_CENTER), 68 + KEY(1, 4, KEY_ENTER), 69 69 KEY(2, 0, KEY_CAMERA), 70 70 0, 71 71 };

arch/arm/mach-omap2/board-2430sdp.c

··· 208 208 209 209 static void __init omap_2430sdp_map_io(void) 210 210 { 211 + omap2_set_globals_243x(); 211 212 omap2_map_common_io(); 212 213 } 213 214

arch/arm/mach-omap2/board-apollon.c

··· 394 394 395 395 static void __init omap_apollon_map_io(void) 396 396 { 397 + omap2_set_globals_242x(); 397 398 omap2_map_common_io(); 398 399 } 399 400

arch/arm/mach-omap2/board-generic.c

··· 65 65 66 66 static void __init omap_generic_map_io(void) 67 67 { 68 + omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ 68 69 omap2_map_common_io(); 69 70 } 70 71

arch/arm/mach-omap2/board-h4.c

··· 420 420 421 421 static void __init omap_h4_map_io(void) 422 422 { 423 + omap2_set_globals_242x(); 423 424 omap2_map_common_io(); 424 425 } 425 426

+3 -1

arch/arm/mach-omap2/clock.c

··· 205 205 /* REVISIT: What are the appropriate exclusions for 34XX? */ 206 206 /* OMAP3: ignore DSS-mod clocks */ 207 207 if (cpu_is_omap34xx() && 208 - (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0))) 208 + (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || 209 + ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && 210 + clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) 209 211 return; 210 212 211 213 /* Check if both functional and interface clocks

+12 -9

arch/arm/mach-omap2/clock34xx.h

··· 836 836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 837 837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 838 838 .clksel = div16_dpll5_clksel, 839 - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 839 + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 840 + PARENT_CONTROLS_CLOCK, 840 841 .recalc = &omap2_clksel_recalc, 841 842 }; 842 843 ··· 1047 1046 .name = "iva2_ck", 1048 1047 .parent = &dpll2_m2_ck, 1049 1048 .init = &omap2_init_clksel_parent, 1049 + .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1050 + .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1050 1051 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 1051 1052 OMAP3430_CM_IDLEST_PLL), 1052 1053 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, 1053 1054 .clksel = iva2_clksel, 1054 - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1055 - PARENT_CONTROLS_CLOCK, 1055 + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1056 1056 .recalc = &omap2_clksel_recalc, 1057 1057 }; 1058 1058 ··· 1838 1836 static struct clk ssi_l4_ick = { 1839 1837 .name = "ssi_l4_ick", 1840 1838 .parent = &l4_ick, 1841 - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1839 + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1840 + PARENT_CONTROLS_CLOCK, 1842 1841 .recalc = &followparent_recalc, 1843 1842 }; 1844 1843 ··· 2347 2344 .name = "gpio6_fck", 2348 2345 .parent = &per_32k_alwon_fck, 2349 2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2350 - .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2347 + .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2351 2348 .flags = CLOCK_IN_OMAP343X, 2352 2349 .recalc = &followparent_recalc, 2353 2350 }; ··· 2356 2353 .name = "gpio5_fck", 2357 2354 .parent = &per_32k_alwon_fck, 2358 2355 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2359 - .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2356 + .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2360 2357 .flags = CLOCK_IN_OMAP343X, 2361 2358 .recalc = &followparent_recalc, 2362 2359 }; ··· 2365 2362 .name = "gpio4_fck", 2366 2363 .parent = &per_32k_alwon_fck, 2367 2364 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2368 - .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2365 + .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2369 2366 .flags = CLOCK_IN_OMAP343X, 2370 2367 .recalc = &followparent_recalc, 2371 2368 }; ··· 2374 2371 .name = "gpio3_fck", 2375 2372 .parent = &per_32k_alwon_fck, 2376 2373 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2377 - .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2374 + .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2378 2375 .flags = CLOCK_IN_OMAP343X, 2379 2376 .recalc = &followparent_recalc, 2380 2377 }; ··· 2383 2380 .name = "gpio2_fck", 2384 2381 .parent = &per_32k_alwon_fck, 2385 2382 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2386 - .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2383 + .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2387 2384 .flags = CLOCK_IN_OMAP343X, 2388 2385 .recalc = &followparent_recalc, 2389 2386 };

arch/arm/mach-omap2/cm-regbits-34xx.h

··· 56 56 57 57 /* CM_FCLKEN_IVA2 */ 58 58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 59 + #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 59 60 60 61 /* CM_CLKEN_PLL_IVA2 */ 61 62 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8

+15 -10

arch/arm/mach-omap2/mailbox.c

··· 70 70 71 71 static struct clk *mbox_ick_handle; 72 72 73 + static void omap2_mbox_enable_irq(struct omap_mbox *mbox, 74 + omap_mbox_type_t irq); 75 + 73 76 static inline unsigned int mbox_read_reg(unsigned int reg) 74 77 { 75 78 return __raw_readl(mbox_base + reg); ··· 84 81 } 85 82 86 83 /* Mailbox H/W preparations */ 87 - static inline int omap2_mbox_startup(struct omap_mbox *mbox) 84 + static int omap2_mbox_startup(struct omap_mbox *mbox) 88 85 { 89 86 unsigned int l; 90 87 ··· 100 97 l |= 0x00000011; 101 98 mbox_write_reg(l, MAILBOX_SYSCONFIG); 102 99 100 + omap2_mbox_enable_irq(mbox, IRQ_RX); 101 + 103 102 return 0; 104 103 } 105 104 106 - static inline void omap2_mbox_shutdown(struct omap_mbox *mbox) 105 + static void omap2_mbox_shutdown(struct omap_mbox *mbox) 107 106 { 108 107 clk_disable(mbox_ick_handle); 109 108 clk_put(mbox_ick_handle); 110 109 } 111 110 112 111 /* Mailbox FIFO handle functions */ 113 - static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox) 112 + static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox) 114 113 { 115 114 struct omap_mbox2_fifo *fifo = 116 115 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; 117 116 return (mbox_msg_t) mbox_read_reg(fifo->msg); 118 117 } 119 118 120 - static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 119 + static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 121 120 { 122 121 struct omap_mbox2_fifo *fifo = 123 122 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; 124 123 mbox_write_reg(msg, fifo->msg); 125 124 } 126 125 127 - static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox) 126 + static int omap2_mbox_fifo_empty(struct omap_mbox *mbox) 128 127 { 129 128 struct omap_mbox2_fifo *fifo = 130 129 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; 131 130 return (mbox_read_reg(fifo->msg_stat) == 0); 132 131 } 133 132 134 - static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox) 133 + static int omap2_mbox_fifo_full(struct omap_mbox *mbox) 135 134 { 136 135 struct omap_mbox2_fifo *fifo = 137 136 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; ··· 141 136 } 142 137 143 138 /* Mailbox IRQ handle functions */ 144 - static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox, 139 + static void omap2_mbox_enable_irq(struct omap_mbox *mbox, 145 140 omap_mbox_type_t irq) 146 141 { 147 142 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; ··· 152 147 mbox_write_reg(l, p->irqenable); 153 148 } 154 149 155 - static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox, 150 + static void omap2_mbox_disable_irq(struct omap_mbox *mbox, 156 151 omap_mbox_type_t irq) 157 152 { 158 153 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; ··· 163 158 mbox_write_reg(l, p->irqenable); 164 159 } 165 160 166 - static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox, 161 + static void omap2_mbox_ack_irq(struct omap_mbox *mbox, 167 162 omap_mbox_type_t irq) 168 163 { 169 164 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; ··· 172 167 mbox_write_reg(bit, p->irqstatus); 173 168 } 174 169 175 - static inline int omap2_mbox_is_irq(struct omap_mbox *mbox, 170 + static int omap2_mbox_is_irq(struct omap_mbox *mbox, 176 171 omap_mbox_type_t irq) 177 172 { 178 173 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;

+1 -1

arch/arm/mach-omap2/prm.h

··· 30 30 31 31 /* 32 32 * Architecture-specific global PRM registers 33 - * Use prm_{read,write}_reg() with these registers. 33 + * Use __raw_{read,write}l() with these registers. 34 34 * 35 35 * With a few exceptions, these are the register names beginning with 36 36 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the

+1 -1

arch/arm/mach-orion5x/dns323-setup.c

··· 58 58 } 59 59 60 60 static struct hw_pci dns323_pci __initdata = { 61 - .nr_controllers = 1, 61 + .nr_controllers = 2, 62 62 .swizzle = pci_std_swizzle, 63 63 .setup = orion5x_pci_sys_setup, 64 64 .scan = orion5x_pci_sys_scan_bus,

+1 -1

arch/arm/mach-orion5x/kurobox_pro-setup.c

··· 138 138 } 139 139 140 140 static struct hw_pci kurobox_pro_pci __initdata = { 141 - .nr_controllers = 1, 141 + .nr_controllers = 2, 142 142 .swizzle = pci_std_swizzle, 143 143 .setup = orion5x_pci_sys_setup, 144 144 .scan = orion5x_pci_sys_scan_bus,

+1 -2

arch/arm/mach-pxa/colibri.c

··· 98 98 [2] = { 99 99 .start = COLIBRI_ETH_IRQ, 100 100 .end = COLIBRI_ETH_IRQ, 101 - .flags = IORESOURCE_IRQ, 101 + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, 102 102 }, 103 103 }; 104 104 ··· 119 119 /* DM9000 LAN */ 120 120 pxa_gpio_mode(GPIO78_nCS_2_MD); 121 121 pxa_gpio_mode(GPIO_DM9000 | GPIO_IN); 122 - set_irq_type(COLIBRI_ETH_IRQ, IRQT_FALLING); 123 122 124 123 platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices)); 125 124 }

arch/arm/mach-pxa/spitz.c

··· 38 38 #include <asm/arch/pxa-regs.h> 39 39 #include <asm/arch/pxa2xx-regs.h> 40 40 #include <asm/arch/pxa2xx-gpio.h> 41 + #include <asm/arch/pxa27x-udc.h> 41 42 #include <asm/arch/irda.h> 42 43 #include <asm/arch/mmc.h> 43 44 #include <asm/arch/ohci.h>

+1 -1

arch/arm/mm/proc-arm925.S

··· 332 332 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 333 333 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 334 334 #else 335 - mcr p15, 0, r0, c7, c10, 1 @ clean D entry 335 + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 336 336 #endif 337 337 add r0, r0, #CACHE_DLINESIZE 338 338 cmp r0, r1

+1 -1

arch/arm/mm/proc-arm926.S

··· 295 295 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 296 296 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 297 297 #else 298 - mcr p15, 0, r0, c7, c10, 1 @ clean D entry 298 + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 299 299 #endif 300 300 add r0, r0, #CACHE_DLINESIZE 301 301 cmp r0, r1

+1 -1

arch/arm/mm/proc-arm940.S

··· 222 222 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 223 223 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry 224 224 #else 225 - mcr p15, 0, r3, c7, c10, 2 @ clean D entry 225 + mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry 226 226 #endif 227 227 subs r3, r3, #1 << 26 228 228 bcs 2b @ entries 63 to 0

+1 -1

arch/arm/mm/proc-arm946.S

··· 265 265 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 266 266 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 267 267 #else 268 - mcr p15, 0, r0, c7, c10, 1 @ clean D entry 268 + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 269 269 #endif 270 270 add r0, r0, #CACHE_DLINESIZE 271 271 cmp r0, r1

+9 -1

arch/arm/plat-omap/clock.c

··· 134 134 return; 135 135 136 136 spin_lock_irqsave(&clockfw_lock, flags); 137 - BUG_ON(clk->usecount == 0); 137 + if (clk->usecount == 0) { 138 + printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", 139 + clk->name); 140 + WARN_ON(1); 141 + goto out; 142 + } 143 + 138 144 if (arch_clock->clk_disable) 139 145 arch_clock->clk_disable(clk); 146 + 147 + out: 140 148 spin_unlock_irqrestore(&clockfw_lock, flags); 141 149 } 142 150 EXPORT_SYMBOL(clk_disable);

+1 -1

arch/arm/plat-omap/dma.c

··· 604 604 chan->data = data; 605 605 #ifndef CONFIG_ARCH_OMAP1 606 606 chan->chain_id = -1; 607 + chan->next_linked_ch = -1; 607 608 #endif 608 609 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 609 610 ··· 1088 1087 printk(KERN_ERR "omap_dma: Request failed %d\n", err); 1089 1088 return err; 1090 1089 } 1091 - dma_chan[channels[i]].next_linked_ch = -1; 1092 1090 dma_chan[channels[i]].prev_linked_ch = -1; 1093 1091 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; 1094 1092

-1

arch/arm/plat-omap/mailbox.c

··· 355 355 "failed to register mailbox interrupt:%d\n", ret); 356 356 goto fail_request_irq; 357 357 } 358 - enable_mbox_irq(mbox, IRQ_RX); 359 358 360 359 mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work); 361 360 if (!mq) {

+2 -3

drivers/video/pxafb.c

··· 355 355 } 356 356 357 357 #ifdef CONFIG_CPU_FREQ 358 - pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n", 359 - pxafb_display_dma_period(var), 360 - get_clk_frequency_khz(0)); 358 + pr_debug("pxafb: dma period = %d ps\n", 359 + pxafb_display_dma_period(var)); 361 360 #endif 362 361 363 362 return 0;

include/asm-arm/arch-omap/common.h

··· 47 47 } 48 48 #endif 49 49 50 + void omap2_set_globals_242x(void); 51 + void omap2_set_globals_243x(void); 52 + void omap2_set_globals_343x(void); 53 + 50 54 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

+1 -1

include/asm-arm/arch-omap/control.h

··· 80 80 #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 81 81 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 82 82 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 83 - #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074 83 + #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 84 84 #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 85 85 #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 86 86 #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)

+15 -9

include/asm-arm/arch-omap/mmc.h

··· 15 15 #include <linux/device.h> 16 16 #include <linux/mmc/host.h> 17 17 18 + #include <asm/arch/board.h> 19 + 18 20 #define OMAP_MMC_MAX_SLOTS 2 19 21 20 22 struct omap_mmc_platform_data { 21 23 struct omap_mmc_conf conf; 22 24 23 - unsigned enabled:1; 24 25 /* number of slots on board */ 25 26 unsigned nr_slots:2; 26 - /* nomux means "standard" muxing is wrong on this board, and that 27 - * board-specific code handled it before common init logic. 28 - */ 29 - unsigned nomux:1; 30 - /* 4 wire signaling is optional, and is only used for SD/SDIO and 31 - * MMCv4 */ 32 - unsigned wire4:1; 27 + 33 28 /* set if your board has components or wiring that limits the 34 29 * maximum frequency on the MMC bus */ 35 30 unsigned int max_freq; ··· 35 40 * not supported */ 36 41 int (* init)(struct device *dev); 37 42 void (* cleanup)(struct device *dev); 43 + void (* shutdown)(struct device *dev); 44 + 45 + /* To handle board related suspend/resume functionality for MMC */ 46 + int (*suspend)(struct device *dev, int slot); 47 + int (*resume)(struct device *dev, int slot); 38 48 39 49 struct omap_mmc_slot_data { 40 50 int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); ··· 56 56 57 57 const char *name; 58 58 u32 ocr_mask; 59 + 60 + /* Card detection IRQs */ 61 + int card_detect_irq; 62 + int (* card_detect)(int irq); 63 + 64 + unsigned int ban_openended:1; 65 + 59 66 } slots[OMAP_MMC_MAX_SLOTS]; 60 67 }; 61 68 62 69 extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info); 63 70 64 71 /* called from board-specific card detection service routine */ 65 - extern void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected); 66 72 extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); 67 73 68 74 #endif

+1 -1

include/asm-arm/arch-sa1100/irqs.h

··· 141 141 #define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) 142 142 #define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) 143 143 #define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) 144 - #define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20) 144 + #define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20) 145 145 #define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) 146 146 147 147 /*

+11 -8

include/asm-arm/hardware/locomo.h

··· 58 58 #define LOCOMO_SPIMD 0x00 /* SPI mode setting */ 59 59 #define LOCOMO_SPICT 0x04 /* SPI mode control */ 60 60 #define LOCOMO_SPIST 0x08 /* SPI status */ 61 + #define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */ 62 + #define LOCOMO_SPI_REND (1 << 2) /* Receive end bit */ 63 + #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */ 64 + #define LOCOMO_SPI_RFR (1) /* read buffer bit */ 65 + 61 66 #define LOCOMO_SPIIS 0x10 /* SPI interrupt status */ 62 67 #define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */ 63 68 #define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */ ··· 71 66 #define LOCOMO_SPIRD 0x24 /* SPI receive data read */ 72 67 #define LOCOMO_SPITS 0x28 /* SPI transfer data shift */ 73 68 #define LOCOMO_SPIRS 0x2C /* SPI receive data shift */ 74 - #define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */ 75 - #define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */ 76 - #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */ 77 - #define LOCOMO_SPI_RFR (1) /* read buffer bit */ 78 69 79 70 /* GPIO */ 80 71 #define LOCOMO_GPD 0x90 /* GPIO direction */ 81 72 #define LOCOMO_GPE 0x94 /* GPIO input enable */ 82 73 #define LOCOMO_GPL 0x98 /* GPIO level */ 83 - #define LOCOMO_GPO 0x9c /* GPIO out data setteing */ 74 + #define LOCOMO_GPO 0x9c /* GPIO out data setting */ 84 75 #define LOCOMO_GRIE 0xa0 /* GPIO rise detection */ 85 76 #define LOCOMO_GFIE 0xa4 /* GPIO fall detection */ 86 77 #define LOCOMO_GIS 0xa8 /* GPIO edge detection status */ ··· 97 96 #define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10) 98 97 #define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11) 99 98 #define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12) 99 + #define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13) 100 + #define LOCOMO_GPIO_WRITE_PROT LOCOMO_GPIO(14) 101 + #define LOCOMO_GPIO_CARD_POWER LOCOMO_GPIO(15) 100 102 101 103 /* Start the definitions of the devices. Each device has an initial 102 104 * base address and a series of offsets from that base address. */ ··· 126 122 /* Audio controller */ 127 123 #define LOCOMO_AUDIO 0x54 128 124 #define LOCOMO_ACC 0x00 /* Audio clock */ 129 - #define LOCOMO_PAIF 0x7C /* PCM audio interface */ 125 + #define LOCOMO_PAIF 0xD0 /* PCM audio interface */ 130 126 /* Audio clock */ 131 127 #define LOCOMO_ACC_XON 0x80 132 128 #define LOCOMO_ACC_XEN 0x40 ··· 166 162 #define LOCOMO_DEVID_AUDIO 3 167 163 #define LOCOMO_DEVID_LED 4 168 164 #define LOCOMO_DEVID_UART 5 169 - #define LOCOMO_DEVID_SPI 6 165 + #define LOCOMO_DEVID_SPI 6 170 166 171 167 struct locomo_dev { 172 168 struct device dev; ··· 207 203 int locomo_gpio_read_level(struct device *dev, unsigned int bits); 208 204 int locomo_gpio_read_output(struct device *dev, unsigned int bits); 209 205 void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set); 210 - 211 206 212 207 /* M62332 control function */ 213 208 void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);