tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'zynqmp-dt-for-4.14' of https://github.com/Xilinx/linux-xlnx into next/dt64
Pull "arm64: Xilinx ZynqMP DT fixes for v4.14" from Michal Simek:
- Fix DTC warnings
- Add idle states, OP, cci-400, RTC, pcie prefetchable memory
fpd/lpd dmas, clocks for ep108
- Enable can1
- Fix smmu IRQ, aliases, uart compatible string
- Use generic compatible string for i2c eeprom
* tag 'zynqmp-dt-for-4.14' of https://github.com/Xilinx/linux-xlnx:
arm64: zynqmp: Add generic compatible string for I2C EEPROM
arm64: zynqmp: Add missing mmc aliases in ep108
arm64: zynqmp: Enable can1 for ep108
arm64: zynqmp: Added clocks to DT for ep108
arm64: zynqmp: Use C pre-processor for includes
arm64: zynqmp: Add fpd/lpd dmas
arm64: zynqmp: Set status disabled in dtsi
arm64: zynqmp: Add new uartps compatible string
arm64: zynqmp: Correct IRQ nr for the SMMU
arm64: zynqmp: Add support for RTC
arm64: zynqmp: Adding prefetchable memory space to pcie node
arm64: zynqmp: Add CCI-400 node
arm64: zynqmp: Add dcc console for zynqmp
arm64: zynqmp: Add operating points
arm64: zynqmp: Add idle state for ZynqMP
arm64: zynqmp: Add references to cpu nodes
arm64: zynqmp: Move nodes which have no reg property out of bus
arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
arm64: dts: xilinx: fix PCI bus dtc warnings
+321
-24
+49
-1
arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
+49
-1
arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
···
11
11
* the License, or (at your option) any later version.
12
12
*/
13
13
14
-
&amba {
14
+
/ {
15
15
misc_clk: misc_clk {
16
16
compatible = "fixed-clock";
17
17
#clock-cells = <0>;
···
29
29
#clock-cells = <0>;
30
30
clock-frequency = <75000000>;
31
31
};
32
+
33
+
clk100: clk100 {
34
+
compatible = "fixed-clock";
35
+
#clock-cells = <0>;
36
+
clock-frequency = <100000000>;
37
+
};
38
+
39
+
clk600: clk600 {
40
+
compatible = "fixed-clock";
41
+
#clock-cells = <0>;
42
+
clock-frequency = <600000000>;
43
+
};
32
44
};
33
45
34
46
&can0 {
35
47
clocks = <&misc_clk &misc_clk>;
48
+
};
49
+
50
+
&can1 {
51
+
clocks = <&misc_clk &misc_clk>;
52
+
};
53
+
54
+
&fpd_dma_chan1 {
55
+
clocks = <&clk600>, <&clk100>;
56
+
};
57
+
58
+
&fpd_dma_chan2 {
59
+
clocks = <&clk600>, <&clk100>;
60
+
};
61
+
62
+
&fpd_dma_chan3 {
63
+
clocks = <&clk600>, <&clk100>;
64
+
};
65
+
66
+
&fpd_dma_chan4 {
67
+
clocks = <&clk600>, <&clk100>;
68
+
};
69
+
70
+
&fpd_dma_chan5 {
71
+
clocks = <&clk600>, <&clk100>;
72
+
};
73
+
74
+
&fpd_dma_chan6 {
75
+
clocks = <&clk600>, <&clk100>;
76
+
};
77
+
78
+
&fpd_dma_chan7 {
79
+
clocks = <&clk600>, <&clk100>;
80
+
};
81
+
82
+
&fpd_dma_chan8 {
83
+
clocks = <&clk600>, <&clk100>;
36
84
};
37
85
38
86
&gem0 {
+12
-6
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+12
-6
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
···
13
13
14
14
/dts-v1/;
15
15
16
-
/include/ "zynqmp.dtsi"
17
-
/include/ "zynqmp-ep108-clk.dtsi"
16
+
#include "zynqmp.dtsi"
17
+
#include "zynqmp-ep108-clk.dtsi"
18
18
19
19
/ {
20
20
model = "ZynqMP EP108";
21
21
22
22
aliases {
23
+
mmc0 = &sdhci0;
24
+
mmc1 = &sdhci1;
23
25
serial0 = &uart0;
24
26
};
25
27
···
36
34
};
37
35
38
36
&can0 {
37
+
status = "okay";
38
+
};
39
+
40
+
&can1 {
39
41
status = "okay";
40
42
};
41
43
···
61
55
status = "okay";
62
56
clock-frequency = <400000>;
63
57
eeprom@54 {
64
-
compatible = "at,24c64";
58
+
compatible = "atmel,24c64";
65
59
reg = <0x54>;
66
60
};
67
61
};
···
70
64
status = "okay";
71
65
clock-frequency = <400000>;
72
66
eeprom@55 {
73
-
compatible = "at,24c64";
67
+
compatible = "atmel,24c64";
74
68
reg = <0x55>;
75
69
};
76
70
};
···
98
92
spi-max-frequency = <50000000>;
99
93
reg = <0>;
100
94
101
-
spi0_flash0@00000000 {
95
+
spi0_flash0@0 {
102
96
label = "spi0_flash0";
103
97
reg = <0x0 0x100000>;
104
98
};
···
115
109
spi-max-frequency = <50000000>;
116
110
reg = <0>;
117
111
118
-
spi1_flash0@00000000 {
112
+
spi1_flash0@0 {
119
113
label = "spi1_flash0";
120
114
reg = <0x0 0x100000>;
121
115
};
+260
-17
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+260
-17
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
···
20
20
#address-cells = <1>;
21
21
#size-cells = <0>;
22
22
23
-
cpu@0 {
23
+
cpu0: cpu@0 {
24
24
compatible = "arm,cortex-a53", "arm,armv8";
25
25
device_type = "cpu";
26
26
enable-method = "psci";
27
+
operating-points-v2 = <&cpu_opp_table>;
27
28
reg = <0x0>;
29
+
cpu-idle-states = <&CPU_SLEEP_0>;
28
30
};
29
31
30
-
cpu@1 {
32
+
cpu1: cpu@1 {
31
33
compatible = "arm,cortex-a53", "arm,armv8";
32
34
device_type = "cpu";
33
35
enable-method = "psci";
34
36
reg = <0x1>;
37
+
operating-points-v2 = <&cpu_opp_table>;
38
+
cpu-idle-states = <&CPU_SLEEP_0>;
35
39
};
36
40
37
-
cpu@2 {
41
+
cpu2: cpu@2 {
38
42
compatible = "arm,cortex-a53", "arm,armv8";
39
43
device_type = "cpu";
40
44
enable-method = "psci";
41
45
reg = <0x2>;
46
+
operating-points-v2 = <&cpu_opp_table>;
47
+
cpu-idle-states = <&CPU_SLEEP_0>;
42
48
};
43
49
44
-
cpu@3 {
50
+
cpu3: cpu@3 {
45
51
compatible = "arm,cortex-a53", "arm,armv8";
46
52
device_type = "cpu";
47
53
enable-method = "psci";
48
54
reg = <0x3>;
55
+
operating-points-v2 = <&cpu_opp_table>;
56
+
cpu-idle-states = <&CPU_SLEEP_0>;
49
57
};
58
+
59
+
idle-states {
60
+
entry-method = "arm,psci";
61
+
62
+
CPU_SLEEP_0: cpu-sleep-0 {
63
+
compatible = "arm,idle-state";
64
+
arm,psci-suspend-param = <0x40000000>;
65
+
local-timer-stop;
66
+
entry-latency-us = <300>;
67
+
exit-latency-us = <600>;
68
+
min-residency-us = <10000>;
69
+
};
70
+
};
71
+
};
72
+
73
+
cpu_opp_table: cpu_opp_table {
74
+
compatible = "operating-points-v2";
75
+
opp-shared;
76
+
opp00 {
77
+
opp-hz = /bits/ 64 <1199999988>;
78
+
opp-microvolt = <1000000>;
79
+
clock-latency-ns = <500000>;
80
+
};
81
+
opp01 {
82
+
opp-hz = /bits/ 64 <599999994>;
83
+
opp-microvolt = <1000000>;
84
+
clock-latency-ns = <500000>;
85
+
};
86
+
opp02 {
87
+
opp-hz = /bits/ 64 <399999996>;
88
+
opp-microvolt = <1000000>;
89
+
clock-latency-ns = <500000>;
90
+
};
91
+
opp03 {
92
+
opp-hz = /bits/ 64 <299999997>;
93
+
opp-microvolt = <1000000>;
94
+
clock-latency-ns = <500000>;
95
+
};
96
+
};
97
+
98
+
dcc: dcc {
99
+
compatible = "arm,dcc";
100
+
status = "disabled";
50
101
};
51
102
52
103
pmu {
···
168
117
interrupt-parent = <&gic>;
169
118
tx-fifo-depth = <0x40>;
170
119
rx-fifo-depth = <0x40>;
120
+
};
121
+
122
+
cci: cci@fd6e0000 {
123
+
compatible = "arm,cci-400";
124
+
reg = <0x0 0xfd6e0000 0x0 0x9000>;
125
+
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
126
+
#address-cells = <1>;
127
+
#size-cells = <1>;
128
+
129
+
pmu@9000 {
130
+
compatible = "arm,cci-400-pmu,r1";
131
+
reg = <0x9000 0x5000>;
132
+
interrupt-parent = <&gic>;
133
+
interrupts = <0 123 4>,
134
+
<0 123 4>,
135
+
<0 123 4>,
136
+
<0 123 4>,
137
+
<0 123 4>;
138
+
};
139
+
};
140
+
141
+
/* GDMA */
142
+
fpd_dma_chan1: dma@fd500000 {
143
+
status = "disabled";
144
+
compatible = "xlnx,zynqmp-dma-1.0";
145
+
reg = <0x0 0xfd500000 0x0 0x1000>;
146
+
interrupt-parent = <&gic>;
147
+
interrupts = <0 124 4>;
148
+
clock-names = "clk_main", "clk_apb";
149
+
xlnx,bus-width = <128>;
150
+
};
151
+
152
+
fpd_dma_chan2: dma@fd510000 {
153
+
status = "disabled";
154
+
compatible = "xlnx,zynqmp-dma-1.0";
155
+
reg = <0x0 0xfd510000 0x0 0x1000>;
156
+
interrupt-parent = <&gic>;
157
+
interrupts = <0 125 4>;
158
+
clock-names = "clk_main", "clk_apb";
159
+
xlnx,bus-width = <128>;
160
+
};
161
+
162
+
fpd_dma_chan3: dma@fd520000 {
163
+
status = "disabled";
164
+
compatible = "xlnx,zynqmp-dma-1.0";
165
+
reg = <0x0 0xfd520000 0x0 0x1000>;
166
+
interrupt-parent = <&gic>;
167
+
interrupts = <0 126 4>;
168
+
clock-names = "clk_main", "clk_apb";
169
+
xlnx,bus-width = <128>;
170
+
};
171
+
172
+
fpd_dma_chan4: dma@fd530000 {
173
+
status = "disabled";
174
+
compatible = "xlnx,zynqmp-dma-1.0";
175
+
reg = <0x0 0xfd530000 0x0 0x1000>;
176
+
interrupt-parent = <&gic>;
177
+
interrupts = <0 127 4>;
178
+
clock-names = "clk_main", "clk_apb";
179
+
xlnx,bus-width = <128>;
180
+
};
181
+
182
+
fpd_dma_chan5: dma@fd540000 {
183
+
status = "disabled";
184
+
compatible = "xlnx,zynqmp-dma-1.0";
185
+
reg = <0x0 0xfd540000 0x0 0x1000>;
186
+
interrupt-parent = <&gic>;
187
+
interrupts = <0 128 4>;
188
+
clock-names = "clk_main", "clk_apb";
189
+
xlnx,bus-width = <128>;
190
+
};
191
+
192
+
fpd_dma_chan6: dma@fd550000 {
193
+
status = "disabled";
194
+
compatible = "xlnx,zynqmp-dma-1.0";
195
+
reg = <0x0 0xfd550000 0x0 0x1000>;
196
+
interrupt-parent = <&gic>;
197
+
interrupts = <0 129 4>;
198
+
clock-names = "clk_main", "clk_apb";
199
+
xlnx,bus-width = <128>;
200
+
};
201
+
202
+
fpd_dma_chan7: dma@fd560000 {
203
+
status = "disabled";
204
+
compatible = "xlnx,zynqmp-dma-1.0";
205
+
reg = <0x0 0xfd560000 0x0 0x1000>;
206
+
interrupt-parent = <&gic>;
207
+
interrupts = <0 130 4>;
208
+
clock-names = "clk_main", "clk_apb";
209
+
xlnx,bus-width = <128>;
210
+
};
211
+
212
+
fpd_dma_chan8: dma@fd570000 {
213
+
status = "disabled";
214
+
compatible = "xlnx,zynqmp-dma-1.0";
215
+
reg = <0x0 0xfd570000 0x0 0x1000>;
216
+
interrupt-parent = <&gic>;
217
+
interrupts = <0 131 4>;
218
+
clock-names = "clk_main", "clk_apb";
219
+
xlnx,bus-width = <128>;
220
+
};
221
+
222
+
/* LPDDMA default allows only secured access. inorder to enable
223
+
* These dma channels, Users should ensure that these dma
224
+
* Channels are allowed for non secure access.
225
+
*/
226
+
lpd_dma_chan1: dma@ffa80000 {
227
+
status = "disabled";
228
+
compatible = "xlnx,zynqmp-dma-1.0";
229
+
reg = <0x0 0xffa80000 0x0 0x1000>;
230
+
interrupt-parent = <&gic>;
231
+
interrupts = <0 77 4>;
232
+
clock-names = "clk_main", "clk_apb";
233
+
xlnx,bus-width = <64>;
234
+
};
235
+
236
+
lpd_dma_chan2: dma@ffa90000 {
237
+
status = "disabled";
238
+
compatible = "xlnx,zynqmp-dma-1.0";
239
+
reg = <0x0 0xffa90000 0x0 0x1000>;
240
+
interrupt-parent = <&gic>;
241
+
interrupts = <0 78 4>;
242
+
clock-names = "clk_main", "clk_apb";
243
+
xlnx,bus-width = <64>;
244
+
};
245
+
246
+
lpd_dma_chan3: dma@ffaa0000 {
247
+
status = "disabled";
248
+
compatible = "xlnx,zynqmp-dma-1.0";
249
+
reg = <0x0 0xffaa0000 0x0 0x1000>;
250
+
interrupt-parent = <&gic>;
251
+
interrupts = <0 79 4>;
252
+
clock-names = "clk_main", "clk_apb";
253
+
xlnx,bus-width = <64>;
254
+
};
255
+
256
+
lpd_dma_chan4: dma@ffab0000 {
257
+
status = "disabled";
258
+
compatible = "xlnx,zynqmp-dma-1.0";
259
+
reg = <0x0 0xffab0000 0x0 0x1000>;
260
+
interrupt-parent = <&gic>;
261
+
interrupts = <0 80 4>;
262
+
clock-names = "clk_main", "clk_apb";
263
+
xlnx,bus-width = <64>;
264
+
};
265
+
266
+
lpd_dma_chan5: dma@ffac0000 {
267
+
status = "disabled";
268
+
compatible = "xlnx,zynqmp-dma-1.0";
269
+
reg = <0x0 0xffac0000 0x0 0x1000>;
270
+
interrupt-parent = <&gic>;
271
+
interrupts = <0 81 4>;
272
+
clock-names = "clk_main", "clk_apb";
273
+
xlnx,bus-width = <64>;
274
+
};
275
+
276
+
lpd_dma_chan6: dma@ffad0000 {
277
+
status = "disabled";
278
+
compatible = "xlnx,zynqmp-dma-1.0";
279
+
reg = <0x0 0xffad0000 0x0 0x1000>;
280
+
interrupt-parent = <&gic>;
281
+
interrupts = <0 82 4>;
282
+
clock-names = "clk_main", "clk_apb";
283
+
xlnx,bus-width = <64>;
284
+
};
285
+
286
+
lpd_dma_chan7: dma@ffae0000 {
287
+
status = "disabled";
288
+
compatible = "xlnx,zynqmp-dma-1.0";
289
+
reg = <0x0 0xffae0000 0x0 0x1000>;
290
+
interrupt-parent = <&gic>;
291
+
interrupts = <0 83 4>;
292
+
clock-names = "clk_main", "clk_apb";
293
+
xlnx,bus-width = <64>;
294
+
};
295
+
296
+
lpd_dma_chan8: dma@ffaf0000 {
297
+
status = "disabled";
298
+
compatible = "xlnx,zynqmp-dma-1.0";
299
+
reg = <0x0 0xffaf0000 0x0 0x1000>;
300
+
interrupt-parent = <&gic>;
301
+
interrupts = <0 84 4>;
302
+
clock-names = "clk_main", "clk_apb";
303
+
xlnx,bus-width = <64>;
171
304
};
172
305
173
306
gem0: ethernet@ff0b0000 {
···
450
215
<0x0 0xfd480000 0x0 0x1000>,
451
216
<0x80 0x00000000 0x0 0x1000000>;
452
217
reg-names = "breg", "pcireg", "cfg";
453
-
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
454
-
0xe0000000 0x00000000 0x10000000
455
-
/* non-prefetchable memory */
456
-
0x43000000 0x00000006 0x00000000 0x00000006
457
-
0x00000000 0x00000002 0x00000000>;
458
-
/* prefetchable memory */
218
+
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
219
+
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
220
+
bus-range = <0x00 0xff>;
459
221
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
460
222
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
461
223
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
···
463
231
#address-cells = <0>;
464
232
#interrupt-cells = <1>;
465
233
};
234
+
};
235
+
236
+
rtc: rtc@ffa60000 {
237
+
compatible = "xlnx,zynqmp-rtc";
238
+
status = "disabled";
239
+
reg = <0x0 0xffa60000 0x0 0x100>;
240
+
interrupt-parent = <&gic>;
241
+
interrupts = <0 26 4>, <0 27 4>;
242
+
interrupt-names = "alarm", "sec";
243
+
calibration = <0x8000>;
466
244
};
467
245
468
246
sata: ahci@fd0c0000 {
···
504
262
smmu: smmu@fd800000 {
505
263
compatible = "arm,mmu-500";
506
264
reg = <0x0 0xfd800000 0x0 0x20000>;
265
+
status = "disabled";
507
266
#global-interrupts = <1>;
508
267
interrupt-parent = <&gic>;
509
-
interrupts = <0 157 4>,
510
-
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
511
-
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
512
-
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
513
-
<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
268
+
interrupts = <0 155 4>,
269
+
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
270
+
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
271
+
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
272
+
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
514
273
};
515
274
516
275
spi0: spi@ff040000 {
···
573
330
};
574
331
575
332
uart0: serial@ff000000 {
576
-
compatible = "cdns,uart-r1p8";
333
+
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
577
334
status = "disabled";
578
335
interrupt-parent = <&gic>;
579
336
interrupts = <0 21 4>;
···
582
339
};
583
340
584
341
uart1: serial@ff010000 {
585
-
compatible = "cdns,uart-r1p8";
342
+
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
586
343
status = "disabled";
587
344
interrupt-parent = <&gic>;
588
345
interrupts = <0 22 4>;