Merge tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux into soc/dt

+15

Documentation/devicetree/bindings/arm/apple.yaml

··· 19 19 - MacBook Air (M1, 2020) 20 20 - iMac (24-inch, M1, 2021) 21 21 22 + Devices based on the "M2" SoC: 23 + 24 + - MacBook Air (M2, 2022) 25 + - MacBook Pro (13-inch, M2, 2022) 26 + - Mac mini (M2, 2023) 27 + 22 28 And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: 23 29 24 30 - MacBook Pro (14-inch, M1 Pro, 2021) ··· 74 68 - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021) 75 69 - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) 76 70 - const: apple,t8103 71 + - const: apple,arm-platform 72 + 73 + - description: Apple M2 SoC based platforms 74 + items: 75 + - enum: 76 + - apple,j413 # MacBook Air (M2, 2022) 77 + - apple,j473 # Mac mini (M2, 2023) 78 + - apple,j493 # MacBook Pro (13-inch, M2, 2022) 79 + - const: apple,t8112 77 80 - const: apple,arm-platform 78 81 79 82 - description: Apple M1 Pro SoC based platforms

+1

Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml

··· 23 23 items: 24 24 - enum: 25 25 - apple,t8103-pmgr 26 + - apple,t8112-pmgr 26 27 - apple,t6000-pmgr 27 28 - const: apple,pmgr 28 29 - const: syscon

+2

Documentation/devicetree/bindings/arm/cpus.yaml

··· 85 85 86 86 compatible: 87 87 enum: 88 + - apple,avalanche 89 + - apple,blizzard 88 90 - apple,icestorm 89 91 - apple,firestorm 90 92 - arm,arm710t

+1

Documentation/devicetree/bindings/clock/apple,nco.yaml

··· 23 23 - enum: 24 24 - apple,t6000-nco 25 25 - apple,t8103-nco 26 + - apple,t8112-nco 26 27 - const: apple,nco 27 28 28 29 clocks:

+1

Documentation/devicetree/bindings/i2c/apple,i2c.yaml

··· 23 23 items: 24 24 - enum: 25 25 - apple,t8103-i2c 26 + - apple,t8112-i2c 26 27 - apple,t6000-i2c 27 28 - const: apple,i2c 28 29

+19 -3

Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml

··· 31 31 properties: 32 32 compatible: 33 33 items: 34 - - const: apple,t6000-aic 34 + - enum: 35 + - apple,t8112-aic 36 + - apple,t6000-aic 35 37 - const: apple,aic2 36 38 37 39 interrupt-controller: true 38 40 39 41 '#interrupt-cells': 40 - const: 4 42 + minimum: 3 43 + maximum: 4 41 44 description: | 42 45 The 1st cell contains the interrupt type: 43 46 - 0: Hardware IRQ 44 47 - 1: FIQ 45 48 46 - The 2nd cell contains the die ID. 49 + The 2nd cell contains the die ID (only present on apple,t6000-aic). 47 50 48 51 The next cell contains the interrupt number. 49 52 - HW IRQs: interrupt number ··· 112 109 113 110 allOf: 114 111 - $ref: /schemas/interrupt-controller.yaml# 112 + - if: 113 + properties: 114 + compatible: 115 + contains: 116 + const: apple,t8112-aic 117 + then: 118 + properties: 119 + '#interrupt-cells': 120 + const: 3 121 + else: 122 + properties: 123 + '#interrupt-cells': 124 + const: 4 115 125 116 126 examples: 117 127 - |

+7 -3

Documentation/devicetree/bindings/iommu/apple,sart.yaml

··· 28 28 29 29 properties: 30 30 compatible: 31 - enum: 32 - - apple,t6000-sart 33 - - apple,t8103-sart 31 + oneOf: 32 + - items: 33 + - const: apple,t8112-sart 34 + - const: apple,t6000-sart 35 + - enum: 36 + - apple,t6000-sart 37 + - apple,t8103-sart 34 38 35 39 reg: 36 40 maxItems: 1

+2

Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml

··· 29 29 items: 30 30 - enum: 31 31 - apple,t8103-asc-mailbox 32 + - apple,t8112-asc-mailbox 32 33 - apple,t6000-asc-mailbox 33 34 - const: apple,asc-mailbox-v4 34 35 ··· 40 39 items: 41 40 - enum: 42 41 - apple,t8103-m3-mailbox 42 + - apple,t8112-m3-mailbox 43 43 - apple,t6000-m3-mailbox 44 44 - const: apple,m3-mailbox-v2 45 45

+4 -1

Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml

··· 14 14 items: 15 15 - enum: 16 16 - apple,t8103-nvme-ans2 17 + - apple,t8112-nvme-ans2 17 18 - apple,t6000-nvme-ans2 18 19 - const: apple,nvme-ans2 19 20 ··· 66 65 properties: 67 66 compatible: 68 67 contains: 69 - const: apple,t8103-nvme-ans2 68 + enum: 69 + - apple,t8103-nvme-ans2 70 + - apple,t8112-nvme-ans2 70 71 then: 71 72 properties: 72 73 power-domains:

+1

Documentation/devicetree/bindings/pci/apple,pcie.yaml

··· 33 33 items: 34 34 - enum: 35 35 - apple,t8103-pcie 36 + - apple,t8112-pcie 36 37 - apple,t6000-pcie 37 38 - const: apple,pcie 38 39

+1

Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml

··· 19 19 items: 20 20 - enum: 21 21 - apple,t8103-pinctrl 22 + - apple,t8112-pinctrl 22 23 - apple,t6000-pinctrl 23 24 - const: apple,pinctrl 24 25

+1

Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml

··· 32 32 items: 33 33 - enum: 34 34 - apple,t8103-pmgr-pwrstate 35 + - apple,t8112-pmgr-pwrstate 35 36 - apple,t6000-pmgr-pwrstate 36 37 - const: apple,pmgr-pwrstate 37 38

+1

Documentation/devicetree/bindings/watchdog/apple,wdt.yaml

··· 17 17 items: 18 18 - enum: 19 19 - apple,t8103-wdt 20 + - apple,t8112-wdt 20 21 - apple,t6000-wdt 21 22 - const: apple,wdt 22 23

+3

arch/arm64/boot/dts/apple/Makefile

··· 10 10 dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb 11 11 dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb 12 12 dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb 13 + dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb 14 + dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb 15 + dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb

+4

arch/arm64/boot/dts/apple/t600x-die0.dtsi

··· 233 233 interrupt-parent = <&aic>; 234 234 interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>; 235 235 power-domains = <&ps_apcie_gp_sys>; 236 + status = "disabled"; 236 237 }; 237 238 238 239 pcie0_dart_3: iommu@584008000 { ··· 243 242 interrupt-parent = <&aic>; 244 243 interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>; 245 244 power-domains = <&ps_apcie_gp_sys>; 245 + status = "disabled"; 246 246 }; 247 247 248 248 pcie0: pcie@590000000 { ··· 340 338 <0 0 0 2 &port02 0 0 0 1>, 341 339 <0 0 0 3 &port02 0 0 0 2>, 342 340 <0 0 0 4 &port02 0 0 0 3>; 341 + status = "disabled"; 343 342 }; 344 343 345 344 port03: pci@3,0 { ··· 360 357 <0 0 0 2 &port03 0 0 0 1>, 361 358 <0 0 0 3 &port03 0 0 0 2>, 362 359 <0 0 0 4 &port03 0 0 0 3>; 360 + status = "disabled"; 363 361 }; 364 362 };

-11

arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi

··· 101 101 wp-inverted; 102 102 }; 103 103 }; 104 - 105 - &pcie0_dart_2 { 106 - status = "disabled"; 107 - }; 108 - 109 - &pcie0_dart_3 { 110 - status = "disabled"; 111 - }; 112 - 113 - /delete-node/ &port02; 114 - /delete-node/ &port03;

+11

arch/arm64/boot/dts/apple/t600x-j375.dtsi

··· 104 104 &port02 { 105 105 /* 10 Gbit Ethernet */ 106 106 bus-range = <3 3>; 107 + status = "okay"; 107 108 ethernet0: ethernet@0,0 { 108 109 reg = <0x30000 0x0 0x0 0x0 0x0>; 109 110 /* To be filled by the loader */ ··· 115 114 &port03 { 116 115 /* USB xHCI */ 117 116 bus-range = <4 4>; 117 + status = "okay"; 118 + }; 119 + 120 + 121 + &pcie0_dart_2 { 122 + status = "okay"; 123 + }; 124 + 125 + &pcie0_dart_3 { 126 + status = "okay"; 118 127 };

+10

arch/arm64/boot/dts/apple/t8103-j274.dts

··· 37 37 38 38 &port01 { 39 39 bus-range = <2 2>; 40 + status = "okay"; 40 41 }; 41 42 42 43 &port02 { 43 44 bus-range = <3 3>; 45 + status = "okay"; 44 46 ethernet0: ethernet@0,0 { 45 47 reg = <0x30000 0x0 0x0 0x0 0x0>; 46 48 /* To be filled by the loader */ 47 49 local-mac-address = [00 10 18 00 00 00]; 48 50 }; 51 + }; 52 + 53 + &pcie0_dart_1 { 54 + status = "okay"; 55 + }; 56 + 57 + &pcie0_dart_2 { 58 + status = "okay"; 49 59 }; 50 60 51 61 &i2c2 {

-15

arch/arm64/boot/dts/apple/t8103-j293.dts

··· 25 25 brcm,board-type = "apple,honshu"; 26 26 }; 27 27 28 - /* 29 - * Remove unused PCIe ports and disable the associated DARTs. 30 - */ 31 - 32 - &pcie0_dart_1 { 33 - status = "disabled"; 34 - }; 35 - 36 - &pcie0_dart_2 { 37 - status = "disabled"; 38 - }; 39 - 40 - /delete-node/ &port01; 41 - /delete-node/ &port02; 42 - 43 28 &i2c2 { 44 29 status = "okay"; 45 30 };

-15

arch/arm64/boot/dts/apple/t8103-j313.dts

··· 24 24 &wifi0 { 25 25 brcm,board-type = "apple,shikoku"; 26 26 }; 27 - 28 - /* 29 - * Remove unused PCIe ports and disable the associated DARTs. 30 - */ 31 - 32 - &pcie0_dart_1 { 33 - status = "disabled"; 34 - }; 35 - 36 - &pcie0_dart_2 { 37 - status = "disabled"; 38 - }; 39 - 40 - /delete-node/ &port01; 41 - /delete-node/ &port02;

+10

arch/arm64/boot/dts/apple/t8103-j456.dts

··· 55 55 56 56 &port01 { 57 57 bus-range = <2 2>; 58 + status = "okay"; 58 59 }; 59 60 60 61 &port02 { 61 62 bus-range = <3 3>; 63 + status = "okay"; 62 64 ethernet0: ethernet@0,0 { 63 65 reg = <0x30000 0x0 0x0 0x0 0x0>; 64 66 /* To be filled by the loader */ 65 67 local-mac-address = [00 10 18 00 00 00]; 66 68 }; 69 + }; 70 + 71 + &pcie0_dart_1 { 72 + status = "okay"; 73 + }; 74 + 75 + &pcie0_dart_2 { 76 + status = "okay"; 67 77 };

+3 -8

arch/arm64/boot/dts/apple/t8103-j457.dts

··· 37 37 38 38 &port02 { 39 39 bus-range = <3 3>; 40 + status = "okay"; 40 41 ethernet0: ethernet@0,0 { 41 42 reg = <0x30000 0x0 0x0 0x0 0x0>; 42 43 /* To be filled by the loader */ ··· 45 44 }; 46 45 }; 47 46 48 - /* 49 - * Remove unused PCIe port and disable the associated DART. 50 - */ 51 - 52 - &pcie0_dart_1 { 53 - status = "disabled"; 47 + &pcie0_dart_2 { 48 + status = "okay"; 54 49 }; 55 - 56 - /delete-node/ &port01;

+4

arch/arm64/boot/dts/apple/t8103.dtsi

··· 724 724 interrupt-parent = <&aic>; 725 725 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 726 726 power-domains = <&ps_apcie_gp>; 727 + status = "disabled"; 727 728 }; 728 729 729 730 pcie0_dart_2: iommu@683008000 { ··· 734 733 interrupt-parent = <&aic>; 735 734 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 736 735 power-domains = <&ps_apcie_gp>; 736 + status = "disabled"; 737 737 }; 738 738 739 739 pcie0: pcie@690000000 { ··· 809 807 <0 0 0 2 &port01 0 0 0 1>, 810 808 <0 0 0 3 &port01 0 0 0 2>, 811 809 <0 0 0 4 &port01 0 0 0 3>; 810 + status = "disabled"; 812 811 }; 813 812 814 813 port02: pci@2,0 { ··· 829 826 <0 0 0 2 &port02 0 0 0 1>, 830 827 <0 0 0 3 &port02 0 0 0 2>, 831 828 <0 0 0 4 &port02 0 0 0 3>; 829 + status = "disabled"; 832 830 }; 833 831 }; 834 832 };

+63

arch/arm64/boot/dts/apple/t8112-j413.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Apple MacBook Air (M2, 2022) 4 + * 5 + * target-type: J413 6 + * 7 + * Copyright The Asahi Linux Contributors 8 + */ 9 + 10 + /dts-v1/; 11 + 12 + #include "t8112.dtsi" 13 + #include "t8112-jxxx.dtsi" 14 + 15 + / { 16 + compatible = "apple,j413", "apple,t8112", "apple,arm-platform"; 17 + model = "Apple MacBook Air (13-inch, M2, 2022)"; 18 + 19 + aliases { 20 + bluetooth0 = &bluetooth0; 21 + wifi0 = &wifi0; 22 + }; 23 + }; 24 + 25 + /* 26 + * Force the bus number assignments so that we can declare some of the 27 + * on-board devices and properties that are populated by the bootloader 28 + * (such as MAC addresses). 29 + */ 30 + &port00 { 31 + bus-range = <1 1>; 32 + wifi0: wifi@0,0 { 33 + compatible = "pci14e4,4433"; 34 + reg = <0x10000 0x0 0x0 0x0 0x0>; 35 + /* To be filled by the loader */ 36 + local-mac-address = [00 10 18 00 00 10]; 37 + apple,antenna-sku = "XX"; 38 + brcm,board-type = "apple,hokkaido"; 39 + }; 40 + 41 + bluetooth0: bluetooth@0,1 { 42 + compatible = "pci14e4,5f71"; 43 + reg = <0x10100 0x0 0x0 0x0 0x0>; 44 + /* To be filled by the loader */ 45 + local-bd-address = [00 00 00 00 00 00]; 46 + brcm,board-type = "apple,hokkaido"; 47 + }; 48 + }; 49 + 50 + &i2c0 { 51 + /* MagSafe port */ 52 + hpm5: usb-pd@3a { 53 + compatible = "apple,cd321x"; 54 + reg = <0x3a>; 55 + interrupt-parent = <&pinctrl_ap>; 56 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 57 + interrupt-names = "irq"; 58 + }; 59 + }; 60 + 61 + &i2c4 { 62 + status = "okay"; 63 + };

+54

arch/arm64/boot/dts/apple/t8112-j473.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Apple Mac mini (M2, 2023) 4 + * 5 + * target-type: J473 6 + * 7 + * Copyright The Asahi Linux Contributors 8 + */ 9 + 10 + /dts-v1/; 11 + 12 + #include "t8112.dtsi" 13 + #include "t8112-jxxx.dtsi" 14 + 15 + / { 16 + compatible = "apple,j473", "apple,t8112", "apple,arm-platform"; 17 + model = "Apple Mac mini (M2, 2023)"; 18 + 19 + aliases { 20 + ethernet0 = &ethernet0; 21 + }; 22 + }; 23 + 24 + /* 25 + * Force the bus number assignments so that we can declare some of the 26 + * on-board devices and properties that are populated by the bootloader 27 + * (such as MAC addresses). 28 + */ 29 + &port00 { 30 + bus-range = <1 1>; 31 + }; 32 + 33 + &port01 { 34 + bus-range = <2 2>; 35 + status = "okay"; 36 + }; 37 + 38 + &port02 { 39 + bus-range = <3 3>; 40 + status = "okay"; 41 + ethernet0: ethernet@0,0 { 42 + reg = <0x30000 0x0 0x0 0x0 0x0>; 43 + /* To be filled by the loader */ 44 + local-mac-address = [00 10 18 00 00 00]; 45 + }; 46 + }; 47 + 48 + &pcie1_dart { 49 + status = "okay"; 50 + }; 51 + 52 + &pcie2_dart { 53 + status = "okay"; 54 + };

+52

arch/arm64/boot/dts/apple/t8112-j493.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Apple MacBook Pro (13-inch, M1, 2022) 4 + * 5 + * target-type: J493 6 + * 7 + * Copyright The Asahi Linux Contributors 8 + */ 9 + 10 + /dts-v1/; 11 + 12 + #include "t8112.dtsi" 13 + #include "t8112-jxxx.dtsi" 14 + 15 + / { 16 + compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; 17 + model = "Apple MacBook Pro (13-inch, M2, 2022)"; 18 + 19 + aliases { 20 + bluetooth0 = &bluetooth0; 21 + wifi0 = &wifi0; 22 + }; 23 + }; 24 + 25 + /* 26 + * Force the bus number assignments so that we can declare some of the 27 + * on-board devices and properties that are populated by the bootloader 28 + * (such as MAC addresses). 29 + */ 30 + &port00 { 31 + bus-range = <1 1>; 32 + wifi0: wifi@0,0 { 33 + compatible = "pci14e4,4425"; 34 + reg = <0x10000 0x0 0x0 0x0 0x0>; 35 + /* To be filled by the loader */ 36 + local-mac-address = [00 00 00 00 00 00]; 37 + apple,antenna-sku = "XX"; 38 + brcm,board-type = "apple,kyushu"; 39 + }; 40 + 41 + bluetooth0: bluetooth@0,1 { 42 + compatible = "pci14e4,5f69"; 43 + reg = <0x10100 0x0 0x0 0x0 0x0>; 44 + /* To be filled by the loader */ 45 + local-bd-address = [00 00 00 00 00 00]; 46 + brcm,board-type = "apple,kyushu"; 47 + }; 48 + }; 49 + 50 + &i2c4 { 51 + status = "okay"; 52 + };

+81

arch/arm64/boot/dts/apple/t8112-jxxx.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Apple M2 MacBook Air/Pro (M2, 2022) 4 + * 5 + * This file contains parts common to all Apple M2 devices using the t8112. 6 + * 7 + * target-type: J493, J413 8 + * 9 + * Copyright The Asahi Linux Contributors 10 + */ 11 + 12 + / { 13 + aliases { 14 + serial0 = &serial0; 15 + serial2 = &serial2; 16 + }; 17 + 18 + chosen { 19 + #address-cells = <2>; 20 + #size-cells = <2>; 21 + ranges; 22 + 23 + stdout-path = "serial0"; 24 + 25 + framebuffer0: framebuffer@0 { 26 + compatible = "apple,simple-framebuffer", "simple-framebuffer"; 27 + reg = <0 0 0 0>; /* To be filled by loader */ 28 + /* Format properties will be added by loader */ 29 + status = "disabled"; 30 + }; 31 + }; 32 + 33 + memory@800000000 { 34 + device_type = "memory"; 35 + reg = <0x8 0 0x2 0>; /* To be filled by loader */ 36 + }; 37 + }; 38 + 39 + &serial0 { 40 + status = "okay"; 41 + }; 42 + 43 + &serial2 { 44 + status = "okay"; 45 + }; 46 + 47 + &i2c0 { 48 + status = "okay"; 49 + 50 + hpm0: usb-pd@38 { 51 + compatible = "apple,cd321x"; 52 + reg = <0x38>; 53 + interrupt-parent = <&pinctrl_ap>; 54 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 55 + interrupt-names = "irq"; 56 + }; 57 + 58 + hpm1: usb-pd@3f { 59 + compatible = "apple,cd321x"; 60 + reg = <0x3f>; 61 + interrupt-parent = <&pinctrl_ap>; 62 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 63 + interrupt-names = "irq"; 64 + }; 65 + }; 66 + 67 + &i2c1 { 68 + status = "okay"; 69 + }; 70 + 71 + &i2c2 { 72 + status = "okay"; 73 + }; 74 + 75 + &i2c3 { 76 + status = "okay"; 77 + }; 78 + 79 + &nco_clkref { 80 + clock-frequency = <900000000>; 81 + };

+1140

arch/arm64/boot/dts/apple/t8112-pmgr.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * PMGR Power domains for the Apple T8112 "M2" SoC 4 + * 5 + * Copyright The Asahi Linux Contributors 6 + */ 7 + 8 + 9 + &pmgr { 10 + ps_sbr: power-controller@100 { 11 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 12 + reg = <0x100 4>; 13 + #power-domain-cells = <0>; 14 + #reset-cells = <0>; 15 + label = "sbr"; 16 + apple,always-on; /* Core device */ 17 + }; 18 + 19 + ps_aic: power-controller@108 { 20 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 21 + reg = <0x108 4>; 22 + #power-domain-cells = <0>; 23 + #reset-cells = <0>; 24 + label = "aic"; 25 + apple,always-on; /* Core device */ 26 + }; 27 + 28 + ps_dwi: power-controller@110 { 29 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 30 + reg = <0x110 4>; 31 + #power-domain-cells = <0>; 32 + #reset-cells = <0>; 33 + label = "dwi"; 34 + apple,always-on; /* Core device */ 35 + }; 36 + 37 + ps_soc_spmi0: power-controller@118 { 38 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 39 + reg = <0x118 4>; 40 + #power-domain-cells = <0>; 41 + #reset-cells = <0>; 42 + label = "soc_spmi0"; 43 + }; 44 + 45 + ps_gpio: power-controller@120 { 46 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 47 + reg = <0x120 4>; 48 + #power-domain-cells = <0>; 49 + #reset-cells = <0>; 50 + label = "gpio"; 51 + }; 52 + 53 + ps_pms_busif: power-controller@128 { 54 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 55 + reg = <0x128 4>; 56 + #power-domain-cells = <0>; 57 + #reset-cells = <0>; 58 + label = "pms_busif"; 59 + apple,always-on; /* Core device */ 60 + }; 61 + 62 + ps_pms: power-controller@130 { 63 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 64 + reg = <0x130 4>; 65 + #power-domain-cells = <0>; 66 + #reset-cells = <0>; 67 + label = "pms"; 68 + apple,always-on; /* Core device */ 69 + }; 70 + 71 + ps_pms_c1ppt: power-controller@160 { 72 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 73 + reg = <0x160 4>; 74 + #power-domain-cells = <0>; 75 + #reset-cells = <0>; 76 + label = "pms_c1ppt"; 77 + power-domains = <&ps_pms>; 78 + }; 79 + 80 + ps_soc_dpe: power-controller@168 { 81 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 82 + reg = <0x168 4>; 83 + #power-domain-cells = <0>; 84 + #reset-cells = <0>; 85 + label = "soc_dpe"; 86 + apple,always-on; /* Core device */ 87 + }; 88 + 89 + ps_pmgr_soc_ocla: power-controller@170 { 90 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 91 + reg = <0x170 4>; 92 + #power-domain-cells = <0>; 93 + #reset-cells = <0>; 94 + label = "pmgr_soc_ocla"; 95 + power-domains = <&ps_pms>; 96 + }; 97 + 98 + ps_ispsens0: power-controller@178 { 99 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 100 + reg = <0x178 4>; 101 + #power-domain-cells = <0>; 102 + #reset-cells = <0>; 103 + label = "ispsens0"; 104 + }; 105 + 106 + ps_ispsens1: power-controller@180 { 107 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 108 + reg = <0x180 4>; 109 + #power-domain-cells = <0>; 110 + #reset-cells = <0>; 111 + label = "ispsens1"; 112 + }; 113 + 114 + ps_ispsens2: power-controller@188 { 115 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 116 + reg = <0x188 4>; 117 + #power-domain-cells = <0>; 118 + #reset-cells = <0>; 119 + label = "ispsens2"; 120 + }; 121 + 122 + ps_ispsens3: power-controller@190 { 123 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 124 + reg = <0x190 4>; 125 + #power-domain-cells = <0>; 126 + #reset-cells = <0>; 127 + label = "ispsens3"; 128 + }; 129 + 130 + ps_pcie_ref: power-controller@198 { 131 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 132 + reg = <0x198 4>; 133 + #power-domain-cells = <0>; 134 + #reset-cells = <0>; 135 + label = "pcie_ref"; 136 + }; 137 + 138 + ps_aft0: power-controller@1a0 { 139 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 140 + reg = <0x1a0 4>; 141 + #power-domain-cells = <0>; 142 + #reset-cells = <0>; 143 + label = "aft0"; 144 + }; 145 + 146 + ps_imx: power-controller@1a8 { 147 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 148 + reg = <0x1a8 4>; 149 + #power-domain-cells = <0>; 150 + #reset-cells = <0>; 151 + label = "imx"; 152 + apple,always-on; /* Apple fabric, critical block */ 153 + }; 154 + 155 + ps_sio_busif: power-controller@1b0 { 156 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 157 + reg = <0x1b0 4>; 158 + #power-domain-cells = <0>; 159 + #reset-cells = <0>; 160 + label = "sio_busif"; 161 + }; 162 + 163 + ps_sio: power-controller@1b8 { 164 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 165 + reg = <0x1b8 4>; 166 + #power-domain-cells = <0>; 167 + #reset-cells = <0>; 168 + label = "sio"; 169 + apple,always-on; 170 + power-domains = <&ps_sio_busif>; 171 + }; 172 + 173 + ps_sio_cpu: power-controller@1c0 { 174 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 175 + reg = <0x1c0 4>; 176 + #power-domain-cells = <0>; 177 + #reset-cells = <0>; 178 + label = "sio_cpu"; 179 + power-domains = <&ps_sio>; 180 + }; 181 + 182 + ps_fpwm0: power-controller@1c8 { 183 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 184 + reg = <0x1c8 4>; 185 + #power-domain-cells = <0>; 186 + #reset-cells = <0>; 187 + label = "fpwm0"; 188 + power-domains = <&ps_sio>; 189 + }; 190 + 191 + ps_fpwm1: power-controller@1d0 { 192 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 193 + reg = <0x1d0 4>; 194 + #power-domain-cells = <0>; 195 + #reset-cells = <0>; 196 + label = "fpwm1"; 197 + power-domains = <&ps_sio>; 198 + }; 199 + 200 + ps_fpwm2: power-controller@1d8 { 201 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 202 + reg = <0x1d8 4>; 203 + #power-domain-cells = <0>; 204 + #reset-cells = <0>; 205 + label = "fpwm2"; 206 + power-domains = <&ps_sio>; 207 + }; 208 + 209 + ps_i2c0: power-controller@1e0 { 210 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 211 + reg = <0x1e0 4>; 212 + #power-domain-cells = <0>; 213 + #reset-cells = <0>; 214 + label = "i2c0"; 215 + power-domains = <&ps_sio>; 216 + }; 217 + 218 + ps_i2c1: power-controller@1e8 { 219 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 220 + reg = <0x1e8 4>; 221 + #power-domain-cells = <0>; 222 + #reset-cells = <0>; 223 + label = "i2c1"; 224 + power-domains = <&ps_sio>; 225 + }; 226 + 227 + ps_i2c2: power-controller@1f0 { 228 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 229 + reg = <0x1f0 4>; 230 + #power-domain-cells = <0>; 231 + #reset-cells = <0>; 232 + label = "i2c2"; 233 + power-domains = <&ps_sio>; 234 + }; 235 + 236 + ps_i2c3: power-controller@1f8 { 237 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 238 + reg = <0x1f8 4>; 239 + #power-domain-cells = <0>; 240 + #reset-cells = <0>; 241 + label = "i2c3"; 242 + power-domains = <&ps_sio>; 243 + }; 244 + 245 + ps_i2c4: power-controller@200 { 246 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 247 + reg = <0x200 4>; 248 + #power-domain-cells = <0>; 249 + #reset-cells = <0>; 250 + label = "i2c4"; 251 + power-domains = <&ps_sio>; 252 + }; 253 + 254 + ps_spi_p: power-controller@208 { 255 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 256 + reg = <0x208 4>; 257 + #power-domain-cells = <0>; 258 + #reset-cells = <0>; 259 + label = "spi_p"; 260 + power-domains = <&ps_sio>; 261 + }; 262 + 263 + ps_uart_p: power-controller@210 { 264 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 265 + reg = <0x210 4>; 266 + #power-domain-cells = <0>; 267 + #reset-cells = <0>; 268 + label = "uart_p"; 269 + power-domains = <&ps_sio>; 270 + }; 271 + 272 + ps_audio_p: power-controller@218 { 273 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 274 + reg = <0x218 4>; 275 + #power-domain-cells = <0>; 276 + #reset-cells = <0>; 277 + label = "audio_p"; 278 + power-domains = <&ps_sio>; 279 + }; 280 + 281 + ps_aes: power-controller@220 { 282 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 283 + reg = <0x220 4>; 284 + #power-domain-cells = <0>; 285 + #reset-cells = <0>; 286 + label = "aes"; 287 + power-domains = <&ps_sio>; 288 + }; 289 + 290 + ps_spi0: power-controller@228 { 291 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 292 + reg = <0x228 4>; 293 + #power-domain-cells = <0>; 294 + #reset-cells = <0>; 295 + label = "spi0"; 296 + power-domains = <&ps_spi_p>; 297 + }; 298 + 299 + ps_spi1: power-controller@230 { 300 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 301 + reg = <0x230 4>; 302 + #power-domain-cells = <0>; 303 + #reset-cells = <0>; 304 + label = "spi1"; 305 + power-domains = <&ps_spi_p>; 306 + }; 307 + 308 + ps_spi2: power-controller@238 { 309 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 310 + reg = <0x238 4>; 311 + #power-domain-cells = <0>; 312 + #reset-cells = <0>; 313 + label = "spi2"; 314 + power-domains = <&ps_spi_p>; 315 + }; 316 + 317 + ps_spi3: power-controller@240 { 318 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 319 + reg = <0x240 4>; 320 + #power-domain-cells = <0>; 321 + #reset-cells = <0>; 322 + label = "spi3"; 323 + power-domains = <&ps_spi_p>; 324 + }; 325 + 326 + ps_spi4: power-controller@248 { 327 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 328 + reg = <0x248 4>; 329 + #power-domain-cells = <0>; 330 + #reset-cells = <0>; 331 + label = "spi4"; 332 + power-domains = <&ps_spi_p>; 333 + }; 334 + 335 + ps_spi5: power-controller@250 { 336 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 337 + reg = <0x250 4>; 338 + #power-domain-cells = <0>; 339 + #reset-cells = <0>; 340 + label = "spi5"; 341 + power-domains = <&ps_spi_p>; 342 + }; 343 + 344 + ps_uart_n: power-controller@258 { 345 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 346 + reg = <0x258 4>; 347 + #power-domain-cells = <0>; 348 + #reset-cells = <0>; 349 + label = "uart_n"; 350 + power-domains = <&ps_uart_p>; 351 + }; 352 + 353 + ps_uart0: power-controller@260 { 354 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 355 + reg = <0x260 4>; 356 + #power-domain-cells = <0>; 357 + #reset-cells = <0>; 358 + label = "uart0"; 359 + power-domains = <&ps_uart_p>; 360 + }; 361 + 362 + ps_uart1: power-controller@268 { 363 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 364 + reg = <0x268 4>; 365 + #power-domain-cells = <0>; 366 + #reset-cells = <0>; 367 + label = "uart1"; 368 + power-domains = <&ps_uart_p>; 369 + }; 370 + 371 + ps_uart2: power-controller@270 { 372 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 373 + reg = <0x270 4>; 374 + #power-domain-cells = <0>; 375 + #reset-cells = <0>; 376 + label = "uart2"; 377 + power-domains = <&ps_uart_p>; 378 + }; 379 + 380 + ps_uart3: power-controller@278 { 381 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 382 + reg = <0x278 4>; 383 + #power-domain-cells = <0>; 384 + #reset-cells = <0>; 385 + label = "uart3"; 386 + power-domains = <&ps_uart_p>; 387 + }; 388 + 389 + ps_uart4: power-controller@280 { 390 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 391 + reg = <0x280 4>; 392 + #power-domain-cells = <0>; 393 + #reset-cells = <0>; 394 + label = "uart4"; 395 + power-domains = <&ps_uart_p>; 396 + }; 397 + 398 + ps_uart5: power-controller@288 { 399 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 400 + reg = <0x288 4>; 401 + #power-domain-cells = <0>; 402 + #reset-cells = <0>; 403 + label = "uart5"; 404 + power-domains = <&ps_uart_p>; 405 + }; 406 + 407 + ps_uart6: power-controller@290 { 408 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 409 + reg = <0x290 4>; 410 + #power-domain-cells = <0>; 411 + #reset-cells = <0>; 412 + label = "uart6"; 413 + power-domains = <&ps_uart_p>; 414 + }; 415 + 416 + ps_uart7: power-controller@298 { 417 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 418 + reg = <0x298 4>; 419 + #power-domain-cells = <0>; 420 + #reset-cells = <0>; 421 + label = "uart7"; 422 + power-domains = <&ps_uart_p>; 423 + }; 424 + 425 + ps_uart8: power-controller@2a0 { 426 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 427 + reg = <0x2a0 4>; 428 + #power-domain-cells = <0>; 429 + #reset-cells = <0>; 430 + label = "uart8"; 431 + power-domains = <&ps_uart_p>; 432 + }; 433 + 434 + ps_sio_adma: power-controller@2a8 { 435 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 436 + reg = <0x2a8 4>; 437 + #power-domain-cells = <0>; 438 + #reset-cells = <0>; 439 + label = "sio_adma"; 440 + power-domains = <&ps_spi_p>, <&ps_audio_p>; 441 + }; 442 + 443 + ps_dpa0: power-controller@2b0 { 444 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 445 + reg = <0x2b0 4>; 446 + #power-domain-cells = <0>; 447 + #reset-cells = <0>; 448 + label = "dpa0"; 449 + power-domains = <&ps_audio_p>; 450 + }; 451 + 452 + ps_dpa1: power-controller@2b8 { 453 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 454 + reg = <0x2b8 4>; 455 + #power-domain-cells = <0>; 456 + #reset-cells = <0>; 457 + label = "dpa1"; 458 + power-domains = <&ps_audio_p>; 459 + }; 460 + 461 + ps_mca0: power-controller@2c0 { 462 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 463 + reg = <0x2c0 4>; 464 + #power-domain-cells = <0>; 465 + #reset-cells = <0>; 466 + label = "mca0"; 467 + power-domains = <&ps_sio_adma>, <&ps_audio_p>; 468 + }; 469 + 470 + ps_mca1: power-controller@2c8 { 471 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 472 + reg = <0x2c8 4>; 473 + #power-domain-cells = <0>; 474 + #reset-cells = <0>; 475 + label = "mca1"; 476 + power-domains = <&ps_sio_adma>, <&ps_audio_p>; 477 + }; 478 + 479 + ps_mca2: power-controller@2d0 { 480 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 481 + reg = <0x2d0 4>; 482 + #power-domain-cells = <0>; 483 + #reset-cells = <0>; 484 + label = "mca2"; 485 + power-domains = <&ps_sio_adma>, <&ps_audio_p>; 486 + }; 487 + 488 + ps_mca3: power-controller@2d8 { 489 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 490 + reg = <0x2d8 4>; 491 + #power-domain-cells = <0>; 492 + #reset-cells = <0>; 493 + label = "mca3"; 494 + power-domains = <&ps_sio_adma>, <&ps_audio_p>; 495 + }; 496 + 497 + ps_mca4: power-controller@2e0 { 498 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 499 + reg = <0x2e0 4>; 500 + #power-domain-cells = <0>; 501 + #reset-cells = <0>; 502 + label = "mca4"; 503 + power-domains = <&ps_sio_adma>, <&ps_audio_p>; 504 + }; 505 + 506 + ps_mca5: power-controller@2e8 { 507 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 508 + reg = <0x2e8 4>; 509 + #power-domain-cells = <0>; 510 + #reset-cells = <0>; 511 + label = "mca5"; 512 + power-domains = <&ps_sio_adma>, <&ps_audio_p>; 513 + }; 514 + 515 + ps_mcc: power-controller@2f0 { 516 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 517 + reg = <0x2f0 4>; 518 + #power-domain-cells = <0>; 519 + #reset-cells = <0>; 520 + label = "mcc"; 521 + apple,always-on; /* Memory controller */ 522 + }; 523 + 524 + ps_dcs0: power-controller@2f8 { 525 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 526 + reg = <0x2f8 4>; 527 + #power-domain-cells = <0>; 528 + #reset-cells = <0>; 529 + label = "dcs0"; 530 + apple,always-on; /* LPDDR4 interface */ 531 + }; 532 + 533 + ps_dcs2: power-controller@300 { 534 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 535 + reg = <0x300 4>; 536 + #power-domain-cells = <0>; 537 + #reset-cells = <0>; 538 + label = "dcs2"; 539 + apple,always-on; /* LPDDR4 interface */ 540 + }; 541 + 542 + ps_dcs1: power-controller@308 { 543 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 544 + reg = <0x308 4>; 545 + #power-domain-cells = <0>; 546 + #reset-cells = <0>; 547 + label = "dcs1"; 548 + apple,always-on; /* LPDDR4 interface */ 549 + }; 550 + 551 + ps_dcs3: power-controller@310 { 552 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 553 + reg = <0x310 4>; 554 + #power-domain-cells = <0>; 555 + #reset-cells = <0>; 556 + label = "dcs3"; 557 + apple,always-on; /* LPDDR4 interface */ 558 + }; 559 + 560 + ps_dcs4: power-controller@318 { 561 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 562 + reg = <0x318 4>; 563 + #power-domain-cells = <0>; 564 + #reset-cells = <0>; 565 + label = "dcs4"; 566 + apple,always-on; /* LPDDR4 interface */ 567 + }; 568 + 569 + ps_dcs5: power-controller@320 { 570 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 571 + reg = <0x320 4>; 572 + #power-domain-cells = <0>; 573 + #reset-cells = <0>; 574 + label = "dcs5"; 575 + apple,always-on; /* LPDDR4 interface */ 576 + }; 577 + 578 + ps_dcs6: power-controller@328 { 579 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 580 + reg = <0x328 4>; 581 + #power-domain-cells = <0>; 582 + #reset-cells = <0>; 583 + label = "dcs6"; 584 + apple,always-on; /* LPDDR4 interface */ 585 + }; 586 + 587 + ps_dcs7: power-controller@330 { 588 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 589 + reg = <0x330 4>; 590 + #power-domain-cells = <0>; 591 + #reset-cells = <0>; 592 + label = "dcs7"; 593 + apple,always-on; /* LPDDR4 interface */ 594 + }; 595 + 596 + ps_smx0: power-controller@338 { 597 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 598 + reg = <0x338 4>; 599 + #power-domain-cells = <0>; 600 + #reset-cells = <0>; 601 + label = "smx0"; 602 + apple,always-on; /* Apple fabric, critical block */ 603 + }; 604 + 605 + ps_smx1: power-controller@340 { 606 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 607 + reg = <0x340 4>; 608 + #power-domain-cells = <0>; 609 + #reset-cells = <0>; 610 + label = "smx1"; 611 + apple,always-on; /* Apple fabric, critical block */ 612 + }; 613 + 614 + ps_apcie: power-controller@348 { 615 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 616 + reg = <0x348 4>; 617 + #power-domain-cells = <0>; 618 + #reset-cells = <0>; 619 + label = "apcie"; 620 + power-domains = <&ps_imx>, <&ps_pcie_ref>; 621 + }; 622 + 623 + ps_rmx0: power-controller@350 { 624 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 625 + reg = <0x350 4>; 626 + #power-domain-cells = <0>; 627 + #reset-cells = <0>; 628 + label = "rmx0"; 629 + /* Apple Fabric, display/image stuff: this can power down */ 630 + }; 631 + 632 + ps_rmx1: power-controller@358 { 633 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 634 + reg = <0x358 4>; 635 + #power-domain-cells = <0>; 636 + #reset-cells = <0>; 637 + label = "rmx1"; 638 + /* Apple Fabric, display/image stuff: this can power down */ 639 + }; 640 + 641 + ps_cmx: power-controller@360 { 642 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 643 + reg = <0x360 4>; 644 + #power-domain-cells = <0>; 645 + #reset-cells = <0>; 646 + label = "cmx"; 647 + apple,always-on; /* Apple fabric, critical block */ 648 + }; 649 + 650 + ps_mmx: power-controller@368 { 651 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 652 + reg = <0x368 4>; 653 + #power-domain-cells = <0>; 654 + #reset-cells = <0>; 655 + label = "mmx"; 656 + /* Apple Fabric, media stuff: this can power down */ 657 + }; 658 + 659 + ps_disp0_sys: power-controller@370 { 660 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 661 + reg = <0x370 4>; 662 + #power-domain-cells = <0>; 663 + #reset-cells = <0>; 664 + label = "disp0_sys"; 665 + power-domains = <&ps_rmx1>; 666 + apple,always-on; /* TODO: figure out if we can enable PM here */ 667 + }; 668 + 669 + ps_disp0_fe: power-controller@378 { 670 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 671 + reg = <0x378 4>; 672 + #power-domain-cells = <0>; 673 + #reset-cells = <0>; 674 + label = "disp0_fe"; 675 + power-domains = <&ps_disp0_sys>; 676 + apple,always-on; /* TODO: figure out if we can enable PM here */ 677 + }; 678 + 679 + ps_dispext_sys: power-controller@380 { 680 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 681 + reg = <0x380 4>; 682 + #power-domain-cells = <0>; 683 + #reset-cells = <0>; 684 + label = "dispext_sys"; 685 + power-domains = <&ps_rmx0>; 686 + }; 687 + 688 + ps_dispext_fe: power-controller@388 { 689 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 690 + reg = <0x388 4>; 691 + #power-domain-cells = <0>; 692 + #reset-cells = <0>; 693 + label = "dispext_fe"; 694 + power-domains = <&ps_dispext_sys>; 695 + }; 696 + 697 + ps_dispext_cpu0: power-controller@3c8 { 698 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 699 + reg = <0x3c8 4>; 700 + #power-domain-cells = <0>; 701 + #reset-cells = <0>; 702 + label = "dispext_cpu0"; 703 + power-domains = <&ps_dispext_fe>; 704 + apple,min-state = <4>; 705 + }; 706 + 707 + ps_dptx_ext_phy: power-controller@3d8 { 708 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 709 + reg = <0x3d8 4>; 710 + #power-domain-cells = <0>; 711 + #reset-cells = <0>; 712 + label = "dptx_ext_phy"; 713 + }; 714 + 715 + ps_dispdfr_fe: power-controller@3e0 { 716 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 717 + reg = <0x3e0 4>; 718 + #power-domain-cells = <0>; 719 + #reset-cells = <0>; 720 + label = "dispdfr_fe"; 721 + power-domains = <&ps_rmx0>; 722 + }; 723 + 724 + ps_dispdfr_be: power-controller@3e8 { 725 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 726 + reg = <0x3e8 4>; 727 + #power-domain-cells = <0>; 728 + #reset-cells = <0>; 729 + label = "dispdfr_be"; 730 + power-domains = <&ps_dispdfr_fe>; 731 + }; 732 + 733 + ps_mipi_dsi: power-controller@3f0 { 734 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 735 + reg = <0x3f0 4>; 736 + #power-domain-cells = <0>; 737 + #reset-cells = <0>; 738 + label = "mipi_dsi"; 739 + power-domains = <&ps_dispdfr_be>; 740 + }; 741 + 742 + ps_jpg: power-controller@3f8 { 743 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 744 + reg = <0x3f8 4>; 745 + #power-domain-cells = <0>; 746 + #reset-cells = <0>; 747 + label = "jpg"; 748 + power-domains = <&ps_cmx>; 749 + }; 750 + 751 + ps_apcie_gp: power-controller@400 { 752 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 753 + reg = <0x400 4>; 754 + #power-domain-cells = <0>; 755 + #reset-cells = <0>; 756 + label = "apcie_gp"; 757 + power-domains = <&ps_apcie>; 758 + apple,always-on; /* Breaks things if shut down */ 759 + }; 760 + 761 + ps_msr: power-controller@408 { 762 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 763 + reg = <0x408 4>; 764 + #power-domain-cells = <0>; 765 + #reset-cells = <0>; 766 + label = "msr"; 767 + power-domains = <&ps_imx>; 768 + }; 769 + 770 + ps_pmp: power-controller@410 { 771 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 772 + reg = <0x410 4>; 773 + #power-domain-cells = <0>; 774 + #reset-cells = <0>; 775 + label = "pmp"; 776 + apple,always-on; 777 + }; 778 + 779 + ps_pms_sram: power-controller@418 { 780 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 781 + reg = <0x418 4>; 782 + #power-domain-cells = <0>; 783 + #reset-cells = <0>; 784 + label = "pms_sram"; 785 + apple,always-on; 786 + }; 787 + 788 + ps_msr_ase_core: power-controller@420 { 789 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 790 + reg = <0x420 4>; 791 + #power-domain-cells = <0>; 792 + #reset-cells = <0>; 793 + label = "msr_ase_core"; 794 + power-domains = <&ps_msr>; 795 + }; 796 + 797 + ps_ans: power-controller@428 { 798 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 799 + reg = <0x428 4>; 800 + #power-domain-cells = <0>; 801 + #reset-cells = <0>; 802 + label = "ans"; 803 + power-domains = <&ps_imx>; 804 + }; 805 + 806 + ps_gfx: power-controller@430 { 807 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 808 + reg = <0x430 4>; 809 + #power-domain-cells = <0>; 810 + #reset-cells = <0>; 811 + label = "gfx"; 812 + }; 813 + 814 + ps_isp_sys: power-controller@438 { 815 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 816 + reg = <0x438 4>; 817 + #power-domain-cells = <0>; 818 + #reset-cells = <0>; 819 + label = "isp_sys"; 820 + power-domains = <&ps_rmx1>; 821 + }; 822 + 823 + ps_venc_sys: power-controller@440 { 824 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 825 + reg = <0x440 4>; 826 + #power-domain-cells = <0>; 827 + #reset-cells = <0>; 828 + label = "venc_sys"; 829 + power-domains = <&ps_rmx1>; 830 + }; 831 + 832 + ps_avd_sys: power-controller@448 { 833 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 834 + reg = <0x448 4>; 835 + #power-domain-cells = <0>; 836 + #reset-cells = <0>; 837 + label = "avd_sys"; 838 + power-domains = <&ps_mmx>; 839 + }; 840 + 841 + ps_apcie_st: power-controller@450 { 842 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 843 + reg = <0x450 4>; 844 + #power-domain-cells = <0>; 845 + #reset-cells = <0>; 846 + label = "apcie_st"; 847 + power-domains = <&ps_apcie>, <&ps_ans>; 848 + }; 849 + 850 + ps_atc0_common: power-controller@458 { 851 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 852 + reg = <0x458 4>; 853 + #power-domain-cells = <0>; 854 + #reset-cells = <0>; 855 + label = "atc0_common"; 856 + power-domains = <&ps_imx>; 857 + }; 858 + 859 + ps_atc0_pcie: power-controller@460 { 860 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 861 + reg = <0x460 4>; 862 + #power-domain-cells = <0>; 863 + #reset-cells = <0>; 864 + label = "atc0_pcie"; 865 + power-domains = <&ps_atc0_common>; 866 + }; 867 + 868 + ps_atc0_cio: power-controller@468 { 869 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 870 + reg = <0x468 4>; 871 + #power-domain-cells = <0>; 872 + #reset-cells = <0>; 873 + label = "atc0_cio"; 874 + power-domains = <&ps_atc0_common>; 875 + }; 876 + 877 + ps_atc0_cio_pcie: power-controller@470 { 878 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 879 + reg = <0x470 4>; 880 + #power-domain-cells = <0>; 881 + #reset-cells = <0>; 882 + label = "atc0_cio_pcie"; 883 + power-domains = <&ps_atc0_cio>; 884 + }; 885 + 886 + ps_atc0_cio_usb: power-controller@478 { 887 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 888 + reg = <0x478 4>; 889 + #power-domain-cells = <0>; 890 + #reset-cells = <0>; 891 + label = "atc0_cio_usb"; 892 + power-domains = <&ps_atc0_cio>; 893 + }; 894 + 895 + ps_atc1_common: power-controller@480 { 896 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 897 + reg = <0x480 4>; 898 + #power-domain-cells = <0>; 899 + #reset-cells = <0>; 900 + label = "atc1_common"; 901 + power-domains = <&ps_rmx0>; 902 + }; 903 + 904 + ps_atc1_pcie: power-controller@488 { 905 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 906 + reg = <0x488 4>; 907 + #power-domain-cells = <0>; 908 + #reset-cells = <0>; 909 + label = "atc1_pcie"; 910 + power-domains = <&ps_atc1_common>; 911 + }; 912 + 913 + ps_atc1_cio: power-controller@490 { 914 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 915 + reg = <0x490 4>; 916 + #power-domain-cells = <0>; 917 + #reset-cells = <0>; 918 + label = "atc1_cio"; 919 + power-domains = <&ps_atc1_common>; 920 + }; 921 + 922 + ps_atc1_cio_pcie: power-controller@498 { 923 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 924 + reg = <0x498 4>; 925 + #power-domain-cells = <0>; 926 + #reset-cells = <0>; 927 + label = "atc1_cio_pcie"; 928 + power-domains = <&ps_atc1_cio>; 929 + }; 930 + 931 + ps_atc1_cio_usb: power-controller@4a0 { 932 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 933 + reg = <0x4a0 4>; 934 + #power-domain-cells = <0>; 935 + #reset-cells = <0>; 936 + label = "atc1_cio_usb"; 937 + power-domains = <&ps_atc1_cio>; 938 + }; 939 + 940 + ps_ane_sys: power-controller@4a8 { 941 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 942 + reg = <0x4a8 4>; 943 + #power-domain-cells = <0>; 944 + #reset-cells = <0>; 945 + label = "ane_sys"; 946 + power-domains = <&ps_mmx>; 947 + }; 948 + 949 + ps_scodec: power-controller@4b0 { 950 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 951 + reg = <0x4b0 4>; 952 + #power-domain-cells = <0>; 953 + #reset-cells = <0>; 954 + label = "scodec"; 955 + power-domains = <&ps_rmx0>; 956 + }; 957 + 958 + ps_sep: power-controller@c00 { 959 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 960 + reg = <0xc00 4>; 961 + #power-domain-cells = <0>; 962 + #reset-cells = <0>; 963 + label = "sep"; 964 + apple,always-on; 965 + }; 966 + 967 + ps_venc_dma: power-controller@8000 { 968 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 969 + reg = <0x8000 4>; 970 + #power-domain-cells = <0>; 971 + #reset-cells = <0>; 972 + label = "venc_dma"; 973 + power-domains = <&ps_venc_sys>; 974 + }; 975 + 976 + ps_venc_pipe4: power-controller@8008 { 977 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 978 + reg = <0x8008 4>; 979 + #power-domain-cells = <0>; 980 + #reset-cells = <0>; 981 + label = "venc_pipe4"; 982 + power-domains = <&ps_venc_dma>; 983 + }; 984 + 985 + ps_venc_pipe5: power-controller@8010 { 986 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 987 + reg = <0x8010 4>; 988 + #power-domain-cells = <0>; 989 + #reset-cells = <0>; 990 + label = "venc_pipe5"; 991 + power-domains = <&ps_venc_dma>; 992 + }; 993 + 994 + ps_venc_me0: power-controller@8018 { 995 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 996 + reg = <0x8018 4>; 997 + #power-domain-cells = <0>; 998 + #reset-cells = <0>; 999 + label = "venc_me0"; 1000 + power-domains = <&ps_venc_pipe5>, <&ps_venc_pipe4>; 1001 + }; 1002 + 1003 + ps_venc_me1: power-controller@8020 { 1004 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1005 + reg = <0x8020 4>; 1006 + #power-domain-cells = <0>; 1007 + #reset-cells = <0>; 1008 + label = "venc_me1"; 1009 + power-domains = <&ps_venc_pipe5>, <&ps_venc_pipe4>; 1010 + }; 1011 + 1012 + ps_disp0_cpu0: power-controller@10000 { 1013 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1014 + reg = <0x10000 4>; 1015 + #power-domain-cells = <0>; 1016 + #reset-cells = <0>; 1017 + label = "disp0_cpu0"; 1018 + power-domains = <&ps_disp0_fe>; 1019 + apple,min-state = <4>; 1020 + }; 1021 + }; 1022 + 1023 + &pmgr_mini { 1024 + 1025 + ps_debug_gated: power-controller@58 { 1026 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1027 + reg = <0x58 4>; 1028 + #power-domain-cells = <0>; 1029 + #reset-cells = <0>; 1030 + label = "debug_gated"; 1031 + apple,always-on; /* Core AON device */ 1032 + }; 1033 + 1034 + ps_nub_spmi0: power-controller@60 { 1035 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1036 + reg = <0x60 4>; 1037 + #power-domain-cells = <0>; 1038 + #reset-cells = <0>; 1039 + label = "nub_spmi0"; 1040 + apple,always-on; /* Core AON device */ 1041 + }; 1042 + 1043 + ps_nub_spmi1: power-controller@68 { 1044 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1045 + reg = <0x68 4>; 1046 + #power-domain-cells = <0>; 1047 + #reset-cells = <0>; 1048 + label = "nub_spmi1"; 1049 + apple,always-on; /* Core AON device */ 1050 + }; 1051 + 1052 + ps_nub_aon: power-controller@70 { 1053 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1054 + reg = <0x70 4>; 1055 + #power-domain-cells = <0>; 1056 + #reset-cells = <0>; 1057 + label = "nub_aon"; 1058 + apple,always-on; /* Core AON device */ 1059 + }; 1060 + 1061 + ps_msg: power-controller@78 { 1062 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1063 + reg = <0x78 4>; 1064 + #power-domain-cells = <0>; 1065 + #reset-cells = <0>; 1066 + label = "msg"; 1067 + }; 1068 + 1069 + ps_nub_gpio: power-controller@80 { 1070 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1071 + reg = <0x80 4>; 1072 + #power-domain-cells = <0>; 1073 + #reset-cells = <0>; 1074 + label = "nub_gpio"; 1075 + apple,always-on; 1076 + }; 1077 + 1078 + ps_atc0_usb_aon: power-controller@88 { 1079 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1080 + reg = <0x88 4>; 1081 + #power-domain-cells = <0>; 1082 + #reset-cells = <0>; 1083 + label = "atc0_usb_aon"; 1084 + apple,always-on; /* Needs to stay on for dwc3 to work */ 1085 + }; 1086 + 1087 + ps_atc1_usb_aon: power-controller@90 { 1088 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1089 + reg = <0x90 4>; 1090 + #power-domain-cells = <0>; 1091 + #reset-cells = <0>; 1092 + label = "atc1_usb_aon"; 1093 + apple,always-on; /* Needs to stay on for dwc3 to work */ 1094 + }; 1095 + 1096 + ps_atc0_usb: power-controller@98 { 1097 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1098 + reg = <0x98 4>; 1099 + #power-domain-cells = <0>; 1100 + #reset-cells = <0>; 1101 + label = "atc0_usb"; 1102 + power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; 1103 + }; 1104 + 1105 + ps_atc1_usb: power-controller@a0 { 1106 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1107 + reg = <0xa0 4>; 1108 + #power-domain-cells = <0>; 1109 + #reset-cells = <0>; 1110 + label = "atc1_usb"; 1111 + power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; 1112 + }; 1113 + 1114 + ps_nub_fabric: power-controller@a8 { 1115 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1116 + reg = <0xa8 4>; 1117 + #power-domain-cells = <0>; 1118 + #reset-cells = <0>; 1119 + label = "nub_fabric"; 1120 + apple,always-on; /* Core AON device */ 1121 + }; 1122 + 1123 + ps_nub_sram: power-controller@b0 { 1124 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1125 + reg = <0xb0 4>; 1126 + #power-domain-cells = <0>; 1127 + #reset-cells = <0>; 1128 + label = "nub_sram"; 1129 + apple,always-on; /* Core AON device */ 1130 + }; 1131 + 1132 + ps_debug_switch: power-controller@b8 { 1133 + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; 1134 + reg = <0xb8 4>; 1135 + #power-domain-cells = <0>; 1136 + #reset-cells = <0>; 1137 + label = "debug_switch"; 1138 + apple,always-on; /* Core AON device */ 1139 + }; 1140 + };

+912

arch/arm64/boot/dts/apple/t8112.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Apple T8112 "M2" SoC 4 + * 5 + * Other names: H14G 6 + * 7 + * Copyright The Asahi Linux Contributors 8 + */ 9 + 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/interrupt-controller/apple-aic.h> 12 + #include <dt-bindings/interrupt-controller/irq.h> 13 + #include <dt-bindings/pinctrl/apple.h> 14 + #include <dt-bindings/spmi/spmi.h> 15 + 16 + / { 17 + compatible = "apple,t8112", "apple,arm-platform"; 18 + 19 + #address-cells = <2>; 20 + #size-cells = <2>; 21 + 22 + cpus { 23 + #address-cells = <2>; 24 + #size-cells = <0>; 25 + 26 + cpu-map { 27 + cluster0 { 28 + core0 { 29 + cpu = <&cpu_e0>; 30 + }; 31 + core1 { 32 + cpu = <&cpu_e1>; 33 + }; 34 + core2 { 35 + cpu = <&cpu_e2>; 36 + }; 37 + core3 { 38 + cpu = <&cpu_e3>; 39 + }; 40 + }; 41 + 42 + cluster1 { 43 + core0 { 44 + cpu = <&cpu_p0>; 45 + }; 46 + core1 { 47 + cpu = <&cpu_p1>; 48 + }; 49 + core2 { 50 + cpu = <&cpu_p2>; 51 + }; 52 + core3 { 53 + cpu = <&cpu_p3>; 54 + }; 55 + }; 56 + }; 57 + 58 + cpu_e0: cpu@0 { 59 + compatible = "apple,blizzard"; 60 + device_type = "cpu"; 61 + reg = <0x0 0x0>; 62 + enable-method = "spin-table"; 63 + cpu-release-addr = <0 0>; /* To be filled by loader */ 64 + operating-points-v2 = <&ecluster_opp>; 65 + capacity-dmips-mhz = <756>; 66 + performance-domains = <&cpufreq_e>; 67 + next-level-cache = <&l2_cache_0>; 68 + i-cache-size = <0x20000>; 69 + d-cache-size = <0x10000>; 70 + }; 71 + 72 + cpu_e1: cpu@1 { 73 + compatible = "apple,blizzard"; 74 + device_type = "cpu"; 75 + reg = <0x0 0x1>; 76 + enable-method = "spin-table"; 77 + cpu-release-addr = <0 0>; /* To be filled by loader */ 78 + operating-points-v2 = <&ecluster_opp>; 79 + capacity-dmips-mhz = <756>; 80 + performance-domains = <&cpufreq_e>; 81 + next-level-cache = <&l2_cache_0>; 82 + i-cache-size = <0x20000>; 83 + d-cache-size = <0x10000>; 84 + }; 85 + 86 + cpu_e2: cpu@2 { 87 + compatible = "apple,blizzard"; 88 + device_type = "cpu"; 89 + reg = <0x0 0x2>; 90 + enable-method = "spin-table"; 91 + cpu-release-addr = <0 0>; /* To be filled by loader */ 92 + operating-points-v2 = <&ecluster_opp>; 93 + capacity-dmips-mhz = <756>; 94 + performance-domains = <&cpufreq_e>; 95 + next-level-cache = <&l2_cache_0>; 96 + i-cache-size = <0x20000>; 97 + d-cache-size = <0x10000>; 98 + }; 99 + 100 + cpu_e3: cpu@3 { 101 + compatible = "apple,blizzard"; 102 + device_type = "cpu"; 103 + reg = <0x0 0x3>; 104 + enable-method = "spin-table"; 105 + cpu-release-addr = <0 0>; /* To be filled by loader */ 106 + operating-points-v2 = <&ecluster_opp>; 107 + capacity-dmips-mhz = <756>; 108 + performance-domains = <&cpufreq_e>; 109 + next-level-cache = <&l2_cache_0>; 110 + i-cache-size = <0x20000>; 111 + d-cache-size = <0x10000>; 112 + }; 113 + 114 + cpu_p0: cpu@10100 { 115 + compatible = "apple,avalanche"; 116 + device_type = "cpu"; 117 + reg = <0x0 0x10100>; 118 + enable-method = "spin-table"; 119 + cpu-release-addr = <0 0>; /* To be filled by loader */ 120 + operating-points-v2 = <&pcluster_opp>; 121 + capacity-dmips-mhz = <1024>; 122 + performance-domains = <&cpufreq_p>; 123 + next-level-cache = <&l2_cache_1>; 124 + i-cache-size = <0x30000>; 125 + d-cache-size = <0x20000>; 126 + }; 127 + 128 + cpu_p1: cpu@10101 { 129 + compatible = "apple,avalanche"; 130 + device_type = "cpu"; 131 + reg = <0x0 0x10101>; 132 + enable-method = "spin-table"; 133 + cpu-release-addr = <0 0>; /* To be filled by loader */ 134 + operating-points-v2 = <&pcluster_opp>; 135 + capacity-dmips-mhz = <1024>; 136 + performance-domains = <&cpufreq_p>; 137 + next-level-cache = <&l2_cache_1>; 138 + i-cache-size = <0x30000>; 139 + d-cache-size = <0x20000>; 140 + }; 141 + 142 + cpu_p2: cpu@10102 { 143 + compatible = "apple,avalanche"; 144 + device_type = "cpu"; 145 + reg = <0x0 0x10102>; 146 + enable-method = "spin-table"; 147 + cpu-release-addr = <0 0>; /* To be filled by loader */ 148 + operating-points-v2 = <&pcluster_opp>; 149 + capacity-dmips-mhz = <1024>; 150 + performance-domains = <&cpufreq_p>; 151 + next-level-cache = <&l2_cache_1>; 152 + i-cache-size = <0x30000>; 153 + d-cache-size = <0x20000>; 154 + }; 155 + 156 + cpu_p3: cpu@10103 { 157 + compatible = "apple,avalanche"; 158 + device_type = "cpu"; 159 + reg = <0x0 0x10103>; 160 + enable-method = "spin-table"; 161 + cpu-release-addr = <0 0>; /* To be filled by loader */ 162 + operating-points-v2 = <&pcluster_opp>; 163 + capacity-dmips-mhz = <1024>; 164 + performance-domains = <&cpufreq_p>; 165 + next-level-cache = <&l2_cache_1>; 166 + i-cache-size = <0x30000>; 167 + d-cache-size = <0x20000>; 168 + }; 169 + 170 + l2_cache_0: l2-cache-0 { 171 + compatible = "cache"; 172 + cache-level = <2>; 173 + cache-unified; 174 + cache-size = <0x400000>; 175 + }; 176 + 177 + l2_cache_1: l2-cache-1 { 178 + compatible = "cache"; 179 + cache-level = <2>; 180 + cache-unified; 181 + cache-size = <0x1000000>; 182 + }; 183 + }; 184 + 185 + ecluster_opp: opp-table-0 { 186 + compatible = "operating-points-v2"; 187 + opp-shared; 188 + 189 + opp01 { 190 + opp-hz = /bits/ 64 <600000000>; 191 + opp-level = <1>; 192 + clock-latency-ns = <7500>; 193 + }; 194 + opp02 { 195 + opp-hz = /bits/ 64 <912000000>; 196 + opp-level = <2>; 197 + clock-latency-ns = <20000>; 198 + }; 199 + opp03 { 200 + opp-hz = /bits/ 64 <1284000000>; 201 + opp-level = <3>; 202 + clock-latency-ns = <22000>; 203 + }; 204 + opp04 { 205 + opp-hz = /bits/ 64 <1752000000>; 206 + opp-level = <4>; 207 + clock-latency-ns = <30000>; 208 + }; 209 + opp05 { 210 + opp-hz = /bits/ 64 <2004000000>; 211 + opp-level = <5>; 212 + clock-latency-ns = <35000>; 213 + }; 214 + opp06 { 215 + opp-hz = /bits/ 64 <2256000000>; 216 + opp-level = <6>; 217 + clock-latency-ns = <39000>; 218 + }; 219 + opp07 { 220 + opp-hz = /bits/ 64 <2424000000>; 221 + opp-level = <7>; 222 + clock-latency-ns = <53000>; 223 + }; 224 + }; 225 + 226 + pcluster_opp: opp-table-1 { 227 + compatible = "operating-points-v2"; 228 + opp-shared; 229 + 230 + opp01 { 231 + opp-hz = /bits/ 64 <660000000>; 232 + opp-level = <1>; 233 + clock-latency-ns = <9000>; 234 + }; 235 + opp02 { 236 + opp-hz = /bits/ 64 <924000000>; 237 + opp-level = <2>; 238 + clock-latency-ns = <19000>; 239 + }; 240 + opp03 { 241 + opp-hz = /bits/ 64 <1188000000>; 242 + opp-level = <3>; 243 + clock-latency-ns = <22000>; 244 + }; 245 + opp04 { 246 + opp-hz = /bits/ 64 <1452000000>; 247 + opp-level = <4>; 248 + clock-latency-ns = <24000>; 249 + }; 250 + opp05 { 251 + opp-hz = /bits/ 64 <1704000000>; 252 + opp-level = <5>; 253 + clock-latency-ns = <26000>; 254 + }; 255 + opp06 { 256 + opp-hz = /bits/ 64 <1968000000>; 257 + opp-level = <6>; 258 + clock-latency-ns = <28000>; 259 + }; 260 + opp07 { 261 + opp-hz = /bits/ 64 <2208000000>; 262 + opp-level = <7>; 263 + clock-latency-ns = <30000>; 264 + }; 265 + opp08 { 266 + opp-hz = /bits/ 64 <2400000000>; 267 + opp-level = <8>; 268 + clock-latency-ns = <33000>; 269 + }; 270 + opp09 { 271 + opp-hz = /bits/ 64 <2568000000>; 272 + opp-level = <9>; 273 + clock-latency-ns = <34000>; 274 + }; 275 + opp10 { 276 + opp-hz = /bits/ 64 <2724000000>; 277 + opp-level = <10>; 278 + clock-latency-ns = <36000>; 279 + }; 280 + opp11 { 281 + opp-hz = /bits/ 64 <2868000000>; 282 + opp-level = <11>; 283 + clock-latency-ns = <41000>; 284 + }; 285 + opp12 { 286 + opp-hz = /bits/ 64 <2988000000>; 287 + opp-level = <12>; 288 + clock-latency-ns = <42000>; 289 + }; 290 + opp13 { 291 + opp-hz = /bits/ 64 <3096000000>; 292 + opp-level = <13>; 293 + clock-latency-ns = <44000>; 294 + }; 295 + opp14 { 296 + opp-hz = /bits/ 64 <3204000000>; 297 + opp-level = <14>; 298 + clock-latency-ns = <46000>; 299 + }; 300 + /* Not available until CPU deep sleep is implemented */ 301 + #if 0 302 + opp15 { 303 + opp-hz = /bits/ 64 <3324000000>; 304 + opp-level = <15>; 305 + clock-latency-ns = <62000>; 306 + turbo-mode; 307 + }; 308 + opp16 { 309 + opp-hz = /bits/ 64 <3408000000>; 310 + opp-level = <16>; 311 + clock-latency-ns = <62000>; 312 + turbo-mode; 313 + }; 314 + opp17 { 315 + opp-hz = /bits/ 64 <3504000000>; 316 + opp-level = <17>; 317 + clock-latency-ns = <62000>; 318 + turbo-mode; 319 + }; 320 + #endif 321 + }; 322 + 323 + timer { 324 + compatible = "arm,armv8-timer"; 325 + interrupt-parent = <&aic>; 326 + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 327 + interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 328 + <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 329 + <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 330 + <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 331 + }; 332 + 333 + pmu-e { 334 + compatible = "apple,blizzard-pmu"; 335 + interrupt-parent = <&aic>; 336 + interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 337 + }; 338 + 339 + pmu-p { 340 + compatible = "apple,avalanche-pmu"; 341 + interrupt-parent = <&aic>; 342 + interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 343 + }; 344 + 345 + clkref: clock-ref { 346 + compatible = "fixed-clock"; 347 + #clock-cells = <0>; 348 + clock-frequency = <24000000>; 349 + clock-output-names = "clkref"; 350 + }; 351 + 352 + /* 353 + * This is a fabulated representation of the input clock 354 + * to NCO since we don't know the true clock tree. 355 + */ 356 + nco_clkref: clock-ref-nco { 357 + compatible = "fixed-clock"; 358 + #clock-cells = <0>; 359 + clock-output-names = "nco_ref"; 360 + }; 361 + 362 + soc { 363 + compatible = "simple-bus"; 364 + #address-cells = <2>; 365 + #size-cells = <2>; 366 + 367 + ranges; 368 + nonposted-mmio; 369 + 370 + cpufreq_e: cpufreq@210e20000 { 371 + compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 372 + reg = <0x2 0x10e20000 0 0x1000>; 373 + #performance-domain-cells = <0>; 374 + }; 375 + 376 + cpufreq_p: cpufreq@211e20000 { 377 + compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 378 + reg = <0x2 0x11e20000 0 0x1000>; 379 + #performance-domain-cells = <0>; 380 + }; 381 + 382 + sio_dart: iommu@235004000 { 383 + compatible = "apple,t8110-dart"; 384 + reg = <0x2 0x35004000 0x0 0x4000>; 385 + interrupt-parent = <&aic>; 386 + interrupts = <AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH>; 387 + #iommu-cells = <1>; 388 + power-domains = <&ps_sio_cpu>; 389 + }; 390 + 391 + i2c0: i2c@235010000 { 392 + compatible = "apple,t8112-i2c", "apple,i2c"; 393 + reg = <0x2 0x35010000 0x0 0x4000>; 394 + clocks = <&clkref>; 395 + interrupt-parent = <&aic>; 396 + interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>; 397 + pinctrl-0 = <&i2c0_pins>; 398 + pinctrl-names = "default"; 399 + #address-cells = <0x1>; 400 + #size-cells = <0x0>; 401 + power-domains = <&ps_i2c0>; 402 + status = "disabled"; 403 + }; 404 + 405 + i2c1: i2c@235014000 { 406 + compatible = "apple,t8112-i2c", "apple,i2c"; 407 + reg = <0x2 0x35014000 0x0 0x4000>; 408 + clocks = <&clkref>; 409 + interrupt-parent = <&aic>; 410 + interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>; 411 + pinctrl-0 = <&i2c1_pins>; 412 + pinctrl-names = "default"; 413 + #address-cells = <0x1>; 414 + #size-cells = <0x0>; 415 + power-domains = <&ps_i2c1>; 416 + status = "disabled"; 417 + }; 418 + 419 + i2c2: i2c@235018000 { 420 + compatible = "apple,t8112-i2c", "apple,i2c"; 421 + reg = <0x2 0x35018000 0x0 0x4000>; 422 + clocks = <&clkref>; 423 + interrupt-parent = <&aic>; 424 + interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>; 425 + pinctrl-0 = <&i2c2_pins>; 426 + pinctrl-names = "default"; 427 + #address-cells = <0x1>; 428 + #size-cells = <0x0>; 429 + power-domains = <&ps_i2c2>; 430 + status = "disabled"; 431 + }; 432 + 433 + i2c3: i2c@23501c000 { 434 + compatible = "apple,t8112-i2c", "apple,i2c"; 435 + reg = <0x2 0x3501c000 0x0 0x4000>; 436 + clocks = <&clkref>; 437 + interrupt-parent = <&aic>; 438 + interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>; 439 + pinctrl-0 = <&i2c3_pins>; 440 + pinctrl-names = "default"; 441 + #address-cells = <0x1>; 442 + #size-cells = <0x0>; 443 + power-domains = <&ps_i2c3>; 444 + status = "disabled"; 445 + }; 446 + 447 + i2c4: i2c@235020000 { 448 + compatible = "apple,t8112-i2c", "apple,i2c"; 449 + reg = <0x2 0x35020000 0x0 0x4000>; 450 + clocks = <&clkref>; 451 + interrupt-parent = <&aic>; 452 + interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>; 453 + pinctrl-0 = <&i2c4_pins>; 454 + pinctrl-names = "default"; 455 + #address-cells = <0x1>; 456 + #size-cells = <0x0>; 457 + power-domains = <&ps_i2c4>; 458 + status = "disabled"; 459 + }; 460 + 461 + serial0: serial@235200000 { 462 + compatible = "apple,s5l-uart"; 463 + reg = <0x2 0x35200000 0x0 0x1000>; 464 + reg-io-width = <4>; 465 + interrupt-parent = <&aic>; 466 + interrupts = <AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH>; 467 + /* 468 + * TODO: figure out the clocking properly, there may 469 + * be a third selectable clock. 470 + */ 471 + clocks = <&clkref>, <&clkref>; 472 + clock-names = "uart", "clk_uart_baud0"; 473 + power-domains = <&ps_uart0>; 474 + status = "disabled"; 475 + }; 476 + 477 + serial2: serial@235208000 { 478 + compatible = "apple,s5l-uart"; 479 + reg = <0x2 0x35208000 0x0 0x1000>; 480 + reg-io-width = <4>; 481 + interrupt-parent = <&aic>; 482 + interrupts = <AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH>; 483 + clocks = <&clkref>, <&clkref>; 484 + clock-names = "uart", "clk_uart_baud0"; 485 + power-domains = <&ps_uart2>; 486 + status = "disabled"; 487 + }; 488 + 489 + admac: dma-controller@238200000 { 490 + compatible = "apple,t8112-admac", "apple,admac"; 491 + reg = <0x2 0x38200000 0x0 0x34000>; 492 + dma-channels = <24>; 493 + interrupts-extended = <0>, 494 + <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>, 495 + <0>, 496 + <0>; 497 + #dma-cells = <1>; 498 + iommus = <&sio_dart 2>; 499 + power-domains = <&ps_sio_adma>; 500 + resets = <&ps_audio_p>; 501 + }; 502 + 503 + mca: i2s@238400000 { 504 + compatible = "apple,t8112-mca", "apple,mca"; 505 + reg = <0x2 0x38400000 0x0 0x18000>, 506 + <0x2 0x38300000 0x0 0x30000>; 507 + 508 + interrupt-parent = <&aic>; 509 + interrupts = <AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH>, 510 + <AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH>, 511 + <AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH>, 512 + <AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH>, 513 + <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>, 514 + <AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH>; 515 + 516 + resets = <&ps_audio_p>; 517 + clocks = <&nco 0>, <&nco 1>, <&nco 2>, 518 + <&nco 3>, <&nco 4>, <&nco 4>; 519 + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 520 + <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 521 + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 522 + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 523 + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 524 + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 525 + <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 526 + <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 527 + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 528 + "tx1a", "rx1a", "tx1b", "rx1b", 529 + "tx2a", "rx2a", "tx2b", "rx2b", 530 + "tx3a", "rx3a", "tx3b", "rx3b", 531 + "tx4a", "rx4a", "tx4b", "rx4b", 532 + "tx5a", "rx5a", "tx5b", "rx5b"; 533 + 534 + #sound-dai-cells = <1>; 535 + }; 536 + 537 + nco: clock-controller@23b044000 { 538 + compatible = "apple,t8112-nco", "apple,nco"; 539 + reg = <0x2 0x3b044000 0x0 0x14000>; 540 + clocks = <&nco_clkref>; 541 + #clock-cells = <1>; 542 + }; 543 + 544 + aic: interrupt-controller@23b0c0000 { 545 + compatible = "apple,t8112-aic", "apple,aic2"; 546 + #interrupt-cells = <3>; 547 + interrupt-controller; 548 + reg = <0x2 0x3b0c0000 0x0 0x8000>, 549 + <0x2 0x3b0c8000 0x0 0x4>; 550 + reg-names = "core", "event"; 551 + power-domains = <&ps_aic>; 552 + 553 + affinities { 554 + e-core-pmu-affinity { 555 + apple,fiq-index = <AIC_CPU_PMU_E>; 556 + cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 557 + }; 558 + 559 + p-core-pmu-affinity { 560 + apple,fiq-index = <AIC_CPU_PMU_P>; 561 + cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 562 + }; 563 + }; 564 + }; 565 + 566 + pmgr: power-management@23b700000 { 567 + compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 568 + #address-cells = <1>; 569 + #size-cells = <1>; 570 + reg = <0x2 0x3b700000 0 0x14000>; 571 + /* child nodes are added in t8103-pmgr.dtsi */ 572 + }; 573 + 574 + pinctrl_ap: pinctrl@23c100000 { 575 + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 576 + reg = <0x2 0x3c100000 0x0 0x100000>; 577 + power-domains = <&ps_gpio>; 578 + 579 + gpio-controller; 580 + #gpio-cells = <2>; 581 + gpio-ranges = <&pinctrl_ap 0 0 213>; 582 + apple,npins = <213>; 583 + 584 + interrupt-controller; 585 + #interrupt-cells = <2>; 586 + interrupt-parent = <&aic>; 587 + interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 588 + <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 589 + <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 590 + <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 591 + <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 592 + <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 593 + <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 594 + 595 + i2c0_pins: i2c0-pins { 596 + pinmux = <APPLE_PINMUX(111, 1)>, 597 + <APPLE_PINMUX(110, 1)>; 598 + }; 599 + 600 + i2c1_pins: i2c1-pins { 601 + pinmux = <APPLE_PINMUX(113, 1)>, 602 + <APPLE_PINMUX(112, 1)>; 603 + }; 604 + 605 + i2c2_pins: i2c2-pins { 606 + pinmux = <APPLE_PINMUX(87, 1)>, 607 + <APPLE_PINMUX(86, 1)>; 608 + }; 609 + 610 + i2c3_pins: i2c3-pins { 611 + pinmux = <APPLE_PINMUX(54, 1)>, 612 + <APPLE_PINMUX(53, 1)>; 613 + }; 614 + 615 + i2c4_pins: i2c4-pins { 616 + pinmux = <APPLE_PINMUX(131, 1)>, 617 + <APPLE_PINMUX(130, 1)>; 618 + }; 619 + 620 + spi3_pins: spi3-pins { 621 + pinmux = <APPLE_PINMUX(46, 1)>, 622 + <APPLE_PINMUX(47, 1)>, 623 + <APPLE_PINMUX(48, 1)>, 624 + <APPLE_PINMUX(49, 1)>; 625 + }; 626 + 627 + pcie_pins: pcie-pins { 628 + pinmux = <APPLE_PINMUX(162, 1)>, 629 + <APPLE_PINMUX(163, 1)>, 630 + <APPLE_PINMUX(164, 1)>; 631 + // TODO: 1 more CLKREQs 632 + }; 633 + }; 634 + 635 + pinctrl_nub: pinctrl@23d1f0000 { 636 + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 637 + reg = <0x2 0x3d1f0000 0x0 0x4000>; 638 + power-domains = <&ps_nub_gpio>; 639 + 640 + gpio-controller; 641 + #gpio-cells = <2>; 642 + gpio-ranges = <&pinctrl_nub 0 0 24>; 643 + apple,npins = <24>; 644 + 645 + interrupt-controller; 646 + #interrupt-cells = <2>; 647 + interrupt-parent = <&aic>; 648 + interrupts = <AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH>, 649 + <AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH>, 650 + <AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH>, 651 + <AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH>, 652 + <AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH>, 653 + <AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH>, 654 + <AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH>; 655 + }; 656 + 657 + pmgr_mini: power-management@23d280000 { 658 + compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 659 + #address-cells = <1>; 660 + #size-cells = <1>; 661 + reg = <0x2 0x3d280000 0 0x4000>; 662 + /* child nodes are added in t8103-pmgr.dtsi */ 663 + }; 664 + 665 + wdt: watchdog@23d2b0000 { 666 + compatible = "apple,t8112-wdt", "apple,wdt"; 667 + reg = <0x2 0x3d2b0000 0x0 0x4000>; 668 + clocks = <&clkref>; 669 + interrupt-parent = <&aic>; 670 + interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>; 671 + }; 672 + 673 + pinctrl_smc: pinctrl@23e820000 { 674 + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 675 + reg = <0x2 0x3e820000 0x0 0x4000>; 676 + 677 + gpio-controller; 678 + #gpio-cells = <2>; 679 + gpio-ranges = <&pinctrl_smc 0 0 18>; 680 + apple,npins = <18>; 681 + 682 + interrupt-controller; 683 + #interrupt-cells = <2>; 684 + interrupt-parent = <&aic>; 685 + interrupts = <AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH>, 686 + <AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH>, 687 + <AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH>, 688 + <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>, 689 + <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>, 690 + <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>, 691 + <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>; 692 + }; 693 + 694 + pinctrl_aop: pinctrl@24a820000 { 695 + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 696 + reg = <0x2 0x4a820000 0x0 0x4000>; 697 + 698 + gpio-controller; 699 + #gpio-cells = <2>; 700 + gpio-ranges = <&pinctrl_aop 0 0 54>; 701 + apple,npins = <54>; 702 + 703 + interrupt-controller; 704 + #interrupt-cells = <2>; 705 + interrupt-parent = <&aic>; 706 + interrupts = <AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH>, 707 + <AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH>, 708 + <AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH>, 709 + <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>, 710 + <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>, 711 + <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>, 712 + <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; 713 + }; 714 + 715 + ans_mbox: mbox@277408000 { 716 + compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; 717 + reg = <0x2 0x77408000 0x0 0x4000>; 718 + interrupt-parent = <&aic>; 719 + interrupts = <AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH>, 720 + <AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH>, 721 + <AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH>, 722 + <AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH>; 723 + interrupt-names = "send-empty", "send-not-empty", 724 + "recv-empty", "recv-not-empty"; 725 + #mbox-cells = <0>; 726 + power-domains = <&ps_ans>; 727 + }; 728 + 729 + sart: sart@27bc50000 { 730 + compatible = "apple,t8112-sart", "apple,t6000-sart"; 731 + reg = <0x2 0x7bc50000 0x0 0x10000>; 732 + power-domains = <&ps_ans>; 733 + }; 734 + 735 + nvme@27bcc0000 { 736 + compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2"; 737 + reg = <0x2 0x7bcc0000 0x0 0x40000>, 738 + <0x2 0x77400000 0x0 0x4000>; 739 + reg-names = "nvme", "ans"; 740 + interrupt-parent = <&aic>; 741 + interrupts = <AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH>; 742 + mboxes = <&ans_mbox>; 743 + apple,sart = <&sart>; 744 + power-domains = <&ps_ans>, <&ps_apcie_st>; 745 + power-domain-names = "ans", "apcie0"; 746 + resets = <&ps_ans>; 747 + }; 748 + 749 + pcie0_dart: iommu@681008000 { 750 + compatible = "apple,t8110-dart"; 751 + reg = <0x6 0x81008000 0x0 0x4000>; 752 + #iommu-cells = <1>; 753 + interrupt-parent = <&aic>; 754 + interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>; 755 + power-domains = <&ps_apcie_gp>; 756 + }; 757 + 758 + pcie1_dart: iommu@682008000 { 759 + compatible = "apple,t8110-dart"; 760 + reg = <0x6 0x82008000 0x0 0x4000>; 761 + #iommu-cells = <1>; 762 + interrupt-parent = <&aic>; 763 + interrupts = <AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH>; 764 + power-domains = <&ps_apcie_gp>; 765 + status = "disabled"; 766 + }; 767 + 768 + pcie2_dart: iommu@683008000 { 769 + compatible = "apple,t8110-dart"; 770 + reg = <0x6 0x83008000 0x0 0x4000>; 771 + #iommu-cells = <1>; 772 + interrupt-parent = <&aic>; 773 + interrupts = <AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH>; 774 + power-domains = <&ps_apcie_gp>; 775 + status = "disabled"; 776 + }; 777 + 778 + pcie3_dart: iommu@684008000 { 779 + compatible = "apple,t8110-dart"; 780 + reg = <0x6 0x84008000 0x0 0x4000>; 781 + #iommu-cells = <1>; 782 + interrupt-parent = <&aic>; 783 + interrupts = <AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH>; 784 + power-domains = <&ps_apcie_gp>; 785 + status = "disabled"; 786 + }; 787 + 788 + pcie0: pcie@690000000 { 789 + compatible = "apple,t8112-pcie", "apple,pcie"; 790 + device_type = "pci"; 791 + 792 + reg = <0x6 0x90000000 0x0 0x1000000>, 793 + <0x6 0x80000000 0x0 0x100000>, 794 + <0x6 0x81000000 0x0 0x4000>, 795 + <0x6 0x82000000 0x0 0x4000>, 796 + <0x6 0x83000000 0x0 0x4000>, 797 + <0x6 0x84000000 0x0 0x4000>; 798 + reg-names = "config", "rc", "port0", "port1", "port2", "port3"; 799 + 800 + interrupt-parent = <&aic>; 801 + interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>, 802 + <AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>, 803 + <AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH>, 804 + <AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>; 805 + 806 + msi-controller; 807 + msi-parent = <&pcie0>; 808 + msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>; 809 + 810 + iommu-map = <0x100 &pcie0_dart 0 1>, 811 + <0x200 &pcie1_dart 1 1>, 812 + <0x300 &pcie2_dart 2 1>, 813 + <0x400 &pcie3_dart 3 1>; 814 + iommu-map-mask = <0xff00>; 815 + 816 + bus-range = <0 4>; 817 + #address-cells = <3>; 818 + #size-cells = <2>; 819 + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 820 + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 821 + 822 + power-domains = <&ps_apcie_gp>; 823 + pinctrl-0 = <&pcie_pins>; 824 + pinctrl-names = "default"; 825 + 826 + port00: pci@0,0 { 827 + device_type = "pci"; 828 + reg = <0x0 0x0 0x0 0x0 0x0>; 829 + reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>; 830 + 831 + #address-cells = <3>; 832 + #size-cells = <2>; 833 + ranges; 834 + 835 + interrupt-controller; 836 + #interrupt-cells = <1>; 837 + 838 + interrupt-map-mask = <0 0 0 7>; 839 + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 840 + <0 0 0 2 &port00 0 0 0 1>, 841 + <0 0 0 3 &port00 0 0 0 2>, 842 + <0 0 0 4 &port00 0 0 0 3>; 843 + }; 844 + 845 + port01: pci@1,0 { 846 + device_type = "pci"; 847 + reg = <0x800 0x0 0x0 0x0 0x0>; 848 + reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>; 849 + 850 + #address-cells = <3>; 851 + #size-cells = <2>; 852 + ranges; 853 + 854 + interrupt-controller; 855 + #interrupt-cells = <1>; 856 + 857 + interrupt-map-mask = <0 0 0 7>; 858 + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 859 + <0 0 0 2 &port01 0 0 0 1>, 860 + <0 0 0 3 &port01 0 0 0 2>, 861 + <0 0 0 4 &port01 0 0 0 3>; 862 + 863 + status = "disabled"; 864 + }; 865 + 866 + port02: pci@2,0 { 867 + device_type = "pci"; 868 + reg = <0x1000 0x0 0x0 0x0 0x0>; 869 + reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>; 870 + 871 + #address-cells = <3>; 872 + #size-cells = <2>; 873 + ranges; 874 + 875 + interrupt-controller; 876 + #interrupt-cells = <1>; 877 + 878 + interrupt-map-mask = <0 0 0 7>; 879 + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 880 + <0 0 0 2 &port02 0 0 0 1>, 881 + <0 0 0 3 &port02 0 0 0 2>, 882 + <0 0 0 4 &port02 0 0 0 3>; 883 + 884 + status = "disabled"; 885 + }; 886 + 887 + /* TODO: GPIO unknown */ 888 + port03: pci@3,0 { 889 + device_type = "pci"; 890 + reg = <0x1800 0x0 0x0 0x0 0x0>; 891 + //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 892 + 893 + #address-cells = <3>; 894 + #size-cells = <2>; 895 + ranges; 896 + 897 + interrupt-controller; 898 + #interrupt-cells = <1>; 899 + 900 + interrupt-map-mask = <0 0 0 7>; 901 + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, 902 + <0 0 0 2 &port03 0 0 0 1>, 903 + <0 0 0 3 &port03 0 0 0 2>, 904 + <0 0 0 4 &port03 0 0 0 3>; 905 + 906 + status = "disabled"; 907 + }; 908 + }; 909 + }; 910 + }; 911 + 912 + #include "t8112-pmgr.dtsi"