tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-next

Some additional fixes for 4.9:
- The rest of Christian's GTT rework which fixes a long standing bug
in the GPUVM code among other things
- Changes to the pci shutdown callbacks for certain hypervisors
- Fix hpd interrupt storms on eDP panels which have the hpd interrupt
enabled by the bios
- misc cleanups and bug fixes

* 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux: (33 commits)
drm/radeon: always apply pci shutdown callbacks
drm/amdgpu: always apply pci shutdown callbacks (v2)
drm/amdgpu: improve VM PTE trace points
drm/amdgpu: fix GART_DEBUGFS define
drm/amdgpu: free userptrs even if GTT isn't bound
drm/amd/amdgpu: Various cleanups for DCEv6
drm/amdgpu: fix BO move offsets
drm/amdgpu: fix amdgpu_move_blit on 32bit systems
drm/amdgpu: fix gtt_mgr bo's offset
drm/amdgpu: fix initializing the VM BO shadow
drm/amdgpu: fix initializing the VM last eviction counter
drm/amdgpu: cleanup VM shadow BO unreferencing
drm/amdgpu: allocate GTT space for shadow VM page tables
drm/amdgpu: rename all rbo variable to abo v2
drm/amdgpu: remove unused member from struct amdgpu_bo
drm/amdgpu: add a custom GTT memory manager v2
drm/amdgpu/dce6: disable hpd on local panels
drm/amdgpu/dce8: disable hpd on local panels
drm/amdgpu/dce11: disable hpd on local panels
drm/amdgpu/dce10: disable hpd on local panels
...

Dave Airlie 28a39654 b2d7e089

+700 -322
+2 -1
drivers/gpu/drm/amd/amdgpu/Makefile
··· 23 23 amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ 24 24 atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ 25 25 amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ 26 - amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o 26 + amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ 27 + amdgpu_gtt_mgr.o 27 28 28 29 # add asic specific block 29 30 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
+2 -4
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 445 445 #define AMDGPU_GEM_DOMAIN_MAX 0x3 446 446 447 447 struct amdgpu_bo { 448 - /* Protected by gem.mutex */ 449 - struct list_head list; 450 448 /* Protected by tbo.reserved */ 451 449 u32 prefered_domains; 452 450 u32 allowed_domains; ··· 702 704 u32 target_vblank; 703 705 uint64_t base; 704 706 struct drm_pending_vblank_event *event; 705 - struct amdgpu_bo *old_rbo; 707 + struct amdgpu_bo *old_abo; 706 708 struct fence *excl; 707 709 unsigned shared_count; 708 710 struct fence **shared; ··· 2415 2417 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2416 2418 u32 ip_instance, u32 ring, 2417 2419 struct amdgpu_ring **out_ring); 2418 - void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2420 + void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 2419 2421 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2420 2422 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 2421 2423 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
··· 648 648 if (!r && p->uf_entry.robj) { 649 649 struct amdgpu_bo *uf = p->uf_entry.robj; 650 650 651 - r = amdgpu_ttm_bind(uf->tbo.ttm, &uf->tbo.mem); 651 + r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem); 652 652 p->job->uf_addr += amdgpu_bo_gpu_offset(uf); 653 653 } 654 654 ··· 1192 1192 for (i = 0; i < parser->bo_list->num_entries; i++) { 1193 1193 struct amdgpu_bo *bo = parser->bo_list->array[i].robj; 1194 1194 1195 - r = amdgpu_ttm_bind(bo->tbo.ttm, &bo->tbo.mem); 1195 + r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 1196 1196 if (unlikely(r)) 1197 1197 return r; 1198 1198 }
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
··· 60 60 amd_sched_entity_fini(&adev->rings[j]->sched, 61 61 &ctx->rings[j].entity); 62 62 kfree(ctx->fences); 63 + ctx->fences = NULL; 63 64 return r; 64 65 } 65 66 return 0; ··· 78 77 for (j = 0; j < amdgpu_sched_jobs; ++j) 79 78 fence_put(ctx->rings[i].fences[j]); 80 79 kfree(ctx->fences); 80 + ctx->fences = NULL; 81 81 82 82 for (i = 0; i < adev->num_rings; i++) 83 83 amd_sched_entity_fini(&adev->rings[i]->sched,
+21 -21
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 123 123 int r; 124 124 125 125 /* unpin of the old buffer */ 126 - r = amdgpu_bo_reserve(work->old_rbo, false); 126 + r = amdgpu_bo_reserve(work->old_abo, false); 127 127 if (likely(r == 0)) { 128 - r = amdgpu_bo_unpin(work->old_rbo); 128 + r = amdgpu_bo_unpin(work->old_abo); 129 129 if (unlikely(r != 0)) { 130 130 DRM_ERROR("failed to unpin buffer after flip\n"); 131 131 } 132 - amdgpu_bo_unreserve(work->old_rbo); 132 + amdgpu_bo_unreserve(work->old_abo); 133 133 } else 134 134 DRM_ERROR("failed to reserve buffer after flip\n"); 135 135 136 - amdgpu_bo_unref(&work->old_rbo); 136 + amdgpu_bo_unref(&work->old_abo); 137 137 kfree(work->shared); 138 138 kfree(work); 139 139 } ··· 150 150 struct amdgpu_framebuffer *new_amdgpu_fb; 151 151 struct drm_gem_object *obj; 152 152 struct amdgpu_flip_work *work; 153 - struct amdgpu_bo *new_rbo; 153 + struct amdgpu_bo *new_abo; 154 154 unsigned long flags; 155 155 u64 tiling_flags; 156 156 u64 base; ··· 173 173 obj = old_amdgpu_fb->obj; 174 174 175 175 /* take a reference to the old object */ 176 - work->old_rbo = gem_to_amdgpu_bo(obj); 177 - amdgpu_bo_ref(work->old_rbo); 176 + work->old_abo = gem_to_amdgpu_bo(obj); 177 + amdgpu_bo_ref(work->old_abo); 178 178 179 179 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 180 180 obj = new_amdgpu_fb->obj; 181 - new_rbo = gem_to_amdgpu_bo(obj); 181 + new_abo = gem_to_amdgpu_bo(obj); 182 182 183 183 /* pin the new buffer */ 184 - r = amdgpu_bo_reserve(new_rbo, false); 184 + r = amdgpu_bo_reserve(new_abo, false); 185 185 if (unlikely(r != 0)) { 186 - DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 186 + DRM_ERROR("failed to reserve new abo buffer before flip\n"); 187 187 goto cleanup; 188 188 } 189 189 190 - r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 190 + r = amdgpu_bo_pin_restricted(new_abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 191 191 if (unlikely(r != 0)) { 192 192 r = -EINVAL; 193 - DRM_ERROR("failed to pin new rbo buffer before flip\n"); 193 + DRM_ERROR("failed to pin new abo buffer before flip\n"); 194 194 goto unreserve; 195 195 } 196 196 197 - r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, 197 + r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, 198 198 &work->shared_count, 199 199 &work->shared); 200 200 if (unlikely(r != 0)) { ··· 202 202 goto unpin; 203 203 } 204 204 205 - amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); 206 - amdgpu_bo_unreserve(new_rbo); 205 + amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 206 + amdgpu_bo_unreserve(new_abo); 207 207 208 208 work->base = base; 209 209 work->target_vblank = target - drm_crtc_vblank_count(crtc) + ··· 231 231 return 0; 232 232 233 233 pflip_cleanup: 234 - if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { 235 - DRM_ERROR("failed to reserve new rbo in error path\n"); 234 + if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 235 + DRM_ERROR("failed to reserve new abo in error path\n"); 236 236 goto cleanup; 237 237 } 238 238 unpin: 239 - if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { 240 - DRM_ERROR("failed to unpin new rbo in error path\n"); 239 + if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { 240 + DRM_ERROR("failed to unpin new abo in error path\n"); 241 241 } 242 242 unreserve: 243 - amdgpu_bo_unreserve(new_rbo); 243 + amdgpu_bo_unreserve(new_abo); 244 244 245 245 cleanup: 246 - amdgpu_bo_unref(&work->old_rbo); 246 + amdgpu_bo_unref(&work->old_abo); 247 247 fence_put(work->excl); 248 248 for (i = 0; i < work->shared_count; ++i) 249 249 fence_put(work->shared[i]);
+6 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 57 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 59 * - 3.7.0 - Add support for VCE clock list packet 60 + * - 3.8.0 - Add support raster config init in the kernel 60 61 */ 61 62 #define KMS_DRIVER_MAJOR 3 62 - #define KMS_DRIVER_MINOR 7 63 + #define KMS_DRIVER_MINOR 8 63 64 #define KMS_DRIVER_PATCHLEVEL 0 64 65 65 66 int amdgpu_vram_limit = 0; ··· 481 480 static void 482 481 amdgpu_pci_shutdown(struct pci_dev *pdev) 483 482 { 484 - struct drm_device *dev = pci_get_drvdata(pdev); 485 - struct amdgpu_device *adev = dev->dev_private; 486 - 487 483 /* if we are running in a VM, make sure the device 488 - * torn down properly on reboot/shutdown 484 + * torn down properly on reboot/shutdown. 485 + * unfortunately we can't detect certain 486 + * hypervisors so just do this all the time. 489 487 */ 490 - if (amdgpu_passthrough(adev)) 491 - amdgpu_pci_remove(pdev); 488 + amdgpu_pci_remove(pdev); 492 489 } 493 490 494 491 static int amdgpu_pmops_suspend(struct device *dev)
+22 -22
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
··· 115 115 116 116 static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) 117 117 { 118 - struct amdgpu_bo *rbo = gem_to_amdgpu_bo(gobj); 118 + struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 119 119 int ret; 120 120 121 - ret = amdgpu_bo_reserve(rbo, false); 121 + ret = amdgpu_bo_reserve(abo, false); 122 122 if (likely(ret == 0)) { 123 - amdgpu_bo_kunmap(rbo); 124 - amdgpu_bo_unpin(rbo); 125 - amdgpu_bo_unreserve(rbo); 123 + amdgpu_bo_kunmap(abo); 124 + amdgpu_bo_unpin(abo); 125 + amdgpu_bo_unreserve(abo); 126 126 } 127 127 drm_gem_object_unreference_unlocked(gobj); 128 128 } ··· 133 133 { 134 134 struct amdgpu_device *adev = rfbdev->adev; 135 135 struct drm_gem_object *gobj = NULL; 136 - struct amdgpu_bo *rbo = NULL; 136 + struct amdgpu_bo *abo = NULL; 137 137 bool fb_tiled = false; /* useful for testing */ 138 138 u32 tiling_flags = 0; 139 139 int ret; ··· 159 159 aligned_size); 160 160 return -ENOMEM; 161 161 } 162 - rbo = gem_to_amdgpu_bo(gobj); 162 + abo = gem_to_amdgpu_bo(gobj); 163 163 164 164 if (fb_tiled) 165 165 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); 166 166 167 - ret = amdgpu_bo_reserve(rbo, false); 167 + ret = amdgpu_bo_reserve(abo, false); 168 168 if (unlikely(ret != 0)) 169 169 goto out_unref; 170 170 171 171 if (tiling_flags) { 172 - ret = amdgpu_bo_set_tiling_flags(rbo, 172 + ret = amdgpu_bo_set_tiling_flags(abo, 173 173 tiling_flags); 174 174 if (ret) 175 175 dev_err(adev->dev, "FB failed to set tiling flags\n"); 176 176 } 177 177 178 178 179 - ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL); 179 + ret = amdgpu_bo_pin_restricted(abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL); 180 180 if (ret) { 181 - amdgpu_bo_unreserve(rbo); 181 + amdgpu_bo_unreserve(abo); 182 182 goto out_unref; 183 183 } 184 - ret = amdgpu_bo_kmap(rbo, NULL); 185 - amdgpu_bo_unreserve(rbo); 184 + ret = amdgpu_bo_kmap(abo, NULL); 185 + amdgpu_bo_unreserve(abo); 186 186 if (ret) { 187 187 goto out_unref; 188 188 } ··· 204 204 struct drm_framebuffer *fb = NULL; 205 205 struct drm_mode_fb_cmd2 mode_cmd; 206 206 struct drm_gem_object *gobj = NULL; 207 - struct amdgpu_bo *rbo = NULL; 207 + struct amdgpu_bo *abo = NULL; 208 208 int ret; 209 209 unsigned long tmp; 210 210 ··· 223 223 return ret; 224 224 } 225 225 226 - rbo = gem_to_amdgpu_bo(gobj); 226 + abo = gem_to_amdgpu_bo(gobj); 227 227 228 228 /* okay we have an object now allocate the framebuffer */ 229 229 info = drm_fb_helper_alloc_fbi(helper); ··· 246 246 /* setup helper */ 247 247 rfbdev->helper.fb = fb; 248 248 249 - memset_io(rbo->kptr, 0x0, amdgpu_bo_size(rbo)); 249 + memset_io(abo->kptr, 0x0, amdgpu_bo_size(abo)); 250 250 251 251 strcpy(info->fix.id, "amdgpudrmfb"); 252 252 ··· 255 255 info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; 256 256 info->fbops = &amdgpufb_ops; 257 257 258 - tmp = amdgpu_bo_gpu_offset(rbo) - adev->mc.vram_start; 258 + tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start; 259 259 info->fix.smem_start = adev->mc.aper_base + tmp; 260 - info->fix.smem_len = amdgpu_bo_size(rbo); 261 - info->screen_base = rbo->kptr; 262 - info->screen_size = amdgpu_bo_size(rbo); 260 + info->fix.smem_len = amdgpu_bo_size(abo); 261 + info->screen_base = abo->kptr; 262 + info->screen_size = amdgpu_bo_size(abo); 263 263 264 264 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); 265 265 ··· 276 276 277 277 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); 278 278 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base); 279 - DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(rbo)); 279 + DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); 280 280 DRM_INFO("fb depth is %d\n", fb->depth); 281 281 DRM_INFO(" pitch is %d\n", fb->pitches[0]); 282 282 ··· 286 286 out_destroy_fbi: 287 287 drm_fb_helper_release_fbi(helper); 288 288 out_unref: 289 - if (rbo) { 289 + if (abo) { 290 290 291 291 } 292 292 if (fb && ret) {
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 454 454 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 455 455 fence_put(ring->fence_drv.fences[j]); 456 456 kfree(ring->fence_drv.fences); 457 + ring->fence_drv.fences = NULL; 457 458 ring->fence_drv.initialized = false; 458 459 } 459 460 }
+4 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
··· 238 238 t = offset / AMDGPU_GPU_PAGE_SIZE; 239 239 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 240 240 for (i = 0; i < pages; i++, p++) { 241 - #ifdef CONFIG_AMDGPU_GART_DEBUGFS 241 + #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 242 242 adev->gart.pages[p] = NULL; 243 243 #endif 244 244 page_base = adev->dummy_page.addr; ··· 286 286 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 287 287 288 288 for (i = 0; i < pages; i++, p++) { 289 - #ifdef CONFIG_AMDGPU_GART_DEBUGFS 289 + #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 290 290 adev->gart.pages[p] = pagelist[i]; 291 291 #endif 292 292 if (adev->gart.ptr) { ··· 331 331 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 332 332 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 333 333 334 - #ifdef CONFIG_AMDGPU_GART_DEBUGFS 334 + #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 335 335 /* Allocate pages table */ 336 336 adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); 337 337 if (adev->gart.pages == NULL) { ··· 357 357 amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); 358 358 } 359 359 adev->gart.ready = false; 360 - #ifdef CONFIG_AMDGPU_GART_DEBUGFS 360 + #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 361 361 vfree(adev->gart.pages); 362 362 adev->gart.pages = NULL; 363 363 #endif
+11 -11
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
··· 118 118 */ 119 119 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) 120 120 { 121 - struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); 122 - struct amdgpu_device *adev = rbo->adev; 121 + struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 122 + struct amdgpu_device *adev = abo->adev; 123 123 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 124 124 struct amdgpu_vm *vm = &fpriv->vm; 125 125 struct amdgpu_bo_va *bo_va; 126 126 int r; 127 - r = amdgpu_bo_reserve(rbo, false); 127 + r = amdgpu_bo_reserve(abo, false); 128 128 if (r) 129 129 return r; 130 130 131 - bo_va = amdgpu_vm_bo_find(vm, rbo); 131 + bo_va = amdgpu_vm_bo_find(vm, abo); 132 132 if (!bo_va) { 133 - bo_va = amdgpu_vm_bo_add(adev, vm, rbo); 133 + bo_va = amdgpu_vm_bo_add(adev, vm, abo); 134 134 } else { 135 135 ++bo_va->ref_count; 136 136 } 137 - amdgpu_bo_unreserve(rbo); 137 + amdgpu_bo_unreserve(abo); 138 138 return 0; 139 139 } 140 140 ··· 528 528 goto error_unreserve; 529 529 530 530 if (operation == AMDGPU_VA_OP_MAP) 531 - r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); 531 + r = amdgpu_vm_bo_update(adev, bo_va, false); 532 532 533 533 error_unreserve: 534 534 ttm_eu_backoff_reservation(&ticket, &list); ··· 547 547 struct drm_gem_object *gobj; 548 548 struct amdgpu_device *adev = dev->dev_private; 549 549 struct amdgpu_fpriv *fpriv = filp->driver_priv; 550 - struct amdgpu_bo *rbo; 550 + struct amdgpu_bo *abo; 551 551 struct amdgpu_bo_va *bo_va; 552 552 struct ttm_validate_buffer tv, tv_pd; 553 553 struct ww_acquire_ctx ticket; ··· 587 587 gobj = drm_gem_object_lookup(filp, args->handle); 588 588 if (gobj == NULL) 589 589 return -ENOENT; 590 - rbo = gem_to_amdgpu_bo(gobj); 590 + abo = gem_to_amdgpu_bo(gobj); 591 591 INIT_LIST_HEAD(&list); 592 592 INIT_LIST_HEAD(&duplicates); 593 - tv.bo = &rbo->tbo; 593 + tv.bo = &abo->tbo; 594 594 tv.shared = true; 595 595 list_add(&tv.head, &list); 596 596 ··· 604 604 return r; 605 605 } 606 606 607 - bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 607 + bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 608 608 if (!bo_va) { 609 609 ttm_eu_backoff_reservation(&ticket, &list); 610 610 drm_gem_object_unreference_unlocked(gobj);
+239
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
··· 1 + /* 2 + * Copyright 2016 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * Authors: Christian König 23 + */ 24 + 25 + #include <drm/drmP.h> 26 + #include "amdgpu.h" 27 + 28 + struct amdgpu_gtt_mgr { 29 + struct drm_mm mm; 30 + spinlock_t lock; 31 + uint64_t available; 32 + }; 33 + 34 + /** 35 + * amdgpu_gtt_mgr_init - init GTT manager and DRM MM 36 + * 37 + * @man: TTM memory type manager 38 + * @p_size: maximum size of GTT 39 + * 40 + * Allocate and initialize the GTT manager. 41 + */ 42 + static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man, 43 + unsigned long p_size) 44 + { 45 + struct amdgpu_gtt_mgr *mgr; 46 + 47 + mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); 48 + if (!mgr) 49 + return -ENOMEM; 50 + 51 + drm_mm_init(&mgr->mm, 0, p_size); 52 + spin_lock_init(&mgr->lock); 53 + mgr->available = p_size; 54 + man->priv = mgr; 55 + return 0; 56 + } 57 + 58 + /** 59 + * amdgpu_gtt_mgr_fini - free and destroy GTT manager 60 + * 61 + * @man: TTM memory type manager 62 + * 63 + * Destroy and free the GTT manager, returns -EBUSY if ranges are still 64 + * allocated inside it. 65 + */ 66 + static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) 67 + { 68 + struct amdgpu_gtt_mgr *mgr = man->priv; 69 + 70 + spin_lock(&mgr->lock); 71 + if (!drm_mm_clean(&mgr->mm)) { 72 + spin_unlock(&mgr->lock); 73 + return -EBUSY; 74 + } 75 + 76 + drm_mm_takedown(&mgr->mm); 77 + spin_unlock(&mgr->lock); 78 + kfree(mgr); 79 + man->priv = NULL; 80 + return 0; 81 + } 82 + 83 + /** 84 + * amdgpu_gtt_mgr_alloc - allocate new ranges 85 + * 86 + * @man: TTM memory type manager 87 + * @tbo: TTM BO we need this range for 88 + * @place: placement flags and restrictions 89 + * @mem: the resulting mem object 90 + * 91 + * Allocate the address space for a node. 92 + */ 93 + int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, 94 + struct ttm_buffer_object *tbo, 95 + const struct ttm_place *place, 96 + struct ttm_mem_reg *mem) 97 + { 98 + struct amdgpu_gtt_mgr *mgr = man->priv; 99 + struct drm_mm_node *node = mem->mm_node; 100 + enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; 101 + enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; 102 + unsigned long fpfn, lpfn; 103 + int r; 104 + 105 + if (node->start != AMDGPU_BO_INVALID_OFFSET) 106 + return 0; 107 + 108 + if (place) 109 + fpfn = place->fpfn; 110 + else 111 + fpfn = 0; 112 + 113 + if (place && place->lpfn) 114 + lpfn = place->lpfn; 115 + else 116 + lpfn = man->size; 117 + 118 + if (place && place->flags & TTM_PL_FLAG_TOPDOWN) { 119 + sflags = DRM_MM_SEARCH_BELOW; 120 + aflags = DRM_MM_CREATE_TOP; 121 + } 122 + 123 + spin_lock(&mgr->lock); 124 + r = drm_mm_insert_node_in_range_generic(&mgr->mm, node, mem->num_pages, 125 + mem->page_alignment, 0, 126 + fpfn, lpfn, sflags, aflags); 127 + spin_unlock(&mgr->lock); 128 + 129 + if (!r) { 130 + mem->start = node->start; 131 + if (&tbo->mem == mem) 132 + tbo->offset = (tbo->mem.start << PAGE_SHIFT) + 133 + tbo->bdev->man[tbo->mem.mem_type].gpu_offset; 134 + } 135 + 136 + return r; 137 + } 138 + 139 + /** 140 + * amdgpu_gtt_mgr_new - allocate a new node 141 + * 142 + * @man: TTM memory type manager 143 + * @tbo: TTM BO we need this range for 144 + * @place: placement flags and restrictions 145 + * @mem: the resulting mem object 146 + * 147 + * Dummy, allocate the node but no space for it yet. 148 + */ 149 + static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, 150 + struct ttm_buffer_object *tbo, 151 + const struct ttm_place *place, 152 + struct ttm_mem_reg *mem) 153 + { 154 + struct amdgpu_gtt_mgr *mgr = man->priv; 155 + struct drm_mm_node *node; 156 + int r; 157 + 158 + spin_lock(&mgr->lock); 159 + if (mgr->available < mem->num_pages) { 160 + spin_unlock(&mgr->lock); 161 + return 0; 162 + } 163 + mgr->available -= mem->num_pages; 164 + spin_unlock(&mgr->lock); 165 + 166 + node = kzalloc(sizeof(*node), GFP_KERNEL); 167 + if (!node) 168 + return -ENOMEM; 169 + 170 + node->start = AMDGPU_BO_INVALID_OFFSET; 171 + mem->mm_node = node; 172 + 173 + if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) { 174 + r = amdgpu_gtt_mgr_alloc(man, tbo, place, mem); 175 + if (unlikely(r)) { 176 + kfree(node); 177 + mem->mm_node = NULL; 178 + } 179 + } else { 180 + mem->start = node->start; 181 + } 182 + 183 + return 0; 184 + } 185 + 186 + /** 187 + * amdgpu_gtt_mgr_del - free ranges 188 + * 189 + * @man: TTM memory type manager 190 + * @tbo: TTM BO we need this range for 191 + * @place: placement flags and restrictions 192 + * @mem: TTM memory object 193 + * 194 + * Free the allocated GTT again. 195 + */ 196 + static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man, 197 + struct ttm_mem_reg *mem) 198 + { 199 + struct amdgpu_gtt_mgr *mgr = man->priv; 200 + struct drm_mm_node *node = mem->mm_node; 201 + 202 + if (!node) 203 + return; 204 + 205 + spin_lock(&mgr->lock); 206 + if (node->start != AMDGPU_BO_INVALID_OFFSET) 207 + drm_mm_remove_node(node); 208 + mgr->available += mem->num_pages; 209 + spin_unlock(&mgr->lock); 210 + 211 + kfree(node); 212 + mem->mm_node = NULL; 213 + } 214 + 215 + /** 216 + * amdgpu_gtt_mgr_debug - dump VRAM table 217 + * 218 + * @man: TTM memory type manager 219 + * @prefix: text prefix 220 + * 221 + * Dump the table content using printk. 222 + */ 223 + static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man, 224 + const char *prefix) 225 + { 226 + struct amdgpu_gtt_mgr *mgr = man->priv; 227 + 228 + spin_lock(&mgr->lock); 229 + drm_mm_debug_table(&mgr->mm, prefix); 230 + spin_unlock(&mgr->lock); 231 + } 232 + 233 + const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func = { 234 + amdgpu_gtt_mgr_init, 235 + amdgpu_gtt_mgr_fini, 236 + amdgpu_gtt_mgr_new, 237 + amdgpu_gtt_mgr_del, 238 + amdgpu_gtt_mgr_debug 239 + };
+7 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c
··· 158 158 }; 159 159 160 160 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 161 - struct amdgpu_i2c_bus_rec *rec, 162 - const char *name) 161 + const struct amdgpu_i2c_bus_rec *rec, 162 + const char *name) 163 163 { 164 164 struct amdgpu_i2c_chan *i2c; 165 165 int ret; ··· 249 249 250 250 /* Add additional buses */ 251 251 void amdgpu_i2c_add(struct amdgpu_device *adev, 252 - struct amdgpu_i2c_bus_rec *rec, 253 - const char *name) 252 + const struct amdgpu_i2c_bus_rec *rec, 253 + const char *name) 254 254 { 255 255 struct drm_device *dev = adev->ddev; 256 256 int i; ··· 266 266 /* looks up bus based on id */ 267 267 struct amdgpu_i2c_chan * 268 268 amdgpu_i2c_lookup(struct amdgpu_device *adev, 269 - struct amdgpu_i2c_bus_rec *i2c_bus) 269 + const struct amdgpu_i2c_bus_rec *i2c_bus) 270 270 { 271 271 int i; 272 272 ··· 336 336 337 337 /* ddc router switching */ 338 338 void 339 - amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector) 339 + amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector) 340 340 { 341 341 u8 val; 342 342 ··· 365 365 366 366 /* clock/data router switching */ 367 367 void 368 - amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector) 368 + amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector) 369 369 { 370 370 u8 val; 371 371
+7 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h
··· 25 25 #define __AMDGPU_I2C_H__ 26 26 27 27 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 28 - struct amdgpu_i2c_bus_rec *rec, 29 - const char *name); 28 + const struct amdgpu_i2c_bus_rec *rec, 29 + const char *name); 30 30 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c); 31 31 void amdgpu_i2c_init(struct amdgpu_device *adev); 32 32 void amdgpu_i2c_fini(struct amdgpu_device *adev); 33 33 void amdgpu_i2c_add(struct amdgpu_device *adev, 34 - struct amdgpu_i2c_bus_rec *rec, 35 - const char *name); 34 + const struct amdgpu_i2c_bus_rec *rec, 35 + const char *name); 36 36 struct amdgpu_i2c_chan * 37 37 amdgpu_i2c_lookup(struct amdgpu_device *adev, 38 - struct amdgpu_i2c_bus_rec *i2c_bus); 38 + const struct amdgpu_i2c_bus_rec *i2c_bus); 39 39 void 40 - amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector); 40 + amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *connector); 41 41 void 42 - amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector); 42 + amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *connector); 43 43 44 44 #endif
+9 -10
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 203 203 placement->busy_placement = places; 204 204 } 205 205 206 - void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) 206 + void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 207 207 { 208 - amdgpu_ttm_placement_init(rbo->adev, &rbo->placement, 209 - rbo->placements, domain, rbo->flags); 208 + amdgpu_ttm_placement_init(abo->adev, &abo->placement, 209 + abo->placements, domain, abo->flags); 210 210 } 211 211 212 212 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, ··· 352 352 return r; 353 353 } 354 354 bo->adev = adev; 355 - INIT_LIST_HEAD(&bo->list); 356 355 INIT_LIST_HEAD(&bo->shadow_list); 357 356 INIT_LIST_HEAD(&bo->va); 358 357 bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | ··· 672 673 dev_err(bo->adev->dev, "%p pin failed\n", bo); 673 674 goto error; 674 675 } 675 - r = amdgpu_ttm_bind(bo->tbo.ttm, &bo->tbo.mem); 676 + r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 676 677 if (unlikely(r)) { 677 678 dev_err(bo->adev->dev, "%p bind failed\n", bo); 678 679 goto error; ··· 849 850 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 850 851 struct ttm_mem_reg *new_mem) 851 852 { 852 - struct amdgpu_bo *rbo; 853 + struct amdgpu_bo *abo; 853 854 struct ttm_mem_reg *old_mem = &bo->mem; 854 855 855 856 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 856 857 return; 857 858 858 - rbo = container_of(bo, struct amdgpu_bo, tbo); 859 - amdgpu_vm_bo_invalidate(rbo->adev, rbo); 859 + abo = container_of(bo, struct amdgpu_bo, tbo); 860 + amdgpu_vm_bo_invalidate(abo->adev, abo); 860 861 861 862 /* update statistics */ 862 863 if (!new_mem) 863 864 return; 864 865 865 866 /* move_notify is called before move happens */ 866 - amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem); 867 + amdgpu_update_memory_usage(abo->adev, &bo->mem, new_mem); 867 868 868 - trace_amdgpu_ttm_bo_move(rbo, new_mem->mem_type, old_mem->mem_type); 869 + trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 869 870 } 870 871 871 872 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
··· 264 264 (void **)&ring->ring); 265 265 266 266 amdgpu_debugfs_ring_fini(ring); 267 + 268 + ring->adev->rings[ring->idx] = NULL; 267 269 } 268 270 269 271 /*
+19 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
··· 247 247 TP_ARGS(mapping) 248 248 ); 249 249 250 - TRACE_EVENT(amdgpu_vm_set_page, 250 + TRACE_EVENT(amdgpu_vm_set_ptes, 251 251 TP_PROTO(uint64_t pe, uint64_t addr, unsigned count, 252 252 uint32_t incr, uint32_t flags), 253 253 TP_ARGS(pe, addr, count, incr, flags), ··· 269 269 TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u", 270 270 __entry->pe, __entry->addr, __entry->incr, 271 271 __entry->flags, __entry->count) 272 + ); 273 + 274 + TRACE_EVENT(amdgpu_vm_copy_ptes, 275 + TP_PROTO(uint64_t pe, uint64_t src, unsigned count), 276 + TP_ARGS(pe, src, count), 277 + TP_STRUCT__entry( 278 + __field(u64, pe) 279 + __field(u64, src) 280 + __field(u32, count) 281 + ), 282 + 283 + TP_fast_assign( 284 + __entry->pe = pe; 285 + __entry->src = src; 286 + __entry->count = count; 287 + ), 288 + TP_printk("pe=%010Lx, src=%010Lx, count=%u", 289 + __entry->pe, __entry->src, __entry->count) 272 290 ); 273 291 274 292 TRACE_EVENT(amdgpu_vm_flush,
+33 -25
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 160 160 man->default_caching = TTM_PL_FLAG_CACHED; 161 161 break; 162 162 case TTM_PL_TT: 163 - man->func = &ttm_bo_manager_func; 163 + man->func = &amdgpu_gtt_mgr_func; 164 164 man->gpu_offset = adev->mc.gtt_start; 165 165 man->available_caching = TTM_PL_MASK_CACHING; 166 166 man->default_caching = TTM_PL_FLAG_CACHED; ··· 195 195 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 196 196 struct ttm_placement *placement) 197 197 { 198 - struct amdgpu_bo *rbo; 198 + struct amdgpu_bo *abo; 199 199 static struct ttm_place placements = { 200 200 .fpfn = 0, 201 201 .lpfn = 0, ··· 210 210 placement->num_busy_placement = 1; 211 211 return; 212 212 } 213 - rbo = container_of(bo, struct amdgpu_bo, tbo); 213 + abo = container_of(bo, struct amdgpu_bo, tbo); 214 214 switch (bo->mem.mem_type) { 215 215 case TTM_PL_VRAM: 216 - if (rbo->adev->mman.buffer_funcs_ring->ready == false) { 217 - amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); 216 + if (abo->adev->mman.buffer_funcs_ring->ready == false) { 217 + amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 218 218 } else { 219 - amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT); 220 - for (i = 0; i < rbo->placement.num_placement; ++i) { 221 - if (!(rbo->placements[i].flags & 219 + amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 220 + for (i = 0; i < abo->placement.num_placement; ++i) { 221 + if (!(abo->placements[i].flags & 222 222 TTM_PL_FLAG_TT)) 223 223 continue; 224 224 225 - if (rbo->placements[i].lpfn) 225 + if (abo->placements[i].lpfn) 226 226 continue; 227 227 228 228 /* set an upper limit to force directly 229 229 * allocating address space for the BO. 230 230 */ 231 - rbo->placements[i].lpfn = 232 - rbo->adev->mc.gtt_size >> PAGE_SHIFT; 231 + abo->placements[i].lpfn = 232 + abo->adev->mc.gtt_size >> PAGE_SHIFT; 233 233 } 234 234 } 235 235 break; 236 236 case TTM_PL_TT: 237 237 default: 238 - amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); 238 + amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 239 239 } 240 - *placement = rbo->placement; 240 + *placement = abo->placement; 241 241 } 242 242 243 243 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 244 244 { 245 - struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); 245 + struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo); 246 246 247 247 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 248 248 return -EPERM; 249 - return drm_vma_node_verify_access(&rbo->gem_base.vma_node, 249 + return drm_vma_node_verify_access(&abo->gem_base.vma_node, 250 250 filp->private_data); 251 251 } 252 252 ··· 273 273 274 274 adev = amdgpu_get_adev(bo->bdev); 275 275 ring = adev->mman.buffer_funcs_ring; 276 - old_start = (u64)old_mem->start << PAGE_SHIFT; 277 - new_start = (u64)new_mem->start << PAGE_SHIFT; 278 276 279 277 switch (old_mem->mem_type) { 280 278 case TTM_PL_TT: 281 - r = amdgpu_ttm_bind(bo->ttm, old_mem); 279 + r = amdgpu_ttm_bind(bo, old_mem); 282 280 if (r) 283 281 return r; 284 282 285 283 case TTM_PL_VRAM: 284 + old_start = (u64)old_mem->start << PAGE_SHIFT; 286 285 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset; 287 286 break; 288 287 default: ··· 290 291 } 291 292 switch (new_mem->mem_type) { 292 293 case TTM_PL_TT: 293 - r = amdgpu_ttm_bind(bo->ttm, new_mem); 294 + r = amdgpu_ttm_bind(bo, new_mem); 294 295 if (r) 295 296 return r; 296 297 297 298 case TTM_PL_VRAM: 299 + new_start = (u64)new_mem->start << PAGE_SHIFT; 298 300 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset; 299 301 break; 300 302 default: ··· 676 676 return r; 677 677 } 678 678 } 679 - gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 680 679 if (!ttm->num_pages) { 681 680 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 682 681 ttm->num_pages, bo_mem, ttm); ··· 696 697 return gtt && !list_empty(&gtt->list); 697 698 } 698 699 699 - int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) 700 + int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) 700 701 { 701 - struct amdgpu_ttm_tt *gtt = (void *)ttm; 702 + struct ttm_tt *ttm = bo->ttm; 703 + struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 702 704 uint32_t flags; 703 705 int r; 704 706 705 707 if (!ttm || amdgpu_ttm_is_bound(ttm)) 706 708 return 0; 707 709 710 + r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo, 711 + NULL, bo_mem); 712 + if (r) { 713 + DRM_ERROR("Failed to allocate GTT address space (%d)\n", r); 714 + return r; 715 + } 716 + 708 717 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 718 + gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 709 719 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, 710 720 ttm->pages, gtt->ttm.dma_address, flags); 711 721 ··· 758 750 { 759 751 struct amdgpu_ttm_tt *gtt = (void *)ttm; 760 752 753 + if (gtt->userptr) 754 + amdgpu_ttm_tt_unpin_userptr(ttm); 755 + 761 756 if (!amdgpu_ttm_is_bound(ttm)) 762 757 return 0; 763 758 764 759 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 765 760 if (gtt->adev->gart.ready) 766 761 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); 767 - 768 - if (gtt->userptr) 769 - amdgpu_ttm_tt_unpin_userptr(ttm); 770 762 771 763 spin_lock(&gtt->adev->gtt_list_lock); 772 764 list_del_init(&gtt->list);
+8 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
··· 65 65 struct amdgpu_mman_lru guard; 66 66 }; 67 67 68 + extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func; 69 + 70 + int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, 71 + struct ttm_buffer_object *tbo, 72 + const struct ttm_place *place, 73 + struct ttm_mem_reg *mem); 74 + 68 75 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 69 76 uint64_t src_offset, 70 77 uint64_t dst_offset, ··· 85 78 86 79 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 87 80 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm); 88 - int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); 81 + int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem); 89 82 90 83 #endif
+4 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
··· 351 351 } 352 352 } 353 353 354 - static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) 354 + static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 355 355 { 356 356 int i; 357 - for (i = 0; i < rbo->placement.num_placement; ++i) { 358 - rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; 359 - rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 357 + for (i = 0; i < abo->placement.num_placement; ++i) { 358 + abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 359 + abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 360 360 } 361 361 } 362 362
+9 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
··· 210 210 */ 211 211 int amdgpu_vce_sw_fini(struct amdgpu_device *adev) 212 212 { 213 + unsigned i; 214 + 213 215 if (adev->vce.vcpu_bo == NULL) 214 216 return 0; 215 217 ··· 219 217 220 218 amdgpu_bo_unref(&adev->vce.vcpu_bo); 221 219 222 - amdgpu_ring_fini(&adev->vce.ring[0]); 223 - amdgpu_ring_fini(&adev->vce.ring[1]); 220 + for (i = 0; i < adev->vce.num_rings; i++) 221 + amdgpu_ring_fini(&adev->vce.ring[i]); 224 222 225 223 release_firmware(adev->vce.fw); 226 224 mutex_destroy(&adev->vce.idle_mutex); ··· 305 303 { 306 304 struct amdgpu_device *adev = 307 305 container_of(work, struct amdgpu_device, vce.idle_work.work); 306 + unsigned i, count = 0; 308 307 309 - if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) && 310 - (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) { 308 + for (i = 0; i < adev->vce.num_rings; i++) 309 + count += amdgpu_fence_count_emitted(&adev->vce.ring[i]); 310 + 311 + if (count == 0) { 311 312 if (adev->pm.dpm_enabled) { 312 313 amdgpu_dpm_enable_vce(adev, false); 313 314 } else {
+55 -12
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 487 487 unsigned count, uint32_t incr, 488 488 uint32_t flags) 489 489 { 490 - trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); 490 + trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); 491 491 492 492 if (count < 3) { 493 493 amdgpu_vm_write_pte(params->adev, params->ib, pe, ··· 516 516 unsigned count, uint32_t incr, 517 517 uint32_t flags) 518 518 { 519 - trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); 519 + uint64_t src = (params->src + (addr >> 12) * 8); 520 520 521 - amdgpu_vm_copy_pte(params->adev, params->ib, pe, 522 - (params->src + (addr >> 12) * 8), count); 521 + 522 + trace_amdgpu_vm_copy_ptes(pe, src, count); 523 + 524 + amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); 523 525 } 524 526 525 527 /** ··· 551 549 return r; 552 550 553 551 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 552 + if (r) 553 + goto error; 554 + 555 + r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); 554 556 if (r) 555 557 goto error; 556 558 ··· 631 625 632 626 if (!pd) 633 627 return 0; 628 + 629 + r = amdgpu_ttm_bind(&pd->tbo, &pd->tbo.mem); 630 + if (r) 631 + return r; 632 + 634 633 pd_addr = amdgpu_bo_gpu_offset(pd); 635 634 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); 636 635 ··· 660 649 661 650 if (bo == NULL) 662 651 continue; 652 + 653 + if (bo->shadow) { 654 + struct amdgpu_bo *shadow = bo->shadow; 655 + 656 + r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); 657 + if (r) 658 + return r; 659 + } 663 660 664 661 pt = amdgpu_bo_gpu_offset(bo); 665 662 if (!shadow) { ··· 1019 1000 AMDGPU_GPU_PAGE_SIZE); 1020 1001 pte[i] |= flags; 1021 1002 } 1003 + addr = 0; 1022 1004 } 1023 1005 1024 1006 r = amdgpu_sync_fence(adev, &job->sync, exclusive); ··· 1432 1412 1433 1413 r = amdgpu_vm_clear_bo(adev, vm, pt); 1434 1414 if (r) { 1415 + amdgpu_bo_unref(&pt->shadow); 1435 1416 amdgpu_bo_unref(&pt); 1436 1417 goto error_free; 1418 + } 1419 + 1420 + if (pt->shadow) { 1421 + r = amdgpu_vm_clear_bo(adev, vm, pt->shadow); 1422 + if (r) { 1423 + amdgpu_bo_unref(&pt->shadow); 1424 + amdgpu_bo_unref(&pt); 1425 + goto error_free; 1426 + } 1437 1427 } 1438 1428 1439 1429 entry->robj = pt; ··· 1640 1610 goto error_free_page_directory; 1641 1611 1642 1612 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); 1643 - amdgpu_bo_unreserve(vm->page_directory); 1644 1613 if (r) 1645 - goto error_free_page_directory; 1614 + goto error_unreserve; 1615 + 1616 + if (vm->page_directory->shadow) { 1617 + r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory->shadow); 1618 + if (r) 1619 + goto error_unreserve; 1620 + } 1621 + 1646 1622 vm->last_eviction_counter = atomic64_read(&adev->num_evictions); 1623 + amdgpu_bo_unreserve(vm->page_directory); 1647 1624 1648 1625 return 0; 1649 1626 1627 + error_unreserve: 1628 + amdgpu_bo_unreserve(vm->page_directory); 1629 + 1650 1630 error_free_page_directory: 1631 + amdgpu_bo_unref(&vm->page_directory->shadow); 1651 1632 amdgpu_bo_unref(&vm->page_directory); 1652 1633 vm->page_directory = NULL; 1653 1634 ··· 1701 1660 } 1702 1661 1703 1662 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { 1704 - if (vm->page_tables[i].entry.robj && 1705 - vm->page_tables[i].entry.robj->shadow) 1706 - amdgpu_bo_unref(&vm->page_tables[i].entry.robj->shadow); 1707 - amdgpu_bo_unref(&vm->page_tables[i].entry.robj); 1663 + struct amdgpu_bo *pt = vm->page_tables[i].entry.robj; 1664 + 1665 + if (!pt) 1666 + continue; 1667 + 1668 + amdgpu_bo_unref(&pt->shadow); 1669 + amdgpu_bo_unref(&pt); 1708 1670 } 1709 1671 drm_free_large(vm->page_tables); 1710 1672 1711 - if (vm->page_directory->shadow) 1712 - amdgpu_bo_unref(&vm->page_directory->shadow); 1673 + amdgpu_bo_unref(&vm->page_directory->shadow); 1713 1674 amdgpu_bo_unref(&vm->page_directory); 1714 1675 fence_put(vm->page_directory_fence); 1715 1676 }
+31 -28
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 427 427 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 428 428 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 429 429 430 - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 431 - connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 432 - /* don't try to enable hpd on eDP or LVDS avoid breaking the 433 - * aux dp channel on imac and help (but not completely fix) 434 - * https://bugzilla.redhat.com/show_bug.cgi?id=726143 435 - * also avoid interrupt storms during dpms. 436 - */ 437 - continue; 438 - } 439 - 440 430 switch (amdgpu_connector->hpd.hpd) { 441 431 case AMDGPU_HPD_1: 442 432 idx = 0; ··· 447 457 idx = 5; 448 458 break; 449 459 default: 460 + continue; 461 + } 462 + 463 + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 464 + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 465 + /* don't try to enable hpd on eDP or LVDS avoid breaking the 466 + * aux dp channel on imac and help (but not completely fix) 467 + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 468 + * also avoid interrupt storms during dpms. 469 + */ 470 + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 471 + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 472 + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 450 473 continue; 451 474 } 452 475 ··· 2107 2104 struct amdgpu_framebuffer *amdgpu_fb; 2108 2105 struct drm_framebuffer *target_fb; 2109 2106 struct drm_gem_object *obj; 2110 - struct amdgpu_bo *rbo; 2107 + struct amdgpu_bo *abo; 2111 2108 uint64_t fb_location, tiling_flags; 2112 2109 uint32_t fb_format, fb_pitch_pixels; 2113 2110 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); ··· 2135 2132 * just update base pointers 2136 2133 */ 2137 2134 obj = amdgpu_fb->obj; 2138 - rbo = gem_to_amdgpu_bo(obj); 2139 - r = amdgpu_bo_reserve(rbo, false); 2135 + abo = gem_to_amdgpu_bo(obj); 2136 + r = amdgpu_bo_reserve(abo, false); 2140 2137 if (unlikely(r != 0)) 2141 2138 return r; 2142 2139 2143 2140 if (atomic) { 2144 - fb_location = amdgpu_bo_gpu_offset(rbo); 2141 + fb_location = amdgpu_bo_gpu_offset(abo); 2145 2142 } else { 2146 - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2143 + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2147 2144 if (unlikely(r != 0)) { 2148 - amdgpu_bo_unreserve(rbo); 2145 + amdgpu_bo_unreserve(abo); 2149 2146 return -EINVAL; 2150 2147 } 2151 2148 } 2152 2149 2153 - amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2154 - amdgpu_bo_unreserve(rbo); 2150 + amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 2151 + amdgpu_bo_unreserve(abo); 2155 2152 2156 2153 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2157 2154 ··· 2326 2323 2327 2324 if (!atomic && fb && fb != crtc->primary->fb) { 2328 2325 amdgpu_fb = to_amdgpu_framebuffer(fb); 2329 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2330 - r = amdgpu_bo_reserve(rbo, false); 2326 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2327 + r = amdgpu_bo_reserve(abo, false); 2331 2328 if (unlikely(r != 0)) 2332 2329 return r; 2333 - amdgpu_bo_unpin(rbo); 2334 - amdgpu_bo_unreserve(rbo); 2330 + amdgpu_bo_unpin(abo); 2331 + amdgpu_bo_unreserve(abo); 2335 2332 } 2336 2333 2337 2334 /* Bytes per pixel may have changed */ ··· 2811 2808 if (crtc->primary->fb) { 2812 2809 int r; 2813 2810 struct amdgpu_framebuffer *amdgpu_fb; 2814 - struct amdgpu_bo *rbo; 2811 + struct amdgpu_bo *abo; 2815 2812 2816 2813 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2817 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2818 - r = amdgpu_bo_reserve(rbo, false); 2814 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2815 + r = amdgpu_bo_reserve(abo, false); 2819 2816 if (unlikely(r)) 2820 - DRM_ERROR("failed to reserve rbo before unpin\n"); 2817 + DRM_ERROR("failed to reserve abo before unpin\n"); 2821 2818 else { 2822 - amdgpu_bo_unpin(rbo); 2823 - amdgpu_bo_unreserve(rbo); 2819 + amdgpu_bo_unpin(abo); 2820 + amdgpu_bo_unreserve(abo); 2824 2821 } 2825 2822 } 2826 2823 /* disable the GRPH */
+31 -28
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 443 443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 444 444 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 445 445 446 - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 447 - connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 448 - /* don't try to enable hpd on eDP or LVDS avoid breaking the 449 - * aux dp channel on imac and help (but not completely fix) 450 - * https://bugzilla.redhat.com/show_bug.cgi?id=726143 451 - * also avoid interrupt storms during dpms. 452 - */ 453 - continue; 454 - } 455 - 456 446 switch (amdgpu_connector->hpd.hpd) { 457 447 case AMDGPU_HPD_1: 458 448 idx = 0; ··· 463 473 idx = 5; 464 474 break; 465 475 default: 476 + continue; 477 + } 478 + 479 + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 480 + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 481 + /* don't try to enable hpd on eDP or LVDS avoid breaking the 482 + * aux dp channel on imac and help (but not completely fix) 483 + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 484 + * also avoid interrupt storms during dpms. 485 + */ 486 + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 487 + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 488 + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 466 489 continue; 467 490 } 468 491 ··· 2088 2085 struct amdgpu_framebuffer *amdgpu_fb; 2089 2086 struct drm_framebuffer *target_fb; 2090 2087 struct drm_gem_object *obj; 2091 - struct amdgpu_bo *rbo; 2088 + struct amdgpu_bo *abo; 2092 2089 uint64_t fb_location, tiling_flags; 2093 2090 uint32_t fb_format, fb_pitch_pixels; 2094 2091 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); ··· 2116 2113 * just update base pointers 2117 2114 */ 2118 2115 obj = amdgpu_fb->obj; 2119 - rbo = gem_to_amdgpu_bo(obj); 2120 - r = amdgpu_bo_reserve(rbo, false); 2116 + abo = gem_to_amdgpu_bo(obj); 2117 + r = amdgpu_bo_reserve(abo, false); 2121 2118 if (unlikely(r != 0)) 2122 2119 return r; 2123 2120 2124 2121 if (atomic) { 2125 - fb_location = amdgpu_bo_gpu_offset(rbo); 2122 + fb_location = amdgpu_bo_gpu_offset(abo); 2126 2123 } else { 2127 - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2124 + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2128 2125 if (unlikely(r != 0)) { 2129 - amdgpu_bo_unreserve(rbo); 2126 + amdgpu_bo_unreserve(abo); 2130 2127 return -EINVAL; 2131 2128 } 2132 2129 } 2133 2130 2134 - amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2135 - amdgpu_bo_unreserve(rbo); 2131 + amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 2132 + amdgpu_bo_unreserve(abo); 2136 2133 2137 2134 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2138 2135 ··· 2307 2304 2308 2305 if (!atomic && fb && fb != crtc->primary->fb) { 2309 2306 amdgpu_fb = to_amdgpu_framebuffer(fb); 2310 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2311 - r = amdgpu_bo_reserve(rbo, false); 2307 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2308 + r = amdgpu_bo_reserve(abo, false); 2312 2309 if (unlikely(r != 0)) 2313 2310 return r; 2314 - amdgpu_bo_unpin(rbo); 2315 - amdgpu_bo_unreserve(rbo); 2311 + amdgpu_bo_unpin(abo); 2312 + amdgpu_bo_unreserve(abo); 2316 2313 } 2317 2314 2318 2315 /* Bytes per pixel may have changed */ ··· 2827 2824 if (crtc->primary->fb) { 2828 2825 int r; 2829 2826 struct amdgpu_framebuffer *amdgpu_fb; 2830 - struct amdgpu_bo *rbo; 2827 + struct amdgpu_bo *abo; 2831 2828 2832 2829 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2833 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2834 - r = amdgpu_bo_reserve(rbo, false); 2830 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2831 + r = amdgpu_bo_reserve(abo, false); 2835 2832 if (unlikely(r)) 2836 - DRM_ERROR("failed to reserve rbo before unpin\n"); 2833 + DRM_ERROR("failed to reserve abo before unpin\n"); 2837 2834 else { 2838 - amdgpu_bo_unpin(rbo); 2839 - amdgpu_bo_unreserve(rbo); 2835 + amdgpu_bo_unpin(abo); 2836 + amdgpu_bo_unreserve(abo); 2840 2837 } 2841 2838 } 2842 2839 /* disable the GRPH */
+67 -63
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 375 375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 376 376 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 377 377 378 - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 379 - connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 380 - /* don't try to enable hpd on eDP or LVDS avoid breaking the 381 - * aux dp channel on imac and help (but not completely fix) 382 - * https://bugzilla.redhat.com/show_bug.cgi?id=726143 383 - * also avoid interrupt storms during dpms. 384 - */ 385 - continue; 386 - } 387 378 switch (amdgpu_connector->hpd.hpd) { 388 379 case AMDGPU_HPD_1: 389 380 WREG32(DC_HPD1_CONTROL, tmp); ··· 397 406 default: 398 407 break; 399 408 } 409 + 410 + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 411 + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 412 + /* don't try to enable hpd on eDP or LVDS avoid breaking the 413 + * aux dp channel on imac and help (but not completely fix) 414 + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 415 + * also avoid interrupt storms during dpms. 416 + */ 417 + u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 418 + 419 + switch (amdgpu_connector->hpd.hpd) { 420 + case AMDGPU_HPD_1: 421 + dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL; 422 + break; 423 + case AMDGPU_HPD_2: 424 + dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL; 425 + break; 426 + case AMDGPU_HPD_3: 427 + dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL; 428 + break; 429 + case AMDGPU_HPD_4: 430 + dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL; 431 + break; 432 + case AMDGPU_HPD_5: 433 + dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL; 434 + break; 435 + case AMDGPU_HPD_6: 436 + dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL; 437 + break; 438 + default: 439 + continue; 440 + } 441 + 442 + dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 443 + dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 444 + WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 445 + continue; 446 + } 447 + 400 448 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 401 449 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 402 450 } ··· 1505 1475 u32 vga_control; 1506 1476 1507 1477 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1508 - if (enable) 1509 - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1510 - else 1511 - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1478 + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1512 1479 } 1513 1480 1514 1481 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) ··· 1514 1487 struct drm_device *dev = crtc->dev; 1515 1488 struct amdgpu_device *adev = dev->dev_private; 1516 1489 1517 - if (enable) 1518 - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1519 - else 1520 - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1490 + WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1521 1491 } 1522 1492 1523 1493 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, ··· 1527 1503 struct amdgpu_framebuffer *amdgpu_fb; 1528 1504 struct drm_framebuffer *target_fb; 1529 1505 struct drm_gem_object *obj; 1530 - struct amdgpu_bo *rbo; 1506 + struct amdgpu_bo *abo; 1531 1507 uint64_t fb_location, tiling_flags; 1532 1508 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1533 1509 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); ··· 1544 1520 if (atomic) { 1545 1521 amdgpu_fb = to_amdgpu_framebuffer(fb); 1546 1522 target_fb = fb; 1547 - } 1548 - else { 1523 + } else { 1549 1524 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 1550 1525 target_fb = crtc->primary->fb; 1551 1526 } ··· 1553 1530 * just update base pointers 1554 1531 */ 1555 1532 obj = amdgpu_fb->obj; 1556 - rbo = gem_to_amdgpu_bo(obj); 1557 - r = amdgpu_bo_reserve(rbo, false); 1533 + abo = gem_to_amdgpu_bo(obj); 1534 + r = amdgpu_bo_reserve(abo, false); 1558 1535 if (unlikely(r != 0)) 1559 1536 return r; 1560 1537 1561 - if (atomic) 1562 - fb_location = amdgpu_bo_gpu_offset(rbo); 1563 - else { 1564 - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1538 + if (atomic) { 1539 + fb_location = amdgpu_bo_gpu_offset(abo); 1540 + } else { 1541 + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1565 1542 if (unlikely(r != 0)) { 1566 - amdgpu_bo_unreserve(rbo); 1543 + amdgpu_bo_unreserve(abo); 1567 1544 return -EINVAL; 1568 1545 } 1569 1546 } 1570 1547 1571 - amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 1572 - amdgpu_bo_unreserve(rbo); 1548 + amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1549 + amdgpu_bo_unreserve(abo); 1573 1550 1574 1551 switch (target_fb->pixel_format) { 1575 1552 case DRM_FORMAT_C8: ··· 1656 1633 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1657 1634 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1658 1635 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1659 - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) 1636 + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1660 1637 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1638 + } 1661 1639 1662 1640 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1663 1641 fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config); ··· 1722 1698 1723 1699 if (!atomic && fb && fb != crtc->primary->fb) { 1724 1700 amdgpu_fb = to_amdgpu_framebuffer(fb); 1725 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 1726 - r = amdgpu_bo_reserve(rbo, false); 1701 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 1702 + r = amdgpu_bo_reserve(abo, false); 1727 1703 if (unlikely(r != 0)) 1728 1704 return r; 1729 - amdgpu_bo_unpin(rbo); 1730 - amdgpu_bo_unreserve(rbo); 1705 + amdgpu_bo_unpin(abo); 1706 + amdgpu_bo_unreserve(abo); 1731 1707 } 1732 1708 1733 1709 /* Bytes per pixel may have changed */ ··· 1822 1798 1823 1799 switch (amdgpu_encoder->encoder_id) { 1824 1800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1825 - if (dig->linkb) 1826 - return 1; 1827 - else 1828 - return 0; 1829 - break; 1801 + return dig->linkb ? 1 : 0; 1830 1802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1831 - if (dig->linkb) 1832 - return 3; 1833 - else 1834 - return 2; 1835 - break; 1803 + return dig->linkb ? 3 : 2; 1836 1804 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1837 - if (dig->linkb) 1838 - return 5; 1839 - else 1840 - return 4; 1841 - break; 1805 + return dig->linkb ? 5 : 4; 1842 1806 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1843 1807 return 6; 1844 - break; 1845 1808 default: 1846 1809 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 1847 1810 return 0; ··· 2063 2052 amdgpu_crtc->cursor_y); 2064 2053 2065 2054 dce_v6_0_show_cursor(crtc); 2066 - 2067 2055 dce_v6_0_lock_cursor(crtc, false); 2068 2056 } 2069 2057 } ··· 2161 2151 if (crtc->primary->fb) { 2162 2152 int r; 2163 2153 struct amdgpu_framebuffer *amdgpu_fb; 2164 - struct amdgpu_bo *rbo; 2154 + struct amdgpu_bo *abo; 2165 2155 2166 2156 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2167 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2168 - r = amdgpu_bo_reserve(rbo, false); 2157 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2158 + r = amdgpu_bo_reserve(abo, false); 2169 2159 if (unlikely(r)) 2170 - DRM_ERROR("failed to reserve rbo before unpin\n"); 2160 + DRM_ERROR("failed to reserve abo before unpin\n"); 2171 2161 else { 2172 - amdgpu_bo_unpin(rbo); 2173 - amdgpu_bo_unreserve(rbo); 2162 + amdgpu_bo_unpin(abo); 2163 + amdgpu_bo_unreserve(abo); 2174 2164 } 2175 2165 } 2176 2166 /* disable the GRPH */ ··· 2385 2375 adev->mode_info.mode_config_initialized = true; 2386 2376 2387 2377 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2388 - 2389 2378 adev->ddev->mode_config.async_page_flip = true; 2390 - 2391 2379 adev->ddev->mode_config.max_width = 16384; 2392 2380 adev->ddev->mode_config.max_height = 16384; 2393 - 2394 2381 adev->ddev->mode_config.preferred_depth = 24; 2395 2382 adev->ddev->mode_config.prefer_shadow = 1; 2396 - 2397 2383 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2398 2384 2399 2385 r = amdgpu_modeset_create_props(adev); ··· 2435 2429 drm_kms_helper_poll_fini(adev->ddev); 2436 2430 2437 2431 dce_v6_0_audio_fini(adev); 2438 - 2439 2432 dce_v6_0_afmt_fini(adev); 2440 2433 2441 2434 drm_mode_config_cleanup(adev->ddev); ··· 3062 3057 } 3063 3058 3064 3059 amdgpu_encoder->enc_priv = NULL; 3065 - 3066 3060 amdgpu_encoder->encoder_enum = encoder_enum; 3067 3061 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3068 3062 amdgpu_encoder->devices = supported_device;
+57 -27
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 397 397 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 398 398 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 399 399 400 - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 401 - connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 402 - /* don't try to enable hpd on eDP or LVDS avoid breaking the 403 - * aux dp channel on imac and help (but not completely fix) 404 - * https://bugzilla.redhat.com/show_bug.cgi?id=726143 405 - * also avoid interrupt storms during dpms. 406 - */ 407 - continue; 408 - } 409 400 switch (amdgpu_connector->hpd.hpd) { 410 401 case AMDGPU_HPD_1: 411 402 WREG32(mmDC_HPD1_CONTROL, tmp); ··· 419 428 default: 420 429 break; 421 430 } 431 + 432 + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 433 + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 434 + /* don't try to enable hpd on eDP or LVDS avoid breaking the 435 + * aux dp channel on imac and help (but not completely fix) 436 + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 437 + * also avoid interrupt storms during dpms. 438 + */ 439 + u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 440 + 441 + switch (amdgpu_connector->hpd.hpd) { 442 + case AMDGPU_HPD_1: 443 + dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; 444 + break; 445 + case AMDGPU_HPD_2: 446 + dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; 447 + break; 448 + case AMDGPU_HPD_3: 449 + dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; 450 + break; 451 + case AMDGPU_HPD_4: 452 + dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; 453 + break; 454 + case AMDGPU_HPD_5: 455 + dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; 456 + break; 457 + case AMDGPU_HPD_6: 458 + dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; 459 + break; 460 + default: 461 + continue; 462 + } 463 + 464 + dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 465 + dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 466 + WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 467 + continue; 468 + } 469 + 422 470 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 423 471 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 424 472 } ··· 2022 1992 struct amdgpu_framebuffer *amdgpu_fb; 2023 1993 struct drm_framebuffer *target_fb; 2024 1994 struct drm_gem_object *obj; 2025 - struct amdgpu_bo *rbo; 1995 + struct amdgpu_bo *abo; 2026 1996 uint64_t fb_location, tiling_flags; 2027 1997 uint32_t fb_format, fb_pitch_pixels; 2028 1998 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); ··· 2050 2020 * just update base pointers 2051 2021 */ 2052 2022 obj = amdgpu_fb->obj; 2053 - rbo = gem_to_amdgpu_bo(obj); 2054 - r = amdgpu_bo_reserve(rbo, false); 2023 + abo = gem_to_amdgpu_bo(obj); 2024 + r = amdgpu_bo_reserve(abo, false); 2055 2025 if (unlikely(r != 0)) 2056 2026 return r; 2057 2027 2058 2028 if (atomic) { 2059 - fb_location = amdgpu_bo_gpu_offset(rbo); 2029 + fb_location = amdgpu_bo_gpu_offset(abo); 2060 2030 } else { 2061 - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2031 + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2062 2032 if (unlikely(r != 0)) { 2063 - amdgpu_bo_unreserve(rbo); 2033 + amdgpu_bo_unreserve(abo); 2064 2034 return -EINVAL; 2065 2035 } 2066 2036 } 2067 2037 2068 - amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2069 - amdgpu_bo_unreserve(rbo); 2038 + amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 2039 + amdgpu_bo_unreserve(abo); 2070 2040 2071 2041 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2072 2042 ··· 2222 2192 2223 2193 if (!atomic && fb && fb != crtc->primary->fb) { 2224 2194 amdgpu_fb = to_amdgpu_framebuffer(fb); 2225 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2226 - r = amdgpu_bo_reserve(rbo, false); 2195 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2196 + r = amdgpu_bo_reserve(abo, false); 2227 2197 if (unlikely(r != 0)) 2228 2198 return r; 2229 - amdgpu_bo_unpin(rbo); 2230 - amdgpu_bo_unreserve(rbo); 2199 + amdgpu_bo_unpin(abo); 2200 + amdgpu_bo_unreserve(abo); 2231 2201 } 2232 2202 2233 2203 /* Bytes per pixel may have changed */ ··· 2699 2669 if (crtc->primary->fb) { 2700 2670 int r; 2701 2671 struct amdgpu_framebuffer *amdgpu_fb; 2702 - struct amdgpu_bo *rbo; 2672 + struct amdgpu_bo *abo; 2703 2673 2704 2674 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2705 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2706 - r = amdgpu_bo_reserve(rbo, false); 2675 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2676 + r = amdgpu_bo_reserve(abo, false); 2707 2677 if (unlikely(r)) 2708 - DRM_ERROR("failed to reserve rbo before unpin\n"); 2678 + DRM_ERROR("failed to reserve abo before unpin\n"); 2709 2679 else { 2710 - amdgpu_bo_unpin(rbo); 2711 - amdgpu_bo_unreserve(rbo); 2680 + amdgpu_bo_unpin(abo); 2681 + amdgpu_bo_unreserve(abo); 2712 2682 } 2713 2683 } 2714 2684 /* disable the GRPH */
+6 -6
drivers/gpu/drm/amd/amdgpu/dce_virtual.c
··· 229 229 if (crtc->primary->fb) { 230 230 int r; 231 231 struct amdgpu_framebuffer *amdgpu_fb; 232 - struct amdgpu_bo *rbo; 232 + struct amdgpu_bo *abo; 233 233 234 234 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 235 - rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 236 - r = amdgpu_bo_reserve(rbo, false); 235 + abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 236 + r = amdgpu_bo_reserve(abo, false); 237 237 if (unlikely(r)) 238 - DRM_ERROR("failed to reserve rbo before unpin\n"); 238 + DRM_ERROR("failed to reserve abo before unpin\n"); 239 239 else { 240 - amdgpu_bo_unpin(rbo); 241 - amdgpu_bo_unreserve(rbo); 240 + amdgpu_bo_unpin(abo); 241 + amdgpu_bo_unreserve(abo); 242 242 } 243 243 } 244 244
+14 -1
drivers/gpu/drm/amd/amdgpu/si_dpm.c
··· 3023 3023 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 3024 3024 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 3025 3025 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 3026 + { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, 3026 3027 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 3027 3028 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 3028 3029 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 3030 + { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 3031 + { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 3029 3032 { 0, 0, 0, 0 }, 3030 3033 }; 3031 3034 ··· 3488 3485 break; 3489 3486 } 3490 3487 ++p; 3488 + } 3489 + /* limit mclk on all R7 370 parts for stability */ 3490 + if (adev->pdev->device == 0x6811 && 3491 + adev->pdev->revision == 0x81) 3492 + max_mclk = 120000; 3493 + /* limit sclk/mclk on Jet parts for stability */ 3494 + if (adev->pdev->device == 0x6665 && 3495 + adev->pdev->revision == 0xc3) { 3496 + max_sclk = 75000; 3497 + max_mclk = 80000; 3491 3498 } 3492 3499 3493 3500 if (rps->vce_active) { ··· 4593 4580 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4594 4581 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4595 4582 4596 - table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4583 + table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4597 4584 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4598 4585 4599 4586 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
+1
drivers/gpu/drm/amd/amdgpu/sislands_smc.h
··· 194 194 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 195 195 #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 196 196 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 197 + #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3 197 198 #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 198 199 199 200 struct SISLANDS_SMC_VOLTAGEMASKTABLE
+2 -1
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
··· 716 716 int i; 717 717 718 718 if ((adev->asic_type == CHIP_POLARIS10) || 719 - (adev->asic_type == CHIP_TONGA)) 719 + (adev->asic_type == CHIP_TONGA) || 720 + (adev->asic_type == CHIP_FIJI)) 720 721 vce_v3_0_set_bypass_mode(adev, enable); 721 722 722 723 if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
+1 -1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
··· 4278 4278 return 0; 4279 4279 } 4280 4280 4281 - static struct pp_hwmgr_func smu7_hwmgr_funcs = { 4281 + static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 4282 4282 .backend_init = &smu7_hwmgr_backend_init, 4283 4283 .backend_fini = &phm_hwmgr_backend_fini, 4284 4284 .asic_setup = &smu7_setup_asic_task,
+6 -6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
··· 31 31 32 32 static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; 33 33 34 - static struct gpu_pt_config_reg GCCACConfig_Polaris10[] = { 34 + static const struct gpu_pt_config_reg GCCACConfig_Polaris10[] = { 35 35 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 36 36 * Offset Mask Shift Value Type 37 37 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ··· 62 62 { 0xFFFFFFFF } 63 63 }; 64 64 65 - static struct gpu_pt_config_reg GCCACConfig_Polaris11[] = { 65 + static const struct gpu_pt_config_reg GCCACConfig_Polaris11[] = { 66 66 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 67 67 * Offset Mask Shift Value Type 68 68 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ··· 93 93 { 0xFFFFFFFF } 94 94 }; 95 95 96 - static struct gpu_pt_config_reg DIDTConfig_Polaris10[] = { 96 + static const struct gpu_pt_config_reg DIDTConfig_Polaris10[] = { 97 97 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 98 98 * Offset Mask Shift Value Type 99 99 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ··· 235 235 { 0xFFFFFFFF } 236 236 }; 237 237 238 - static struct gpu_pt_config_reg DIDTConfig_Polaris11[] = { 238 + static const struct gpu_pt_config_reg DIDTConfig_Polaris11[] = { 239 239 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 240 240 * Offset Mask Shift Value Type 241 241 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ··· 427 427 } 428 428 429 429 static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr, 430 - struct gpu_pt_config_reg *cac_config_regs) 430 + const struct gpu_pt_config_reg *cac_config_regs) 431 431 { 432 - struct gpu_pt_config_reg *config_regs = cac_config_regs; 432 + const struct gpu_pt_config_reg *config_regs = cac_config_regs; 433 433 uint32_t cache = 0; 434 434 uint32_t data = 0; 435 435
+5 -5
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
··· 63 63 #define DEVICE_ID_VI_ICELAND_M_6902 0x6902 64 64 #define DEVICE_ID_VI_ICELAND_M_6903 0x6903 65 65 66 - static struct iceland_pt_defaults defaults_iceland = { 66 + static const struct iceland_pt_defaults defaults_iceland = { 67 67 /* 68 68 * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, 69 69 * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT ··· 74 74 }; 75 75 76 76 /* 35W - XT, XTL */ 77 - static struct iceland_pt_defaults defaults_icelandxt = { 77 + static const struct iceland_pt_defaults defaults_icelandxt = { 78 78 /* 79 79 * sviLoadLIneEn, SviLoadLineVddC, 80 80 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, ··· 87 87 }; 88 88 89 89 /* 25W - PRO, LE */ 90 - static struct iceland_pt_defaults defaults_icelandpro = { 90 + static const struct iceland_pt_defaults defaults_icelandpro = { 91 91 /* 92 92 * sviLoadLIneEn, SviLoadLineVddC, 93 93 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, ··· 1740 1740 { 1741 1741 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1742 1742 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1743 - struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 1743 + const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 1744 1744 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 1745 1745 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; 1746 1746 struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; 1747 - uint16_t *def1, *def2; 1747 + const uint16_t *def1, *def2; 1748 1748 int i, j, k; 1749 1749 1750 1750
+1 -1
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
··· 62 62 struct SMU71_Discrete_DpmTable smc_state_table; 63 63 struct SMU71_Discrete_PmFuses power_tune_table; 64 64 struct SMU71_Discrete_Ulv ulv_setting; 65 - struct iceland_pt_defaults *power_tune_defaults; 65 + const struct iceland_pt_defaults *power_tune_defaults; 66 66 SMU71_Discrete_MCRegisters mc_regs; 67 67 struct iceland_mc_reg_table mc_reg_table; 68 68 uint32_t activity_target[SMU71_MAX_LEVELS_GRAPHICS];
+6 -7
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
··· 58 58 #define VDDC_VDDCI_DELTA 200 59 59 60 60 61 - static struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { 61 + static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { 62 62 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, 63 63 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT 64 64 */ ··· 1815 1815 { 1816 1816 struct tonga_smumgr *smu_data = 1817 1817 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1818 - struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1818 + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1819 1819 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 1820 1820 struct phm_ppt_v1_information *table_info = 1821 1821 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1822 1822 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; 1823 1823 int i, j, k; 1824 - uint16_t *pdef1; 1825 - uint16_t *pdef2; 1824 + const uint16_t *pdef1, *pdef2; 1826 1825 1827 1826 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( 1828 1827 (uint16_t)(cac_dtp_table->usTDP * 256)); ··· 1862 1863 { 1863 1864 struct tonga_smumgr *smu_data = 1864 1865 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1865 - struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1866 + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1866 1867 1867 1868 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; 1868 1869 smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC; ··· 1877 1878 uint16_t tdc_limit; 1878 1879 struct tonga_smumgr *smu_data = 1879 1880 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1880 - struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1881 + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1881 1882 struct phm_ppt_v1_information *table_info = 1882 1883 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1883 1884 ··· 1898 1899 { 1899 1900 struct tonga_smumgr *smu_data = 1900 1901 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1901 - struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1902 + const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1902 1903 uint32_t temp; 1903 1904 1904 1905 if (smu7_read_smc_sram_dword(hwmgr->smumgr,
+1 -1
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
··· 48 48 struct SMU72_Discrete_DpmTable smc_state_table; 49 49 struct SMU72_Discrete_Ulv ulv_setting; 50 50 struct SMU72_Discrete_PmFuses power_tune_table; 51 - struct tonga_pt_defaults *power_tune_defaults; 51 + const struct tonga_pt_defaults *power_tune_defaults; 52 52 SMU72_Discrete_MCRegisters mc_regs; 53 53 struct tonga_mc_reg_table mc_reg_table; 54 54
+4 -3
drivers/gpu/drm/radeon/radeon_drv.c
··· 365 365 radeon_pci_shutdown(struct pci_dev *pdev) 366 366 { 367 367 /* if we are running in a VM, make sure the device 368 - * torn down properly on reboot/shutdown 368 + * torn down properly on reboot/shutdown. 369 + * unfortunately we can't detect certain 370 + * hypervisors so just do this all the time. 369 371 */ 370 - if (radeon_device_is_virtual()) 371 - radeon_pci_remove(pdev); 372 + radeon_pci_remove(pdev); 372 373 } 373 374 374 375 static int radeon_pmops_suspend(struct device *dev)
+1 -1
drivers/gpu/drm/radeon/si_dpm.c
··· 4106 4106 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4107 4107 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4108 4108 4109 - table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4109 + table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4110 4110 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4111 4111 4112 4112 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
+1
drivers/gpu/drm/radeon/sislands_smc.h
··· 194 194 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 195 195 #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 196 196 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 197 + #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3 197 198 #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 198 199 199 200 struct SISLANDS_SMC_VOLTAGEMASKTABLE