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[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Eric Miao
and committed by
Russell King
283afa06
e7f3c600
+39
-44
+1
-43
arch/arm/mach-pxa/include/mach/pxa-regs.h
+1
-43
arch/arm/mach-pxa/include/mach/pxa-regs.h
···
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/*
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* I2C registers
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* I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
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*/
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#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
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#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
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#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
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#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
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#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
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#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
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#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
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#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
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#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
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#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
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#define ICR_START (1 << 0) /* start bit */
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#define ICR_STOP (1 << 1) /* stop bit */
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#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
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#define ICR_TB (1 << 3) /* transfer byte bit */
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#define ICR_MA (1 << 4) /* master abort */
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#define ICR_SCLE (1 << 5) /* master clock enable */
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#define ICR_IUE (1 << 6) /* unit enable */
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#define ICR_GCD (1 << 7) /* general call disable */
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#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
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#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
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#define ICR_BEIE (1 << 10) /* enable bus error ints */
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#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
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#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
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#define ICR_SADIE (1 << 13) /* slave address detected int enable */
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#define ICR_UR (1 << 14) /* unit reset */
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#define ICR_FM (1 << 15) /* fast mode */
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#define ISR_RWM (1 << 0) /* read/write mode */
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#define ISR_ACKNAK (1 << 1) /* ack/nak status */
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#define ISR_UB (1 << 2) /* unit busy */
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#define ISR_IBB (1 << 3) /* bus busy */
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#define ISR_SSD (1 << 4) /* slave stop detected */
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#define ISR_ALD (1 << 5) /* arbitration loss detected */
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#define ISR_ITE (1 << 6) /* tx buffer empty */
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#define ISR_IRF (1 << 7) /* rx buffer full */
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#define ISR_GCAD (1 << 8) /* general call address detected */
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#define ISR_SAD (1 << 9) /* slave address detected */
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#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
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/*
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* Serial Audio Controller
+38
-1
drivers/i2c/busses/i2c-pxa.c
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-1
drivers/i2c/busses/i2c-pxa.c
···
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <mach/i2c.h>
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#include <mach/pxa-regs.h>
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/*
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* I2C registers and bit definitions
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*/
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#define IBMR (0x00)
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#define IDBR (0x08)
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#define ICR (0x10)
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#define ISR (0x18)
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#define ISAR (0x20)
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#define ICR_START (1 << 0) /* start bit */
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#define ICR_STOP (1 << 1) /* stop bit */
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#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
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#define ICR_TB (1 << 3) /* transfer byte bit */
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#define ICR_MA (1 << 4) /* master abort */
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#define ICR_SCLE (1 << 5) /* master clock enable */
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#define ICR_IUE (1 << 6) /* unit enable */
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#define ICR_GCD (1 << 7) /* general call disable */
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#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
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#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
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#define ICR_BEIE (1 << 10) /* enable bus error ints */
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#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
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#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
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#define ICR_SADIE (1 << 13) /* slave address detected int enable */
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#define ICR_UR (1 << 14) /* unit reset */
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#define ICR_FM (1 << 15) /* fast mode */
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#define ISR_RWM (1 << 0) /* read/write mode */
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#define ISR_ACKNAK (1 << 1) /* ack/nak status */
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#define ISR_UB (1 << 2) /* unit busy */
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#define ISR_IBB (1 << 3) /* bus busy */
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#define ISR_SSD (1 << 4) /* slave stop detected */
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#define ISR_ALD (1 << 5) /* arbitration loss detected */
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#define ISR_ITE (1 << 6) /* tx buffer empty */
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#define ISR_IRF (1 << 7) /* rx buffer full */
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#define ISR_GCAD (1 << 8) /* general call address detected */
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#define ISR_SAD (1 << 9) /* slave address detected */
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#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
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struct pxa_i2c {
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spinlock_t lock;