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Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
From Sascha Hauer:
ARM i.MX SoC updates for next
Mostly clock related updates, most notably the conversion of
i.MX31 to a DT based lookup.
* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: clk-imx35: Fix build warnings with W=1
ARM: imx27: add a clock gate to activate SPLL clock
ARM: mx31: Replace clk_register_clkdev with clock DT lookup
ARM: clk-imx31: Add dummy clock
ARM: Let CONFIG_MACH_IMX31_DT be built by default
Signed-off-by: Olof Johansson <olof@lixom.net>
+129
-23
+91
Documentation/devicetree/bindings/clock/imx31-clock.txt
+91
Documentation/devicetree/bindings/clock/imx31-clock.txt
···
1
+
* Clock bindings for Freescale i.MX31
2
+
3
+
Required properties:
4
+
- compatible: Should be "fsl,imx31-ccm"
5
+
- reg: Address and length of the register set
6
+
- interrupts: Should contain CCM interrupt
7
+
- #clock-cells: Should be <1>
8
+
9
+
The clock consumer should specify the desired clock by having the clock
10
+
ID in its "clocks" phandle cell. The following is a full list of i.MX31
11
+
clocks and IDs.
12
+
13
+
Clock ID
14
+
-----------------------
15
+
dummy 0
16
+
ckih 1
17
+
ckil 2
18
+
mpll 3
19
+
spll 4
20
+
upll 5
21
+
mcu_main 6
22
+
hsp 7
23
+
ahb 8
24
+
nfc 9
25
+
ipg 10
26
+
per_div 11
27
+
per 12
28
+
csi_sel 13
29
+
fir_sel 14
30
+
csi_div 15
31
+
usb_div_pre 16
32
+
usb_div_post 17
33
+
fir_div_pre 18
34
+
fir_div_post 19
35
+
sdhc1_gate 20
36
+
sdhc2_gate 21
37
+
gpt_gate 22
38
+
epit1_gate 23
39
+
epit2_gate 24
40
+
iim_gate 25
41
+
ata_gate 26
42
+
sdma_gate 27
43
+
cspi3_gate 28
44
+
rng_gate 29
45
+
uart1_gate 30
46
+
uart2_gate 31
47
+
ssi1_gate 32
48
+
i2c1_gate 33
49
+
i2c2_gate 34
50
+
i2c3_gate 35
51
+
hantro_gate 36
52
+
mstick1_gate 37
53
+
mstick2_gate 38
54
+
csi_gate 39
55
+
rtc_gate 40
56
+
wdog_gate 41
57
+
pwm_gate 42
58
+
sim_gate 43
59
+
ect_gate 44
60
+
usb_gate 45
61
+
kpp_gate 46
62
+
ipu_gate 47
63
+
uart3_gate 48
64
+
uart4_gate 49
65
+
uart5_gate 50
66
+
owire_gate 51
67
+
ssi2_gate 52
68
+
cspi1_gate 53
69
+
cspi2_gate 54
70
+
gacc_gate 55
71
+
emi_gate 56
72
+
rtic_gate 57
73
+
firi_gate 58
74
+
75
+
Examples:
76
+
77
+
clks: ccm@53f80000{
78
+
compatible = "fsl,imx31-ccm";
79
+
reg = <0x53f80000 0x4000>;
80
+
interrupts = <0 31 0x04 0 53 0x04>;
81
+
#clock-cells = <1>;
82
+
};
83
+
84
+
uart1: serial@43f90000 {
85
+
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
86
+
reg = <0x43f90000 0x4000>;
87
+
interrupts = <45>;
88
+
clocks = <&clks 10>, <&clks 30>;
89
+
clock-names = "ipg", "per";
90
+
status = "disabled";
91
+
};
+17
arch/arm/boot/dts/imx31.dtsi
+17
arch/arm/boot/dts/imx31.dtsi
···
45
45
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
46
46
reg = <0x43f90000 0x4000>;
47
47
interrupts = <45>;
48
+
clocks = <&clks 10>, <&clks 30>;
49
+
clock-names = "ipg", "per";
48
50
status = "disabled";
49
51
};
50
52
···
54
52
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
55
53
reg = <0x43f94000 0x4000>;
56
54
interrupts = <32>;
55
+
clocks = <&clks 10>, <&clks 31>;
56
+
clock-names = "ipg", "per";
57
57
status = "disabled";
58
58
};
59
59
60
60
uart4: serial@43fb0000 {
61
61
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
62
62
reg = <0x43fb0000 0x4000>;
63
+
clocks = <&clks 10>, <&clks 49>;
64
+
clock-names = "ipg", "per";
63
65
interrupts = <46>;
64
66
status = "disabled";
65
67
};
···
72
66
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
73
67
reg = <0x43fb4000 0x4000>;
74
68
interrupts = <47>;
69
+
clocks = <&clks 10>, <&clks 50>;
70
+
clock-names = "ipg", "per";
75
71
status = "disabled";
76
72
};
77
73
};
···
89
81
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
90
82
reg = <0x5000c000 0x4000>;
91
83
interrupts = <18>;
84
+
clocks = <&clks 10>, <&clks 48>;
85
+
clock-names = "ipg", "per";
92
86
status = "disabled";
87
+
};
88
+
89
+
clks: ccm@53f80000{
90
+
compatible = "fsl,imx31-ccm";
91
+
reg = <0x53f80000 0x4000>;
92
+
interrupts = <0 31 0x04 0 53 0x04>;
93
+
#clock-cells = <1>;
93
94
};
94
95
};
95
96
};
+1
arch/arm/configs/imx_v6_v7_defconfig
+1
arch/arm/configs/imx_v6_v7_defconfig
+4
-3
arch/arm/mach-imx/clk-imx27.c
+4
-3
arch/arm/mach-imx/clk-imx27.c
···
62
62
"32k", "usb_div", "dptc",
63
63
};
64
64
65
-
static const char *ssi_sel_clks[] = { "spll", "mpll", };
65
+
static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
66
66
67
67
enum mx27_clks {
68
68
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
···
82
82
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
83
83
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
84
84
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
85
-
mpll_sel, clk_max
85
+
mpll_sel, spll_gate, clk_max
86
86
};
87
87
88
88
static struct clk *clk[clk_max];
···
104
104
ARRAY_SIZE(mpll_sel_clks));
105
105
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
106
106
clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
107
+
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
107
108
clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
108
109
109
110
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
···
122
121
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
123
122
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
124
123
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
125
-
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
124
+
clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
126
125
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
127
126
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
128
127
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+13
-2
arch/arm/mach-imx/clk-imx31.c
+13
-2
arch/arm/mach-imx/clk-imx31.c
···
34
34
static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
35
35
36
36
enum mx31_clks {
37
-
ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
38
-
per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
37
+
dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
38
+
per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
39
39
fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
40
40
iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
41
41
uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
···
46
46
};
47
47
48
48
static struct clk *clk[clk_max];
49
+
static struct clk_onecell_data clk_data;
49
50
50
51
int __init mx31_clocks_init(unsigned long fref)
51
52
{
52
53
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
53
54
int i;
55
+
struct device_node *np;
54
56
57
+
clk[dummy] = imx_clk_fixed("dummy", 0);
55
58
clk[ckih] = imx_clk_fixed("ckih", fref);
56
59
clk[ckil] = imx_clk_fixed("ckil", 32768);
57
60
clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
···
118
115
if (IS_ERR(clk[i]))
119
116
pr_err("imx31 clk %d: register failed with %ld\n",
120
117
i, PTR_ERR(clk[i]));
118
+
119
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
120
+
121
+
if (np) {
122
+
clk_data.clks = clk;
123
+
clk_data.clk_num = ARRAY_SIZE(clk);
124
+
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
125
+
}
121
126
122
127
clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
123
128
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+2
-2
arch/arm/mach-imx/clk-imx35.c
+2
-2
arch/arm/mach-imx/clk-imx35.c
···
67
67
68
68
static struct clk *clk[clk_max];
69
69
70
-
int __init mx35_clocks_init()
70
+
int __init mx35_clocks_init(void)
71
71
{
72
72
void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
73
73
u32 pdr0, consumer_sel, hsp_sel;
74
74
struct arm_ahb_div *aad;
75
75
unsigned char *hsp_div;
76
-
int i;
76
+
u32 i;
77
77
78
78
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
79
79
consumer_sel = (pdr0 >> 16) & 0xf;
+1
-16
arch/arm/mach-imx/imx31-dt.c
+1
-16
arch/arm/mach-imx/imx31-dt.c
···
18
18
#include "common.h"
19
19
#include "mx31.h"
20
20
21
-
static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
22
-
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
23
-
"imx21-uart.0", NULL),
24
-
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
25
-
"imx21-uart.1", NULL),
26
-
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
27
-
"imx21-uart.2", NULL),
28
-
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
29
-
"imx21-uart.3", NULL),
30
-
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
31
-
"imx21-uart.4", NULL),
32
-
{ /* sentinel */ }
33
-
};
34
-
35
21
static void __init imx31_dt_init(void)
36
22
{
37
-
of_platform_populate(NULL, of_default_bus_match_table,
38
-
imx31_auxdata_lookup, NULL);
23
+
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
39
24
}
40
25
41
26
static const char *imx31_dt_board_compat[] __initdata = {