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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull shmobile clk updates from Geert Uytterhoeven:
- Fix a bug in the div6 clock driver that was exposed by CAN
support on R-Car H3,
- Add more module clocks for R-Car H3.
* 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: shmobile: r8a7795: Add CAN FD peripheral clock
clk: shmobile: r8a7795: Add CANFD clock
clk: shmobile: r8a7795: Add CAN peripheral clock
clk: shmobile: div6: Fix .recalc_rate() using a stale divisor
clk: shmobile: r8a7795: Add LVDS module clock
clk: shmobile: r8a7795: Add FCP clocks
+21
-2
+1
-2
drivers/clk/shmobile/clk-div6.c
+1
-2
drivers/clk/shmobile/clk-div6.c
···
82
82
unsigned long parent_rate)
83
83
{
84
84
struct div6_clock *clock = to_div6_clock(hw);
85
-
unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
86
85
87
-
return parent_rate / div;
86
+
return parent_rate / clock->div;
88
87
}
89
88
90
89
static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
+20
drivers/clk/shmobile/r8a7795-cpg-mssr.c
+20
drivers/clk/shmobile/r8a7795-cpg-mssr.c
···
112
112
113
113
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
114
114
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
115
+
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
115
116
};
116
117
117
118
static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
···
148
147
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
149
148
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
150
149
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
150
+
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
151
+
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
152
+
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
153
+
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1),
154
+
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1),
155
+
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1),
156
+
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1),
157
+
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1),
158
+
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1),
159
+
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1),
160
+
DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1),
161
+
DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1),
162
+
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1),
163
+
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1),
164
+
DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1),
151
165
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
152
166
DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
153
167
DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
···
180
164
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
181
165
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
182
166
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
167
+
DEF_MOD("lvds", 727, R8A7795_CLK_S2D1),
183
168
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
184
169
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
185
170
DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
···
193
176
DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
194
177
DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
195
178
DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
179
+
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
180
+
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
181
+
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
196
182
DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
197
183
DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
198
184
DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),