tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-for-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"A collection of fixes this week:

- A set of clock fixes for shmobile platforms
- A fix for tegra that moves serial port labels to be per board.
We're choosing to merge this for 3.18 because the labels will start
being parsed in 3.19, and without this change serial port numbers
that used to be stable since the dawn of time will change numbers.
- A few other DT tweaks for Tegra.
- A fix for multi_v7_defconfig that makes it stop spewing cpufreq
errors on Arndale (Exynos)"

* tag 'armsoc-for-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: multi_v7_defconfig: fix failure setting CPU voltage by enabling dependent I2C controller
ARM: tegra: roth: Fix SD card VDD_IO regulator
ARM: tegra: Remove eMMC vmmc property for roth/tn7
ARM: dts: tegra: move serial aliases to per-board
ARM: tegra: Add serial port labels to Tegra124 DT
ARM: shmobile: kzm9g legacy: Set i2c clks_per_count to 2
ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock
ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree
ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock
ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module
ARM: shmobile: r8a7790: Fix SD3CKCR address
ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller

Linus Torvalds 27946315 9f2e0f63

options
unified split
Changed files
+80 -38
arch
arm
boot
dts
r8a7740.dtsi
r8a7790.dtsi
sun6i-a31.dtsi
tegra114-dalmore.dts
tegra114-roth.dts
tegra114-tn7.dts
tegra114.dtsi
tegra124-jetson-tk1.dts
tegra124-nyan-big.dts
tegra124-venice2.dts
tegra124.dtsi
tegra20-harmony.dts
tegra20-iris-512.dts
tegra20-medcom-wide.dts
tegra20-paz00.dts
tegra20-seaboard.dts
tegra20-tamonten.dtsi
tegra20-trimslice.dts
tegra20-ventana.dts
tegra20-whistler.dts
tegra20.dtsi
tegra30-apalis-eval.dts
tegra30-beaver.dts
tegra30-cardhu.dtsi
tegra30-colibri-eval-v3.dts
tegra30.dtsi
configs
multi_v7_defconfig
mach-shmobile
clock-r8a7740.c
clock-r8a7790.c
setup-sh73a0.c
+1 -1
arch/arm/boot/dts/r8a7740.dtsi
··· 433 433 clocks = <&cpg_clocks R8A7740_CLK_S>, 434 434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, 435 435 <&cpg_clocks R8A7740_CLK_B>, 436 - <&sub_clk>, <&sub_clk>, 436 + <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, 437 437 <&cpg_clocks R8A7740_CLK_B>; 438 438 #clock-cells = <1>; 439 439 renesas,clock-indices = <
+2 -2
arch/arm/boot/dts/r8a7790.dtsi
··· 666 666 #clock-cells = <0>; 667 667 clock-output-names = "sd2"; 668 668 }; 669 - sd3_clk: sd3_clk@e615007c { 669 + sd3_clk: sd3_clk@e615026c { 670 670 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 671 - reg = <0 0xe615007c 0 4>; 671 + reg = <0 0xe615026c 0 4>; 672 672 clocks = <&pll1_div2_clk>; 673 673 #clock-cells = <0>; 674 674 clock-output-names = "sd3";
+4
arch/arm/boot/dts/sun6i-a31.dtsi
··· 361 361 clocks = <&ahb1_gates 6>; 362 362 resets = <&ahb1_rst 6>; 363 363 #dma-cells = <1>; 364 + 365 + /* DMA controller requires AHB1 clocked from PLL6 */ 366 + assigned-clocks = <&ahb1_mux>; 367 + assigned-clock-parents = <&pll6>; 364 368 }; 365 369 366 370 mmc0: mmc@01c0f000 {
+1
arch/arm/boot/dts/tegra114-dalmore.dts
··· 15 15 aliases { 16 16 rtc0 = "/i2c@7000d000/tps65913@58"; 17 17 rtc1 = "/rtc@7000e000"; 18 + serial0 = &uartd; 18 19 }; 19 20 20 21 memory {
+5 -4
arch/arm/boot/dts/tegra114-roth.dts
··· 15 15 linux,initrd-end = <0x82800000>; 16 16 }; 17 17 18 + aliases { 19 + serial0 = &uartd; 20 + }; 21 + 18 22 firmware { 19 23 trusted-foundations { 20 24 compatible = "tlm,trusted-foundations"; ··· 920 916 regulator-name = "vddio-sdmmc3"; 921 917 regulator-min-microvolt = <1800000>; 922 918 regulator-max-microvolt = <3300000>; 923 - regulator-always-on; 924 - regulator-boot-on; 925 919 }; 926 920 927 921 ldousb { ··· 964 962 sdhci@78000400 { 965 963 status = "okay"; 966 964 bus-width = <4>; 967 - vmmc-supply = <&vddio_sdmmc3>; 965 + vqmmc-supply = <&vddio_sdmmc3>; 968 966 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 969 967 power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 970 968 }; ··· 973 971 sdhci@78000600 { 974 972 status = "okay"; 975 973 bus-width = <8>; 976 - vmmc-supply = <&vdd_1v8>; 977 974 non-removable; 978 975 }; 979 976
+4 -1
arch/arm/boot/dts/tegra114-tn7.dts
··· 15 15 linux,initrd-end = <0x82800000>; 16 16 }; 17 17 18 + aliases { 19 + serial0 = &uartd; 20 + }; 21 + 18 22 firmware { 19 23 trusted-foundations { 20 24 compatible = "tlm,trusted-foundations"; ··· 244 240 sdhci@78000600 { 245 241 status = "okay"; 246 242 bus-width = <8>; 247 - vmmc-supply = <&vdd_1v8>; 248 243 non-removable; 249 244 }; 250 245
-7
arch/arm/boot/dts/tegra114.dtsi
··· 9 9 compatible = "nvidia,tegra114"; 10 10 interrupt-parent = <&gic>; 11 11 12 - aliases { 13 - serial0 = &uarta; 14 - serial1 = &uartb; 15 - serial2 = &uartc; 16 - serial3 = &uartd; 17 - }; 18 - 19 12 host1x@50000000 { 20 13 compatible = "nvidia,tegra114-host1x", "simple-bus"; 21 14 reg = <0x50000000 0x00028000>;
+1
arch/arm/boot/dts/tegra124-jetson-tk1.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@0,7000d000/pmic@40"; 12 12 rtc1 = "/rtc@0,7000e000"; 13 + serial0 = &uartd; 13 14 }; 14 15 15 16 memory {
+1
arch/arm/boot/dts/tegra124-nyan-big.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@0,7000d000/pmic@40"; 12 12 rtc1 = "/rtc@0,7000e000"; 13 + serial0 = &uarta; 13 14 }; 14 15 15 16 memory {
+1
arch/arm/boot/dts/tegra124-venice2.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@0,7000d000/pmic@40"; 12 12 rtc1 = "/rtc@0,7000e000"; 13 + serial0 = &uarta; 13 14 }; 14 15 15 16 memory {
+4 -4
arch/arm/boot/dts/tegra124.dtsi
··· 286 286 * the APB DMA based serial driver, the comptible is 287 287 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 288 288 */ 289 - serial@0,70006000 { 289 + uarta: serial@0,70006000 { 290 290 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 291 291 reg = <0x0 0x70006000 0x0 0x40>; 292 292 reg-shift = <2>; ··· 299 299 status = "disabled"; 300 300 }; 301 301 302 - serial@0,70006040 { 302 + uartb: serial@0,70006040 { 303 303 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 304 304 reg = <0x0 0x70006040 0x0 0x40>; 305 305 reg-shift = <2>; ··· 312 312 status = "disabled"; 313 313 }; 314 314 315 - serial@0,70006200 { 315 + uartc: serial@0,70006200 { 316 316 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 317 317 reg = <0x0 0x70006200 0x0 0x40>; 318 318 reg-shift = <2>; ··· 325 325 status = "disabled"; 326 326 }; 327 327 328 - serial@0,70006300 { 328 + uartd: serial@0,70006300 { 329 329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 330 330 reg = <0x0 0x70006300 0x0 0x40>; 331 331 reg-shift = <2>;
+1
arch/arm/boot/dts/tegra20-harmony.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@7000d000/tps6586x@34"; 12 12 rtc1 = "/rtc@7000e000"; 13 + serial0 = &uartd; 13 14 }; 14 15 15 16 memory {
+5
arch/arm/boot/dts/tegra20-iris-512.dts
··· 6 6 model = "Toradex Colibri T20 512MB on Iris"; 7 7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; 8 8 9 + aliases { 10 + serial0 = &uarta; 11 + serial1 = &uartd; 12 + }; 13 + 9 14 host1x@50000000 { 10 15 hdmi@54280000 { 11 16 status = "okay";
+4
arch/arm/boot/dts/tegra20-medcom-wide.dts
··· 6 6 model = "Avionic Design Medcom-Wide board"; 7 7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; 8 8 9 + aliases { 10 + serial0 = &uartd; 11 + }; 12 + 9 13 pwm@7000a000 { 10 14 status = "okay"; 11 15 };
+2
arch/arm/boot/dts/tegra20-paz00.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@7000d000/tps6586x@34"; 12 12 rtc1 = "/rtc@7000e000"; 13 + serial0 = &uarta; 14 + serial1 = &uartc; 13 15 }; 14 16 15 17 memory {
+1
arch/arm/boot/dts/tegra20-seaboard.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@7000d000/tps6586x@34"; 12 12 rtc1 = "/rtc@7000e000"; 13 + serial0 = &uartd; 13 14 }; 14 15 15 16 memory {
+1
arch/arm/boot/dts/tegra20-tamonten.dtsi
··· 7 7 aliases { 8 8 rtc0 = "/i2c@7000d000/tps6586x@34"; 9 9 rtc1 = "/rtc@7000e000"; 10 + serial0 = &uartd; 10 11 }; 11 12 12 13 memory {
+1
arch/arm/boot/dts/tegra20-trimslice.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@7000c500/rtc@56"; 12 12 rtc1 = "/rtc@7000e000"; 13 + serial0 = &uarta; 13 14 }; 14 15 15 16 memory {
+1
arch/arm/boot/dts/tegra20-ventana.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@7000d000/tps6586x@34"; 12 12 rtc1 = "/rtc@7000e000"; 13 + serial0 = &uartd; 13 14 }; 14 15 15 16 memory {
+1
arch/arm/boot/dts/tegra20-whistler.dts
··· 10 10 aliases { 11 11 rtc0 = "/i2c@7000d000/max8907@3c"; 12 12 rtc1 = "/rtc@7000e000"; 13 + serial0 = &uarta; 13 14 }; 14 15 15 16 memory {
-8
arch/arm/boot/dts/tegra20.dtsi
··· 9 9 compatible = "nvidia,tegra20"; 10 10 interrupt-parent = <&intc>; 11 11 12 - aliases { 13 - serial0 = &uarta; 14 - serial1 = &uartb; 15 - serial2 = &uartc; 16 - serial3 = &uartd; 17 - serial4 = &uarte; 18 - }; 19 - 20 12 host1x@50000000 { 21 13 compatible = "nvidia,tegra20-host1x", "simple-bus"; 22 14 reg = <0x50000000 0x00024000>;
+4
arch/arm/boot/dts/tegra30-apalis-eval.dts
··· 11 11 rtc0 = "/i2c@7000c000/rtc@68"; 12 12 rtc1 = "/i2c@7000d000/tps65911@2d"; 13 13 rtc2 = "/rtc@7000e000"; 14 + serial0 = &uarta; 15 + serial1 = &uartb; 16 + serial2 = &uartc; 17 + serial3 = &uartd; 14 18 }; 15 19 16 20 pcie-controller@00003000 {
+1
arch/arm/boot/dts/tegra30-beaver.dts
··· 9 9 aliases { 10 10 rtc0 = "/i2c@7000d000/tps65911@2d"; 11 11 rtc1 = "/rtc@7000e000"; 12 + serial0 = &uarta; 12 13 }; 13 14 14 15 memory {
+2
arch/arm/boot/dts/tegra30-cardhu.dtsi
··· 30 30 aliases { 31 31 rtc0 = "/i2c@7000d000/tps65911@2d"; 32 32 rtc1 = "/rtc@7000e000"; 33 + serial0 = &uarta; 34 + serial1 = &uartc; 33 35 }; 34 36 35 37 memory {
+3
arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
··· 10 10 rtc0 = "/i2c@7000c000/rtc@68"; 11 11 rtc1 = "/i2c@7000d000/tps65911@2d"; 12 12 rtc2 = "/rtc@7000e000"; 13 + serial0 = &uarta; 14 + serial1 = &uartb; 15 + serial2 = &uartd; 13 16 }; 14 17 15 18 host1x@50000000 {
-8
arch/arm/boot/dts/tegra30.dtsi
··· 9 9 compatible = "nvidia,tegra30"; 10 10 interrupt-parent = <&intc>; 11 11 12 - aliases { 13 - serial0 = &uarta; 14 - serial1 = &uartb; 15 - serial2 = &uartc; 16 - serial3 = &uartd; 17 - serial4 = &uarte; 18 - }; 19 - 20 12 pcie-controller@00003000 { 21 13 compatible = "nvidia,tegra30-pcie"; 22 14 device_type = "pci";
+1
arch/arm/configs/multi_v7_defconfig
··· 217 217 CONFIG_I2C_DESIGNWARE_PLATFORM=y 218 218 CONFIG_I2C_EXYNOS5=y 219 219 CONFIG_I2C_MV64XXX=y 220 + CONFIG_I2C_S3C2410=y 220 221 CONFIG_I2C_SIRF=y 221 222 CONFIG_I2C_TEGRA=y 222 223 CONFIG_I2C_ST=y
+7 -2
arch/arm/mach-shmobile/clock-r8a7740.c
··· 455 455 MSTP128, MSTP127, MSTP125, 456 456 MSTP116, MSTP111, MSTP100, MSTP117, 457 457 458 - MSTP230, 458 + MSTP230, MSTP229, 459 459 MSTP222, 460 460 MSTP218, MSTP217, MSTP216, MSTP214, 461 461 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, ··· 474 474 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ 475 475 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ 476 476 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ 477 - [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ 477 + [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */ 478 478 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ 479 479 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ 480 480 481 481 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ 482 + [MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */ 482 483 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ 483 484 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ 484 485 [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ ··· 576 575 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), 577 576 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), 578 577 CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), 578 + CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]), 579 + CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]), 580 + CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]), 581 + CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]), 579 582 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), 580 583 CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), 581 584
+1 -1
arch/arm/mach-shmobile/clock-r8a7790.c
··· 68 68 69 69 #define SDCKCR 0xE6150074 70 70 #define SD2CKCR 0xE6150078 71 - #define SD3CKCR 0xE615007C 71 + #define SD3CKCR 0xE615026C 72 72 #define MMC0CKCR 0xE6150240 73 73 #define MMC1CKCR 0xE6150244 74 74 #define SSPCKCR 0xE6150248
+20
arch/arm/mach-shmobile/setup-sh73a0.c
··· 26 26 #include <linux/of_platform.h> 27 27 #include <linux/delay.h> 28 28 #include <linux/input.h> 29 + #include <linux/i2c/i2c-sh_mobile.h> 29 30 #include <linux/io.h> 30 31 #include <linux/serial_sci.h> 31 32 #include <linux/sh_dma.h> ··· 193 192 }, 194 193 }; 195 194 195 + static struct i2c_sh_mobile_platform_data i2c_platform_data = { 196 + .clks_per_count = 2, 197 + }; 198 + 196 199 static struct platform_device i2c0_device = { 197 200 .name = "i2c-sh_mobile", 198 201 .id = 0, 199 202 .resource = i2c0_resources, 200 203 .num_resources = ARRAY_SIZE(i2c0_resources), 204 + .dev = { 205 + .platform_data = &i2c_platform_data, 206 + }, 201 207 }; 202 208 203 209 static struct platform_device i2c1_device = { ··· 212 204 .id = 1, 213 205 .resource = i2c1_resources, 214 206 .num_resources = ARRAY_SIZE(i2c1_resources), 207 + .dev = { 208 + .platform_data = &i2c_platform_data, 209 + }, 215 210 }; 216 211 217 212 static struct platform_device i2c2_device = { ··· 222 211 .id = 2, 223 212 .resource = i2c2_resources, 224 213 .num_resources = ARRAY_SIZE(i2c2_resources), 214 + .dev = { 215 + .platform_data = &i2c_platform_data, 216 + }, 225 217 }; 226 218 227 219 static struct platform_device i2c3_device = { ··· 232 218 .id = 3, 233 219 .resource = i2c3_resources, 234 220 .num_resources = ARRAY_SIZE(i2c3_resources), 221 + .dev = { 222 + .platform_data = &i2c_platform_data, 223 + }, 235 224 }; 236 225 237 226 static struct platform_device i2c4_device = { ··· 242 225 .id = 4, 243 226 .resource = i2c4_resources, 244 227 .num_resources = ARRAY_SIZE(i2c4_resources), 228 + .dev = { 229 + .platform_data = &i2c_platform_data, 230 + }, 245 231 }; 246 232 247 233 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {