tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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net: ethernet: sun4i-emac: replace magic number with macro

This patch remove magic numbers in sun4i-emac.c and replace with macros
defined in sun4i-emac.h

Signed-off-by: Conley Lee <conleylee@foxmail.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Link: https://lore.kernel.org/r/tencent_71466C2135CD1780B19D7844BE3F167C940A@qq.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Conley Lee and committed by
Jakub Kicinski 274c2240 284a4d94

+35 -13
+17 -13
drivers/net/ethernet/allwinner/sun4i-emac.c
··· 106 106 107 107 /* set EMAC SPEED, depend on PHY */ 108 108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); 109 - reg_val &= ~(0x1 << 8); 109 + reg_val &= ~EMAC_MAC_SUPP_100M; 110 110 if (db->speed == SPEED_100) 111 - reg_val |= 1 << 8; 111 + reg_val |= EMAC_MAC_SUPP_100M; 112 112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 113 113 } 114 114 ··· 264 264 265 265 /* re enable interrupt */ 266 266 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 267 - reg_val |= (0x01 << 8); 267 + reg_val |= EMAC_INT_CTL_RX_EN; 268 268 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 269 269 270 270 db->emacrx_completed_flag = 1; ··· 429 429 /* initial EMAC */ 430 430 /* flush RX FIFO */ 431 431 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 432 - reg_val |= 0x8; 432 + reg_val |= EMAC_RX_CTL_FLUSH_FIFO; 433 433 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 434 434 udelay(1); 435 435 ··· 441 441 442 442 /* set MII clock */ 443 443 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); 444 - reg_val &= (~(0xf << 2)); 445 - reg_val |= (0xD << 2); 444 + reg_val &= ~EMAC_MAC_MCFG_MII_CLKD_MASK; 445 + reg_val |= EMAC_MAC_MCFG_MII_CLKD_72; 446 446 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); 447 447 448 448 /* clear RX counter */ ··· 506 506 507 507 /* enable RX/TX0/RX Hlevel interrup */ 508 508 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 509 - reg_val |= (0xf << 0) | (0x01 << 8); 509 + reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN | EMAC_INT_CTL_RX_EN); 510 510 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 511 511 512 512 spin_unlock_irqrestore(&db->lock, flags); ··· 637 637 if (!rxcount) { 638 638 db->emacrx_completed_flag = 1; 639 639 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 640 - reg_val |= (0xf << 0) | (0x01 << 8); 640 + reg_val |= (EMAC_INT_CTL_TX_EN | 641 + EMAC_INT_CTL_TX_ABRT_EN | 642 + EMAC_INT_CTL_RX_EN); 641 643 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 642 644 643 645 /* had one stuck? */ ··· 671 669 writel(reg_val | EMAC_CTL_RX_EN, 672 670 db->membase + EMAC_CTL_REG); 673 671 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 674 - reg_val |= (0xf << 0) | (0x01 << 8); 672 + reg_val |= (EMAC_INT_CTL_TX_EN | 673 + EMAC_INT_CTL_TX_ABRT_EN | 674 + EMAC_INT_CTL_RX_EN); 675 675 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 676 676 677 677 db->emacrx_completed_flag = 1; ··· 787 783 } 788 784 789 785 /* Transmit Interrupt check */ 790 - if (int_status & (0x01 | 0x02)) 786 + if (int_status & EMAC_INT_STA_TX_COMPLETE) 791 787 emac_tx_done(dev, db, int_status); 792 788 793 - if (int_status & (0x04 | 0x08)) 789 + if (int_status & EMAC_INT_STA_TX_ABRT) 794 790 netdev_info(dev, " ab : %x\n", int_status); 795 791 796 792 /* Re-enable interrupt mask */ 797 793 if (db->emacrx_completed_flag == 1) { 798 794 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 799 - reg_val |= (0xf << 0) | (0x01 << 8); 795 + reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN | EMAC_INT_CTL_RX_EN); 800 796 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 801 797 } else { 802 798 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 803 - reg_val |= (0xf << 0); 799 + reg_val |= (EMAC_INT_CTL_TX_EN | EMAC_INT_CTL_TX_ABRT_EN); 804 800 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 805 801 } 806 802
+18
drivers/net/ethernet/allwinner/sun4i-emac.h
··· 38 38 #define EMAC_RX_CTL_REG (0x3c) 39 39 #define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1) 40 40 #define EMAC_RX_CTL_DMA_EN (1 << 2) 41 + #define EMAC_RX_CTL_FLUSH_FIFO (1 << 3) 41 42 #define EMAC_RX_CTL_PASS_ALL_EN (1 << 4) 42 43 #define EMAC_RX_CTL_PASS_CTL_EN (1 << 5) 43 44 #define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6) ··· 62 61 #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) 63 62 #define EMAC_RX_FBC_REG (0x50) 64 63 #define EMAC_INT_CTL_REG (0x54) 64 + #define EMAC_INT_CTL_RX_EN (1 << 8) 65 + #define EMAC_INT_CTL_TX0_EN (1) 66 + #define EMAC_INT_CTL_TX1_EN (1 << 1) 67 + #define EMAC_INT_CTL_TX_EN (EMAC_INT_CTL_TX0_EN | EMAC_INT_CTL_TX1_EN) 68 + #define EMAC_INT_CTL_TX0_ABRT_EN (0x1 << 2) 69 + #define EMAC_INT_CTL_TX1_ABRT_EN (0x1 << 3) 70 + #define EMAC_INT_CTL_TX_ABRT_EN (EMAC_INT_CTL_TX0_ABRT_EN | EMAC_INT_CTL_TX1_ABRT_EN) 65 71 #define EMAC_INT_STA_REG (0x58) 72 + #define EMAC_INT_STA_TX0_COMPLETE (0x1) 73 + #define EMAC_INT_STA_TX1_COMPLETE (0x1 << 1) 74 + #define EMAC_INT_STA_TX_COMPLETE (EMAC_INT_STA_TX0_COMPLETE | EMAC_INT_STA_TX1_COMPLETE) 75 + #define EMAC_INT_STA_TX0_ABRT (0x1 << 2) 76 + #define EMAC_INT_STA_TX1_ABRT (0x1 << 3) 77 + #define EMAC_INT_STA_TX_ABRT (EMAC_INT_STA_TX0_ABRT | EMAC_INT_STA_TX1_ABRT) 78 + #define EMAC_INT_STA_RX_COMPLETE (0x1 << 8) 66 79 #define EMAC_MAC_CTL0_REG (0x5c) 67 80 #define EMAC_MAC_CTL0_RX_FLOW_CTL_EN (1 << 2) 68 81 #define EMAC_MAC_CTL0_TX_FLOW_CTL_EN (1 << 3) ··· 102 87 #define EMAC_MAC_CLRT_RM (0x0f) 103 88 #define EMAC_MAC_MAXF_REG (0x70) 104 89 #define EMAC_MAC_SUPP_REG (0x74) 90 + #define EMAC_MAC_SUPP_100M (0x1 << 8) 105 91 #define EMAC_MAC_TEST_REG (0x78) 106 92 #define EMAC_MAC_MCFG_REG (0x7c) 93 + #define EMAC_MAC_MCFG_MII_CLKD_MASK (0xff << 2) 94 + #define EMAC_MAC_MCFG_MII_CLKD_72 (0x0d << 2) 107 95 #define EMAC_MAC_A0_REG (0x98) 108 96 #define EMAC_MAC_A1_REG (0x9c) 109 97 #define EMAC_MAC_A2_REG (0xa0)