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PCI: Rename PCI_VC_PORT_REG1/2 to PCI_VC_PORT_CAP1/2

These are set of two capability registers, it's pretty much given that
they're registers, so reflect their purpose in the name.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

authored by

Alex Williamson and committed by
Bjorn Helgaas 274127a1 425c1b22

+29 -29
+14 -14
drivers/pci/vc.c
··· 104 104 static void pci_vc_enable(struct pci_dev *dev, int pos, int res) 105 105 { 106 106 int ctrl_pos, status_pos, id, pos2, evcc, i, ctrl_pos2, status_pos2; 107 - u32 ctrl, header, reg1, ctrl2; 107 + u32 ctrl, header, cap1, ctrl2; 108 108 struct pci_dev *link = NULL; 109 109 110 110 /* Enable VCs from the downstream device */ ··· 129 129 if (!pos2) 130 130 goto enable; 131 131 132 - pci_read_config_dword(dev->bus->self, pos2 + PCI_VC_PORT_REG1, &reg1); 133 - evcc = reg1 & PCI_VC_REG1_EVCC; 132 + pci_read_config_dword(dev->bus->self, pos2 + PCI_VC_PORT_CAP1, &cap1); 133 + evcc = cap1 & PCI_VC_CAP1_EVCC; 134 134 135 135 /* VC0 is hardwired enabled, so we can start with 1 */ 136 136 for (i = 1; i < evcc + 1; i++) { ··· 188 188 struct pci_cap_saved_state *save_state, 189 189 bool save) 190 190 { 191 - u32 reg1; 191 + u32 cap1; 192 192 char evcc, lpevcc, parb_size; 193 193 int i, len = 0; 194 194 u8 *buf = save_state ? (u8 *)save_state->cap.data : NULL; ··· 201 201 return -ENOMEM; 202 202 } 203 203 204 - pci_read_config_dword(dev, pos + PCI_VC_PORT_REG1, &reg1); 204 + pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP1, &cap1); 205 205 /* Extended VC Count (not counting VC0) */ 206 - evcc = reg1 & PCI_VC_REG1_EVCC; 206 + evcc = cap1 & PCI_VC_CAP1_EVCC; 207 207 /* Low Priority Extended VC Count (not counting VC0) */ 208 - lpevcc = (reg1 & PCI_VC_REG1_LPEVCC) >> 4; 208 + lpevcc = (cap1 & PCI_VC_CAP1_LPEVCC) >> 4; 209 209 /* Port Arbitration Table Entry Size (bits) */ 210 - parb_size = 1 << ((reg1 & PCI_VC_REG1_ARB_SIZE) >> 10); 210 + parb_size = 1 << ((cap1 & PCI_VC_CAP1_ARB_SIZE) >> 10); 211 211 212 212 /* 213 213 * Port VC Control Register contains VC Arbitration Select, which ··· 231 231 * in Port VC Capability Register 2 then save/restore it next. 232 232 */ 233 233 if (lpevcc) { 234 - u32 reg2; 234 + u32 cap2; 235 235 int vcarb_offset; 236 236 237 - pci_read_config_dword(dev, pos + PCI_VC_PORT_REG2, &reg2); 238 - vcarb_offset = ((reg2 & PCI_VC_REG2_ARB_OFF) >> 24) * 16; 237 + pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP2, &cap2); 238 + vcarb_offset = ((cap2 & PCI_VC_CAP2_ARB_OFF) >> 24) * 16; 239 239 240 240 if (vcarb_offset) { 241 241 int size, vcarb_phases = 0; 242 242 243 - if (reg2 & PCI_VC_REG2_128_PHASE) 243 + if (cap2 & PCI_VC_CAP2_128_PHASE) 244 244 vcarb_phases = 128; 245 - else if (reg2 & PCI_VC_REG2_64_PHASE) 245 + else if (cap2 & PCI_VC_CAP2_64_PHASE) 246 246 vcarb_phases = 64; 247 - else if (reg2 & PCI_VC_REG2_32_PHASE) 247 + else if (cap2 & PCI_VC_CAP2_32_PHASE) 248 248 vcarb_phases = 32; 249 249 250 250 /* Fixed 4 bits per phase per lpevcc (plus VC0) */
+6 -6
drivers/vfio/pci/vfio_pci_config.c
··· 975 975 int ret, evcc, phases, vc_arb; 976 976 int len = PCI_CAP_VC_BASE_SIZEOF; 977 977 978 - ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG1, &tmp); 978 + ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp); 979 979 if (ret) 980 980 return pcibios_err_to_errno(ret); 981 981 982 - evcc = tmp & PCI_VC_REG1_EVCC; /* extended vc count */ 983 - ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG2, &tmp); 982 + evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */ 983 + ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp); 984 984 if (ret) 985 985 return pcibios_err_to_errno(ret); 986 986 987 - if (tmp & PCI_VC_REG2_128_PHASE) 987 + if (tmp & PCI_VC_CAP2_128_PHASE) 988 988 phases = 128; 989 - else if (tmp & PCI_VC_REG2_64_PHASE) 989 + else if (tmp & PCI_VC_CAP2_64_PHASE) 990 990 phases = 64; 991 - else if (tmp & PCI_VC_REG2_32_PHASE) 991 + else if (tmp & PCI_VC_CAP2_32_PHASE) 992 992 phases = 32; 993 993 else 994 994 phases = 0;
+9 -9
include/uapi/linux/pci_regs.h
··· 677 677 #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ 678 678 679 679 /* Virtual Channel */ 680 - #define PCI_VC_PORT_REG1 4 681 - #define PCI_VC_REG1_EVCC 0x00000007 /* extended VC count */ 682 - #define PCI_VC_REG1_LPEVCC 0x00000070 /* low prio extended VC count */ 683 - #define PCI_VC_REG1_ARB_SIZE 0x00000c00 684 - #define PCI_VC_PORT_REG2 8 685 - #define PCI_VC_REG2_32_PHASE 0x00000002 686 - #define PCI_VC_REG2_64_PHASE 0x00000004 687 - #define PCI_VC_REG2_128_PHASE 0x00000008 688 - #define PCI_VC_REG2_ARB_OFF 0xff000000 680 + #define PCI_VC_PORT_CAP1 4 681 + #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ 682 + #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ 683 + #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 684 + #define PCI_VC_PORT_CAP2 8 685 + #define PCI_VC_CAP2_32_PHASE 0x00000002 686 + #define PCI_VC_CAP2_64_PHASE 0x00000004 687 + #define PCI_VC_CAP2_128_PHASE 0x00000008 688 + #define PCI_VC_CAP2_ARB_OFF 0xff000000 689 689 #define PCI_VC_PORT_CTRL 12 690 690 #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 691 691 #define PCI_VC_PORT_STATUS 14