Merge branch 'omap-for-v4.6/dt-gpmc' into omap-for-v4.6/dt

··· 236 236 status = "okay"; 237 237 238 238 nand@0,0 { 239 239 - reg = <0 0 0>; /* CS0, offset 0 */ 239 239 + compatible = "ti,omap2-nand"; 240 240 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 241 241 + interrupt-parent = <&gpmc>; 242 242 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 243 243 + <1 IRQ_TYPE_NONE>; /* termcount */ 240 244 nand-bus-width = <8>; 241 245 ti,nand-ecc-opt = "bch8"; 242 246 ti,nand-xfer-type = "polled"; ··· 261 257 gpmc,access-ns = <64>; 262 258 gpmc,rd-cycle-ns = <82>; 263 259 gpmc,wr-cycle-ns = <82>; 264 264 - gpmc,wait-on-read = "true"; 265 265 - gpmc,wait-on-write = "true"; 266 260 gpmc,bus-turnaround-ns = <0>; 267 261 gpmc,cycle2cycle-delay-ns = <0>; 268 262 gpmc,clk-activation-ns = <0>; 269 269 - gpmc,wait-monitoring-ns = <0>; 270 263 gpmc,wr-access-ns = <40>; 271 264 gpmc,wr-data-mux-bus-ns = <0>; 272 265

+5 -3

arch/arm/boot/dts/am335x-chilisom.dtsi

reviewed

··· 7 7 * published by the Free Software Foundation. 8 8 */ 9 9 #include "am33xx.dtsi" 10 10 + #include <dt-bindings/interrupt-controller/irq.h> 10 11 11 12 / { 12 13 model = "Grinn AM335x ChiliSOM"; ··· 219 218 pinctrl-0 = <&nandflash_pins>; 220 219 ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ 221 220 nand@0,0 { 221 221 + compatible = "ti,omap2-nand"; 222 222 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 223 223 + interrupt-parent = <&gpmc>; 224 224 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 225 225 + <1 IRQ_TYPE_NONE>; /* termcount */ 223 226 ti,nand-ecc-opt = "bch8"; 224 227 ti,elm-id = <&elm>; 225 228 nand-bus-width = <8>; ··· 242 237 gpmc,access-ns = <64>; 243 238 gpmc,rd-cycle-ns = <82>; 244 239 gpmc,wr-cycle-ns = <82>; 245 245 - gpmc,wait-on-read = "true"; 246 246 - gpmc,wait-on-write = "true"; 247 240 gpmc,bus-turnaround-ns = <0>; 248 241 gpmc,cycle2cycle-delay-ns = <0>; 249 242 gpmc,clk-activation-ns = <0>; 250 250 - gpmc,wait-monitoring-ns = <0>; 251 243 gpmc,wr-access-ns = <40>; 252 244 gpmc,wr-data-mux-bus-ns = <0>; 253 245 };

+5 -4

arch/arm/boot/dts/am335x-cm-t335.dts

reviewed

··· 406 406 pinctrl-0 = <&nandflash_pins>; 407 407 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 408 408 nand@0,0 { 409 409 - reg = <0 0 0>; /* CS0, offset 0 */ 409 409 + compatible = "ti,omap2-nand"; 410 410 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 411 411 + interrupt-parent = <&gpmc>; 412 412 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 413 413 + <1 IRQ_TYPE_NONE>; /* termcount */ 410 414 ti,nand-ecc-opt = "bch8"; 411 415 ti,elm-id = <&elm>; 412 416 nand-bus-width = <8>; ··· 429 425 gpmc,access-ns = <64>; 430 426 gpmc,rd-cycle-ns = <82>; 431 427 gpmc,wr-cycle-ns = <82>; 432 432 - gpmc,wait-on-read = "true"; 433 433 - gpmc,wait-on-write = "true"; 434 428 gpmc,bus-turnaround-ns = <0>; 435 429 gpmc,cycle2cycle-delay-ns = <0>; 436 430 gpmc,clk-activation-ns = <0>; 437 437 - gpmc,wait-monitoring-ns = <0>; 438 431 gpmc,wr-access-ns = <40>; 439 432 gpmc,wr-data-mux-bus-ns = <0>; 440 433 /* MTD partition table */

+4 -3

arch/arm/boot/dts/am335x-evm.dts

reviewed

··· 519 519 pinctrl-0 = <&nandflash_pins_s0>; 520 520 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 521 521 nand@0,0 { 522 522 + compatible = "ti,omap2-nand"; 522 523 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 524 524 + interrupt-parent = <&gpmc>; 525 525 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 526 526 + <1 IRQ_TYPE_NONE>; /* termcount */ 523 527 ti,nand-ecc-opt = "bch8"; 524 528 ti,elm-id = <&elm>; 525 529 nand-bus-width = <8>; ··· 542 538 gpmc,access-ns = <64>; 543 539 gpmc,rd-cycle-ns = <82>; 544 540 gpmc,wr-cycle-ns = <82>; 545 545 - gpmc,wait-on-read = "true"; 546 546 - gpmc,wait-on-write = "true"; 547 541 gpmc,bus-turnaround-ns = <0>; 548 542 gpmc,cycle2cycle-delay-ns = <0>; 549 543 gpmc,clk-activation-ns = <0>; 550 550 - gpmc,wait-monitoring-ns = <0>; 551 544 gpmc,wr-access-ns = <40>; 552 545 gpmc,wr-data-mux-bus-ns = <0>; 553 546 /* MTD partition table */

+5 -3

arch/arm/boot/dts/am335x-igep0033.dtsi

reviewed

··· 11 11 /dts-v1/; 12 12 13 13 #include "am33xx.dtsi" 14 14 + #include <dt-bindings/interrupt-controller/irq.h> 14 15 15 16 / { 16 17 cpus { ··· 130 129 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 131 130 132 131 nand@0,0 { 132 132 + compatible = "ti,omap2-nand"; 133 133 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 134 134 + interrupt-parent = <&gpmc>; 135 135 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 136 136 + <1 IRQ_TYPE_NONE>; /* termcount */ 134 137 nand-bus-width = <8>; 135 138 ti,nand-ecc-opt = "bch8"; 136 139 gpmc,device-width = <1>; ··· 152 147 gpmc,access-ns = <64>; 153 148 gpmc,rd-cycle-ns = <82>; 154 149 gpmc,wr-cycle-ns = <82>; 155 155 - gpmc,wait-on-read = "true"; 156 156 - gpmc,wait-on-write = "true"; 157 150 gpmc,bus-turnaround-ns = <0>; 158 151 gpmc,cycle2cycle-delay-ns = <0>; 159 152 gpmc,clk-activation-ns = <0>; 160 160 - gpmc,wait-monitoring-ns = <0>; 161 153 gpmc,wr-access-ns = <40>; 162 154 gpmc,wr-data-mux-bus-ns = <0>; 163 155

+5 -3

arch/arm/boot/dts/am335x-phycore-som.dtsi

reviewed

··· 8 8 */ 9 9 10 10 #include "am33xx.dtsi" 11 11 + #include <dt-bindings/interrupt-controller/irq.h> 11 12 12 13 / { 13 14 model = "Phytec AM335x phyCORE"; ··· 166 165 pinctrl-0 = <&nandflash_pins>; 167 166 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ 168 167 nandflash: nand@0,0 { 168 168 + compatible = "ti,omap2-nand"; 169 169 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 170 170 + interrupt-parent = <&gpmc>; 171 171 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 172 172 + <1 IRQ_TYPE_NONE>; /* termcount */ 170 173 nand-bus-width = <8>; 171 174 ti,nand-ecc-opt = "bch8"; 172 175 gpmc,device-nand = "true"; ··· 189 184 gpmc,access-ns = <30>; 190 185 gpmc,rd-cycle-ns = <30>; 191 186 gpmc,wr-cycle-ns = <30>; 192 192 - gpmc,wait-on-read = "true"; 193 193 - gpmc,wait-on-write = "true"; 194 187 gpmc,bus-turnaround-ns = <0>; 195 188 gpmc,cycle2cycle-delay-ns = <50>; 196 189 gpmc,cycle2cycle-diffcsen; 197 190 gpmc,clk-activation-ns = <0>; 198 198 - gpmc,wait-monitoring-ns = <0>; 199 191 gpmc,wr-access-ns = <30>; 200 192 gpmc,wr-data-mux-bus-ns = <0>; 201 193

arch/arm/boot/dts/am33xx.dtsi

reviewed

··· 865 865 gpmc,num-waitpins = <2>; 866 866 #address-cells = <2>; 867 867 #size-cells = <1>; 868 868 + interrupt-controller; 869 869 + #interrupt-cells = <2>; 868 870 status = "disabled"; 869 871 }; 870 872

arch/arm/boot/dts/am4372.dtsi

reviewed

··· 893 893 gpmc,num-waitpins = <2>; 894 894 #address-cells = <2>; 895 895 #size-cells = <1>; 896 896 + interrupt-controller; 897 897 + #interrupt-cells = <2>; 896 898 status = "disabled"; 897 899 }; 898 900

+5 -6

arch/arm/boot/dts/am437x-cm-t43.dts

reviewed

··· 146 146 pinctrl-0 = <&nand_flash_x8>; 147 147 ranges = <0 0 0x08000000 0x1000000>; 148 148 nand@0,0 { 149 149 - reg = <0 0 0>; 149 149 + compatible = "ti,omap2-nand"; 150 150 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 151 151 + interrupt-parent = <&gpmc>; 152 152 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 153 153 + <1 IRQ_TYPE_NONE>; /* termcount */ 150 154 ti,nand-ecc-opt = "bch8"; 151 155 ti,elm-id = <&elm>; 152 156 ··· 170 166 gpmc,access-ns = <64>; 171 167 gpmc,rd-cycle-ns = <82>; 172 168 gpmc,wr-cycle-ns = <82>; 173 173 - gpmc,wait-on-read = "true"; 174 174 - gpmc,wait-on-write = "true"; 175 169 gpmc,bus-turnaround-ns = <0>; 176 170 gpmc,cycle2cycle-delay-ns = <0>; 177 171 gpmc,clk-activation-ns = <0>; 178 178 - gpmc,wait-monitoring-ns = <0>; 179 172 gpmc,wr-access-ns = <40>; 180 173 gpmc,wr-data-mux-bus-ns = <0>; 181 181 - 182 182 - gpmc,wait-pin = <0>; 183 174 184 175 #address-cells = <1>; 185 176 #size-cells = <1>;

+5 -3

arch/arm/boot/dts/am437x-gp-evm.dts

reviewed

··· 812 812 status = "okay"; 813 813 pinctrl-names = "default"; 814 814 pinctrl-0 = <&nand_flash_x8>; 815 815 - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 815 815 + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 816 816 nand@0,0 { 817 817 + compatible = "ti,omap2-nand"; 817 818 reg = <0 0 4>; /* device IO registers */ 819 819 + interrupt-parent = <&gpmc>; 820 820 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 821 821 + <1 IRQ_TYPE_NONE>; /* termcount */ 818 822 ti,nand-ecc-opt = "bch16"; 819 823 ti,elm-id = <&elm>; 820 824 nand-bus-width = <8>; ··· 837 833 gpmc,access-ns = <30>; 838 834 gpmc,rd-cycle-ns = <40>; 839 835 gpmc,wr-cycle-ns = <40>; 840 840 - gpmc,wait-pin = <0>; 841 836 gpmc,bus-turnaround-ns = <0>; 842 837 gpmc,cycle2cycle-delay-ns = <0>; 843 838 gpmc,clk-activation-ns = <0>; 844 844 - gpmc,wait-monitoring-ns = <0>; 845 839 gpmc,wr-access-ns = <40>; 846 840 gpmc,wr-data-mux-bus-ns = <0>; 847 841 /* MTD partition table */

+5 -3

arch/arm/boot/dts/am43x-epos-evm.dts

reviewed

··· 561 561 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 562 562 pinctrl-names = "default"; 563 563 pinctrl-0 = <&nand_flash_x8>; 564 564 - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 564 564 + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 565 565 nand@0,0 { 566 566 + compatible = "ti,omap2-nand"; 566 567 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 568 568 + interrupt-parent = <&gpmc>; 569 569 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 570 570 + <1 IRQ_TYPE_NONE>; /* termcount */ 567 571 ti,nand-ecc-opt = "bch16"; 568 572 ti,elm-id = <&elm>; 569 573 nand-bus-width = <8>; ··· 586 582 gpmc,access-ns = <30>; /* tCEA + 4*/ 587 583 gpmc,rd-cycle-ns = <40>; 588 584 gpmc,wr-cycle-ns = <40>; 589 589 - gpmc,wait-pin = <0>; 590 585 gpmc,bus-turnaround-ns = <0>; 591 586 gpmc,cycle2cycle-delay-ns = <0>; 592 587 gpmc,clk-activation-ns = <0>; 593 593 - gpmc,wait-monitoring-ns = <0>; 594 588 gpmc,wr-access-ns = <40>; 595 589 gpmc,wr-data-mux-bus-ns = <0>; 596 590 /* MTD partition table */

+5 -3

arch/arm/boot/dts/dm8168-evm.dts

reviewed

··· 6 6 /dts-v1/; 7 7 8 8 #include "dm816x.dtsi" 9 9 + #include <dt-bindings/interrupt-controller/irq.h> 9 10 10 11 / { 11 12 model = "DM8168 EVM"; ··· 86 85 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ 87 86 88 87 nand@0,0 { 88 88 + compatible = "ti,omap2-nand"; 89 89 linux,mtd-name= "micron,mt29f2g16aadwp"; 90 90 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 91 91 + interrupt-parent = <&gpmc>; 92 92 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 93 93 + <1 IRQ_TYPE_NONE>; /* termcount */ 91 94 #address-cells = <1>; 92 95 #size-cells = <1>; 93 96 ti,nand-ecc-opt = "bch8"; ··· 111 106 gpmc,access-ns = <64>; 112 107 gpmc,rd-cycle-ns = <82>; 113 108 gpmc,wr-cycle-ns = <82>; 114 114 - gpmc,wait-on-read = "true"; 115 115 - gpmc,wait-on-write = "true"; 116 109 gpmc,bus-turnaround-ns = <0>; 117 110 gpmc,cycle2cycle-delay-ns = <0>; 118 111 gpmc,clk-activation-ns = <0>; 119 119 - gpmc,wait-monitoring-ns = <0>; 120 112 gpmc,wr-access-ns = <40>; 121 113 gpmc,wr-data-mux-bus-ns = <0>; 122 114 partition@0 {

arch/arm/boot/dts/dm816x.dtsi

reviewed

··· 183 183 dma-names = "rxtx"; 184 184 gpmc,num-cs = <6>; 185 185 gpmc,num-waitpins = <2>; 186 186 + interrupt-controller; 187 187 + #interrupt-cells = <2>; 186 188 }; 187 189 188 190 i2c1: i2c@48028000 {

+5 -2

arch/arm/boot/dts/dra7-evm.dts

reviewed

··· 741 741 status = "okay"; 742 742 pinctrl-names = "default"; 743 743 pinctrl-0 = <&nand_flash_x16>; 744 744 - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 744 744 + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 745 745 nand@0,0 { 746 746 + compatible = "ti,omap2-nand"; 746 747 reg = <0 0 4>; /* device IO registers */ 748 748 + interrupt-parent = <&gpmc>; 749 749 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 750 750 + <1 IRQ_TYPE_NONE>; /* termcount */ 747 751 ti,nand-ecc-opt = "bch8"; 748 752 ti,elm-id = <&elm>; 749 753 nand-bus-width = <16>; ··· 770 766 gpmc,bus-turnaround-ns = <0>; 771 767 gpmc,cycle2cycle-delay-ns = <0>; 772 768 gpmc,clk-activation-ns = <0>; 773 773 - gpmc,wait-monitoring-ns = <0>; 774 769 gpmc,wr-data-mux-bus-ns = <0>; 775 770 /* MTD partition table */ 776 771 /* All SPL-* partitions are sized to minimal length

arch/arm/boot/dts/dra7.dtsi

reviewed

··· 1402 1402 gpmc,num-waitpins = <2>; 1403 1403 #address-cells = <2>; 1404 1404 #size-cells = <1>; 1405 1405 + interrupt-controller; 1406 1406 + #interrupt-cells = <2>; 1405 1407 status = "disabled"; 1406 1408 }; 1407 1409

+5 -2

arch/arm/boot/dts/dra72-evm.dts

reviewed

··· 492 492 status = "okay"; 493 493 pinctrl-names = "default"; 494 494 pinctrl-0 = <&nand_default>; 495 495 - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 495 495 + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 496 496 nand@0,0 { 497 497 /* To use NAND, DIP switch SW5 must be set like so: 498 498 * SW5.1 (NAND_SELn) = ON (LOW) 499 499 * SW5.9 (GPMC_WPN) = OFF (HIGH) 500 500 */ 501 501 + compatible = "ti,omap2-nand"; 501 502 reg = <0 0 4>; /* device IO registers */ 503 503 + interrupt-parent = <&gpmc>; 504 504 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 505 505 + <1 IRQ_TYPE_NONE>; /* termcount */ 502 506 ti,nand-ecc-opt = "bch8"; 503 507 ti,elm-id = <&elm>; 504 508 nand-bus-width = <16>; ··· 525 521 gpmc,bus-turnaround-ns = <0>; 526 522 gpmc,cycle2cycle-delay-ns = <0>; 527 523 gpmc,clk-activation-ns = <0>; 528 528 - gpmc,wait-monitoring-ns = <0>; 529 524 gpmc,wr-data-mux-bus-ns = <0>; 530 525 /* MTD partition table */ 531 526 /* All SPL-* partitions are sized to minimal length

+2 -1

arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts

reviewed

··· 102 102 }; 103 103 104 104 &gpmc { 105 105 - ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */ 105 105 + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ 106 106 + 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ 106 107 107 108 ethernet@gpmc { 108 109 pinctrl-names = "default";

+6 -2

arch/arm/boot/dts/logicpd-torpedo-som.dtsi

reviewed

··· 35 35 }; 36 36 37 37 &gpmc { 38 38 - ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */ 38 38 + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 39 39 40 40 nand@0,0 { 41 41 - linux,mtd-name = "micron,mt29f4g16abbda3w"; 41 41 + compatible = "ti,omap2-nand"; 42 42 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 43 43 + interrupt-parent = <&gpmc>; 44 44 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 45 45 + <1 IRQ_TYPE_NONE>; /* termcount */ 46 46 + linux,mtd-name = "micron,mt29f4g16abbda3w"; 43 47 nand-bus-width = <16>; 44 48 ti,nand-ecc-opt = "bch8"; 45 49 gpmc,sync-clk-ps = <0>;

+4 -1

arch/arm/boot/dts/omap3-beagle.dts

reviewed

··· 384 384 385 385 /* Chip select 0 */ 386 386 nand@0,0 { 387 387 + compatible = "ti,omap2-nand"; 387 388 reg = <0 0 4>; /* NAND I/O window, 4 bytes */ 388 388 - interrupts = <20>; 389 389 + interrupt-parent = <&gpmc>; 390 390 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 391 391 + <1 IRQ_TYPE_NONE>; /* termcount */ 389 392 ti,nand-ecc-opt = "ham1"; 390 393 nand-bus-width = <16>; 391 394 #address-cells = <1>;

+5 -1

arch/arm/boot/dts/omap3-cm-t3x.dtsi

reviewed

··· 261 261 }; 262 262 263 263 &gpmc { 264 264 - ranges = <0 0 0x00000000 0x01000000>; 264 264 + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ 265 265 266 266 nand@0,0 { 267 267 + compatible = "ti,omap2-nand"; 267 268 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 269 269 + interrupt-parent = <&gpmc>; 270 270 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 271 271 + <1 IRQ_TYPE_NONE>; /* termcount */ 268 272 nand-bus-width = <8>; 269 273 gpmc,device-width = <1>; 270 274 ti,nand-ecc-opt = "sw";

arch/arm/boot/dts/omap3-devkit8000-common.dtsi

reviewed

··· 204 204 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 205 205 206 206 nand@0,0 { 207 207 + compatible = "ti,omap2-nand"; 207 208 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 209 209 + interrupt-parent = <&gpmc>; 210 210 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 211 211 + <1 IRQ_TYPE_NONE>; /* termcount */ 208 212 nand-bus-width = <16>; 209 213 gpmc,device-width = <2>; 210 214 ti,nand-ecc-opt = "sw";

+6 -2

arch/arm/boot/dts/omap3-evm-37xx.dts

reviewed

··· 154 154 }; 155 155 156 156 &gpmc { 157 157 - ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */ 157 157 + ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ 158 158 <5 0 0x2c000000 0x01000000>; 159 159 160 160 nand@0,0 { 161 161 + compatible = "ti,omap2-nand"; 162 162 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 163 163 + interrupt-parent = <&gpmc>; 164 164 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 165 165 + <1 IRQ_TYPE_NONE>; /* termcount */ 161 166 linux,mtd-name= "hynix,h8kds0un0mer-4em"; 162 162 - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 163 167 nand-bus-width = <16>; 164 168 gpmc,device-width = <2>; 165 169 ti,nand-ecc-opt = "bch8";

arch/arm/boot/dts/omap3-gta04.dtsi

reviewed

··· 492 492 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 493 493 494 494 nand@0,0 { 495 495 + compatible = "ti,omap2-nand"; 495 496 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 497 497 + interrupt-parent = <&gpmc>; 498 498 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 499 499 + <1 IRQ_TYPE_NONE>; /* termcount */ 496 500 nand-bus-width = <16>; 497 501 ti,nand-ecc-opt = "bch8"; 498 502

+5 -1

arch/arm/boot/dts/omap3-igep.dtsi

reviewed

··· 99 99 100 100 &gpmc { 101 101 nand@0,0 { 102 102 + compatible = "ti,omap2-nand"; 103 103 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 104 104 + interrupt-parent = <&gpmc>; 105 105 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 106 106 + <1 IRQ_TYPE_NONE>; /* termcount */ 102 107 linux,mtd-name= "micron,mt29c4g96maz"; 103 103 - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 104 108 nand-bus-width = <16>; 105 109 gpmc,device-width = <2>; 106 110 ti,nand-ecc-opt = "bch8";

+2 -2

arch/arm/boot/dts/omap3-igep0020-common.dtsi

reviewed

··· 210 210 }; 211 211 212 212 &gpmc { 213 213 - ranges = <0 0 0x00000000 0x20000000>, 214 214 - <5 0 0x2c000000 0x01000000>; 213 213 + ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ 214 214 + <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ 215 215 216 216 ethernet@gpmc { 217 217 pinctrl-names = "default";

arch/arm/boot/dts/omap3-igep0030-common.dtsi

reviewed

··· 99 99 pinctrl-names = "default"; 100 100 pinctrl-0 = <&uart2_pins>; 101 101 }; 102 102 + 103 103 + &gpmc { 104 104 + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ 105 105 + };

+7 -3

arch/arm/boot/dts/omap3-ldp.dts

reviewed

··· 97 97 }; 98 98 99 99 &gpmc { 100 100 - ranges = <0 0 0x00000000 0x01000000>, 101 101 - <1 0 0x08000000 0x01000000>; 100 100 + ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ 101 101 + <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ 102 102 103 103 nand@0,0 { 104 104 + compatible = "ti,omap2-nand"; 105 105 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 106 106 + interrupt-parent = <&gpmc>; 107 107 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 108 108 + <1 IRQ_TYPE_NONE>; /* termcount */ 104 109 linux,mtd-name= "micron,nand"; 105 105 - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 106 110 nand-bus-width = <16>; 107 111 gpmc,device-width = <2>; 108 112 ti,nand-ecc-opt = "bch8";

+5 -1

arch/arm/boot/dts/omap3-lilly-a83x.dtsi

reviewed

··· 362 362 <7 0 0x15000000 0x01000000>; 363 363 364 364 nand@0,0 { 365 365 - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 365 365 + compatible = "ti,omap2-nand"; 366 366 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 367 367 + interrupt-parent = <&gpmc>; 368 368 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 369 369 + <1 IRQ_TYPE_NONE>; /* termcount */ 366 370 nand-bus-width = <16>; 367 371 ti,nand-ecc-opt = "bch8"; 368 372 /* no elm on omap3 */

+5 -1

arch/arm/boot/dts/omap3-overo-base.dtsi

reviewed

··· 226 226 ranges = <0 0 0x00000000 0x20000000>; 227 227 228 228 nand@0,0 { 229 229 + compatible = "ti,omap2-nand"; 229 230 linux,mtd-name= "micron,mt29c4g96maz"; 230 230 - reg = <0 0 0>; 231 231 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 232 232 + interrupt-parent = <&gpmc>; 233 233 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 234 234 + <1 IRQ_TYPE_NONE>; /* termcount */ 231 235 nand-bus-width = <16>; 232 236 gpmc,device-width = <2>; 233 237 ti,nand-ecc-opt = "bch8";

arch/arm/boot/dts/omap3-pandora-common.dtsi

reviewed

··· 546 546 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 547 547 548 548 nand@0,0 { 549 549 + compatible = "ti,omap2-nand"; 549 550 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 551 551 + interrupt-parent = <&gpmc>; 552 552 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 553 553 + <1 IRQ_TYPE_NONE>; /* termcount */ 550 554 nand-bus-width = <16>; 551 555 ti,nand-ecc-opt = "sw"; 552 556

+5 -1

arch/arm/boot/dts/omap3-tao3530.dtsi

reviewed

··· 275 275 }; 276 276 277 277 &gpmc { 278 278 - ranges = <0 0 0x00000000 0x01000000>; 278 278 + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ 279 279 280 280 nand@0,0 { 281 281 + compatible = "ti,omap2-nand"; 281 282 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 283 283 + interrupt-parent = <&gpmc>; 284 284 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 285 285 + <1 IRQ_TYPE_NONE>; /* termcount */ 282 286 nand-bus-width = <16>; 283 287 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ 284 288 ti,nand-ecc-opt = "sw";

arch/arm/boot/dts/omap3.dtsi

reviewed

··· 723 723 gpmc,num-waitpins = <4>; 724 724 #address-cells = <2>; 725 725 #size-cells = <1>; 726 726 + interrupt-controller; 727 727 + #interrupt-cells = <2>; 726 728 }; 727 729 728 730 usb_otg_hs: usb_otg_hs@480ab000 {

+5 -1

arch/arm/boot/dts/omap3430-sdp.dts

reviewed

··· 103 103 }; 104 104 105 105 nand@1,0 { 106 106 + compatible = "ti,omap2-nand"; 107 107 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 108 108 + interrupt-parent = <&gpmc>; 109 109 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 110 110 + <1 IRQ_TYPE_NONE>; /* termcount */ 106 111 linux,mtd-name= "micron,mt29f1g08abb"; 107 112 #address-cells = <1>; 108 113 #size-cells = <1>; 109 109 - reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ 110 114 ti,nand-ecc-opt = "sw"; 111 115 nand-bus-width = <8>; 112 116 gpmc,cs-on-ns = <0>;