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kernel
os
linux
xtensa: add MX irqchip
MX is an interrupt distributor used in some SMP-capable xtensa
configurations.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
authored by
Max Filippov
and committed by
Chris Zankel
26a8e96a
bae07f8a
+261
+1
arch/xtensa/include/asm/irq.h
+1
arch/xtensa/include/asm/irq.h
+46
arch/xtensa/include/asm/mxregs.h
+46
arch/xtensa/include/asm/mxregs.h
···
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/*
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* Xtensa MX interrupt distributor
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 - 2013 Tensilica Inc.
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*/
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#ifndef _XTENSA_MXREGS_H
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#define _XTENSA_MXREGS_H
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/*
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* RER/WER at, as Read/write external register
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* at: value
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* as: address
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*
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* Address Value
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* 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
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* 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
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* 0180 0...0m..m Clear enable specified by mask (m)
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* 0184 0...0m..m Set enable specified by mask (m)
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* 0190 0...0x..x 8-bit IPI partition register
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* VVVVVVVVPPPPUUUUUUUUUUUUUUUUU
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* V (10-bit) Release/Version
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* P ( 4-bit) Number of cores - 1
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* U (18-bit) ID
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* 01a0 i.......i 32-bit ConfigID
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* 0200 0...0m..m RunStall core 'n'
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* 0220 c Cache coherency enabled
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*/
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#define MIROUT(irq) (0x000 + (irq))
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#define MIPICAUSE(cpu) (0x100 + (cpu))
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#define MIPISET(cause) (0x140 + (cause))
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#define MIENG 0x180
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#define MIENGSET 0x184
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#define MIASG 0x188 /* Read Global Assert Register */
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#define MIASGSET 0x18c /* Set Global Addert Regiter */
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#define MIPIPART 0x190
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#define SYSCFGID 0x1a0
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#define MPSCORE 0x200
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#define CCON 0x220
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#endif /* _XTENSA_MXREGS_H */
+20
arch/xtensa/include/asm/processor.h
+20
arch/xtensa/include/asm/processor.h
···
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#define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
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#define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
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#ifndef XCHAL_HAVE_EXTERN_REGS
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#define XCHAL_HAVE_EXTERN_REGS 0
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#endif
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#if XCHAL_HAVE_EXTERN_REGS
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static inline void set_er(unsigned long value, unsigned long addr)
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{
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asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory");
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}
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static inline unsigned long get_er(unsigned long addr)
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{
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register unsigned long value;
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asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory");
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return value;
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}
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#endif /* XCHAL_HAVE_EXTERN_REGS */
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#endif /* __ASSEMBLY__ */
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#endif /* _XTENSA_PROCESSOR_H */
+8
arch/xtensa/kernel/irq.c
+8
arch/xtensa/kernel/irq.c
···
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return XCHAL_NUM_INTERRUPTS;
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}
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unsigned xtensa_get_ext_irq_no(unsigned irq)
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{
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unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL) &
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((1u << irq) - 1);
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return hweight32(mask);
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}
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void __init init_IRQ(void)
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{
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#ifdef CONFIG_OF
+4
drivers/irqchip/Kconfig
+4
drivers/irqchip/Kconfig
+1
drivers/irqchip/Makefile
+1
drivers/irqchip/Makefile
+164
drivers/irqchip/irq-xtensa-mx.c
+164
drivers/irqchip/irq-xtensa-mx.c
···
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/*
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* Xtensa MX interrupt distributor
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*
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* Copyright (C) 2002 - 2013 Tensilica, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <asm/mxregs.h>
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#include "irqchip.h"
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#define HW_IRQ_IPI_COUNT 2
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#define HW_IRQ_MX_BASE 2
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#define HW_IRQ_EXTERN_BASE 3
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static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
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static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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if (hw < HW_IRQ_IPI_COUNT) {
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struct irq_chip *irq_chip = d->host_data;
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_percpu_irq, "ipi");
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irq_set_status_flags(irq, IRQ_LEVEL);
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return 0;
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}
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return xtensa_irq_map(d, irq, hw);
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}
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/*
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* Device Tree IRQ specifier translation function which works with one or
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* two cell bindings. First cell value maps directly to the hwirq number.
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* Second cell if present specifies whether hwirq number is external (1) or
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* internal (0).
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*/
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static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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return xtensa_irq_domain_xlate(intspec, intsize,
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intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
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out_hwirq, out_type);
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}
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static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
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.xlate = xtensa_mx_irq_domain_xlate,
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.map = xtensa_mx_irq_map,
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};
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void secondary_init_irq(void)
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{
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__this_cpu_write(cached_irq_mask,
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XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
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set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
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}
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static void xtensa_mx_irq_mask(struct irq_data *d)
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{
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unsigned int mask = 1u << d->hwirq;
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if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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HW_IRQ_MX_BASE), MIENG);
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} else {
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mask = __this_cpu_read(cached_irq_mask) & ~mask;
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__this_cpu_write(cached_irq_mask, mask);
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set_sr(mask, intenable);
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}
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}
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static void xtensa_mx_irq_unmask(struct irq_data *d)
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{
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unsigned int mask = 1u << d->hwirq;
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if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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HW_IRQ_MX_BASE), MIENGSET);
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} else {
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mask |= __this_cpu_read(cached_irq_mask);
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__this_cpu_write(cached_irq_mask, mask);
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set_sr(mask, intenable);
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}
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}
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static void xtensa_mx_irq_enable(struct irq_data *d)
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{
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variant_irq_enable(d->hwirq);
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xtensa_mx_irq_unmask(d);
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}
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static void xtensa_mx_irq_disable(struct irq_data *d)
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{
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xtensa_mx_irq_mask(d);
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variant_irq_disable(d->hwirq);
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}
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static void xtensa_mx_irq_ack(struct irq_data *d)
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{
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set_sr(1 << d->hwirq, intclear);
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}
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static int xtensa_mx_irq_retrigger(struct irq_data *d)
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{
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set_sr(1 << d->hwirq, intset);
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return 1;
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}
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static int xtensa_mx_irq_set_affinity(struct irq_data *d,
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const struct cpumask *dest, bool force)
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{
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unsigned mask = 1u << cpumask_any(dest);
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set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
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return 0;
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}
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static struct irq_chip xtensa_mx_irq_chip = {
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.name = "xtensa-mx",
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.irq_enable = xtensa_mx_irq_enable,
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.irq_disable = xtensa_mx_irq_disable,
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.irq_mask = xtensa_mx_irq_mask,
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.irq_unmask = xtensa_mx_irq_unmask,
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.irq_ack = xtensa_mx_irq_ack,
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.irq_retrigger = xtensa_mx_irq_retrigger,
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.irq_set_affinity = xtensa_mx_irq_set_affinity,
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};
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int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
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{
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struct irq_domain *root_domain =
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irq_domain_add_legacy(NULL, NR_IRQS, 0, 0,
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&xtensa_mx_irq_domain_ops,
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&xtensa_mx_irq_chip);
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irq_set_default_host(root_domain);
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secondary_init_irq();
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return 0;
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}
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static int __init xtensa_mx_init(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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struct irq_domain *root_domain =
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irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
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&xtensa_mx_irq_chip);
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irq_set_default_host(root_domain);
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secondary_init_irq();
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return 0;
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}
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IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);
+17
include/linux/irqchip/xtensa-mx.h
+17
include/linux/irqchip/xtensa-mx.h
···
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/*
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* Xtensa MX interrupt distributor
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*
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* Copyright (C) 2002 - 2013 Tensilica, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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+
* for more details.
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*/
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#ifndef __LINUX_IRQCHIP_XTENSA_MX_H
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#define __LINUX_IRQCHIP_XTENSA_MX_H
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struct device_node;
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int xtensa_mx_init_legacy(struct device_node *interrupt_parent);
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#endif /* __LINUX_IRQCHIP_XTENSA_MX_H */