tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/nvd7/gr: initial support
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
authored by
Maarten Lankhorst
and committed by
Ben Skeggs
26410c67
a32b2ffb
+1930
-20
+2
drivers/gpu/drm/nouveau/Makefile
+2
drivers/gpu/drm/nouveau/Makefile
···
203
203
nouveau-y += core/engine/graph/ctxnvc1.o
204
204
nouveau-y += core/engine/graph/ctxnvc3.o
205
205
nouveau-y += core/engine/graph/ctxnvc8.o
206
+
nouveau-y += core/engine/graph/ctxnvd7.o
206
207
nouveau-y += core/engine/graph/ctxnvd9.o
207
208
nouveau-y += core/engine/graph/ctxnve4.o
208
209
nouveau-y += core/engine/graph/ctxnvf0.o
···
221
220
nouveau-y += core/engine/graph/nvc1.o
222
221
nouveau-y += core/engine/graph/nvc3.o
223
222
nouveau-y += core/engine/graph/nvc8.o
223
+
nouveau-y += core/engine/graph/nvd7.o
224
224
nouveau-y += core/engine/graph/nvd9.o
225
225
nouveau-y += core/engine/graph/nve4.o
226
226
nouveau-y += core/engine/graph/nvf0.o
+1
-1
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+1
-1
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
···
304
304
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
305
305
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
306
306
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
307
-
device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
307
+
device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
308
308
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
309
309
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
310
310
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
+303
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
+303
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
···
1
+
/*
2
+
* Copyright 2013 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: Ben Skeggs <bskeggs@redhat.com>
23
+
*/
24
+
25
+
#include "nvc0.h"
26
+
27
+
struct nvc0_graph_init
28
+
nvd7_grctx_init_unk40xx[] = {
29
+
{ 0x404004, 10, 0x04, 0x00000000 },
30
+
{ 0x404044, 1, 0x04, 0x00000000 },
31
+
{ 0x404094, 1, 0x04, 0x00000000 },
32
+
{ 0x404098, 12, 0x04, 0x00000000 },
33
+
{ 0x4040c8, 1, 0x04, 0xf0000087 },
34
+
{ 0x4040d0, 6, 0x04, 0x00000000 },
35
+
{ 0x4040e8, 1, 0x04, 0x00001000 },
36
+
{ 0x4040f8, 1, 0x04, 0x00000000 },
37
+
{ 0x404130, 1, 0x04, 0x00000000 },
38
+
{ 0x404134, 1, 0x04, 0x00000000 },
39
+
{ 0x404138, 1, 0x04, 0x20000040 },
40
+
{ 0x404150, 1, 0x04, 0x0000002e },
41
+
{ 0x404154, 1, 0x04, 0x00000400 },
42
+
{ 0x404158, 1, 0x04, 0x00000200 },
43
+
{ 0x404164, 1, 0x04, 0x00000055 },
44
+
{ 0x404168, 1, 0x04, 0x00000000 },
45
+
{ 0x404178, 2, 0x04, 0x00000000 },
46
+
{ 0x404200, 8, 0x04, 0x00000000 },
47
+
{}
48
+
};
49
+
50
+
static struct nvc0_graph_init
51
+
nvd7_grctx_init_unk58xx[] = {
52
+
{ 0x405800, 1, 0x04, 0x0f8000bf },
53
+
{ 0x405830, 1, 0x04, 0x02180324 },
54
+
{ 0x405834, 1, 0x04, 0x08000000 },
55
+
{ 0x405838, 1, 0x04, 0x00000000 },
56
+
{ 0x405854, 1, 0x04, 0x00000000 },
57
+
{ 0x405870, 4, 0x04, 0x00000001 },
58
+
{ 0x405a00, 2, 0x04, 0x00000000 },
59
+
{ 0x405a18, 1, 0x04, 0x00000000 },
60
+
{}
61
+
};
62
+
63
+
static struct nvc0_graph_init
64
+
nvd7_grctx_init_unk64xx[] = {
65
+
{ 0x4064a8, 1, 0x04, 0x00000000 },
66
+
{ 0x4064ac, 1, 0x04, 0x00003fff },
67
+
{ 0x4064b4, 3, 0x04, 0x00000000 },
68
+
{ 0x4064c0, 1, 0x04, 0x801a0078 },
69
+
{ 0x4064c4, 1, 0x04, 0x00c9ffff },
70
+
{ 0x4064d0, 8, 0x04, 0x00000000 },
71
+
{}
72
+
};
73
+
74
+
static struct nvc0_graph_init
75
+
nvd7_grctx_init_gpc_0[] = {
76
+
{ 0x418380, 1, 0x04, 0x00000016 },
77
+
{ 0x418400, 1, 0x04, 0x38004e00 },
78
+
{ 0x418404, 1, 0x04, 0x71e0ffff },
79
+
{ 0x41840c, 1, 0x04, 0x00001008 },
80
+
{ 0x418410, 1, 0x04, 0x0fff0fff },
81
+
{ 0x418414, 1, 0x04, 0x02200fff },
82
+
{ 0x418450, 6, 0x04, 0x00000000 },
83
+
{ 0x418468, 1, 0x04, 0x00000001 },
84
+
{ 0x41846c, 2, 0x04, 0x00000000 },
85
+
{ 0x418600, 1, 0x04, 0x0000001f },
86
+
{ 0x418684, 1, 0x04, 0x0000000f },
87
+
{ 0x418700, 1, 0x04, 0x00000002 },
88
+
{ 0x418704, 1, 0x04, 0x00000080 },
89
+
{ 0x418708, 3, 0x04, 0x00000000 },
90
+
{ 0x418800, 1, 0x04, 0x7006860a },
91
+
{ 0x418808, 3, 0x04, 0x00000000 },
92
+
{ 0x418828, 1, 0x04, 0x00008442 },
93
+
{ 0x418830, 1, 0x04, 0x10000001 },
94
+
{ 0x4188d8, 1, 0x04, 0x00000008 },
95
+
{ 0x4188e0, 1, 0x04, 0x01000000 },
96
+
{ 0x4188e8, 5, 0x04, 0x00000000 },
97
+
{ 0x4188fc, 1, 0x04, 0x20100018 },
98
+
{ 0x41891c, 1, 0x04, 0x00ff00ff },
99
+
{ 0x418924, 1, 0x04, 0x00000000 },
100
+
{ 0x418928, 1, 0x04, 0x00ffff00 },
101
+
{ 0x41892c, 1, 0x04, 0x0000ff00 },
102
+
{ 0x418b00, 1, 0x04, 0x00000006 },
103
+
{ 0x418b08, 1, 0x04, 0x0a418820 },
104
+
{ 0x418b0c, 1, 0x04, 0x062080e6 },
105
+
{ 0x418b10, 1, 0x04, 0x020398a4 },
106
+
{ 0x418b14, 1, 0x04, 0x0e629062 },
107
+
{ 0x418b18, 1, 0x04, 0x0a418820 },
108
+
{ 0x418b1c, 1, 0x04, 0x000000e6 },
109
+
{ 0x418bb8, 1, 0x04, 0x00000103 },
110
+
{ 0x418c08, 1, 0x04, 0x00000001 },
111
+
{ 0x418c10, 8, 0x04, 0x00000000 },
112
+
{ 0x418c6c, 1, 0x04, 0x00000001 },
113
+
{ 0x418c80, 1, 0x04, 0x20200004 },
114
+
{ 0x418c8c, 1, 0x04, 0x00000001 },
115
+
{ 0x419000, 1, 0x04, 0x00000780 },
116
+
{ 0x419004, 2, 0x04, 0x00000000 },
117
+
{ 0x419014, 1, 0x04, 0x00000004 },
118
+
{}
119
+
};
120
+
121
+
static struct nvc0_graph_init
122
+
nvd7_grctx_init_tpc[] = {
123
+
{ 0x419848, 1, 0x04, 0x00000000 },
124
+
{ 0x419864, 1, 0x04, 0x00000129 },
125
+
{ 0x419888, 1, 0x04, 0x00000000 },
126
+
{ 0x419a00, 1, 0x04, 0x000001f0 },
127
+
{ 0x419a04, 1, 0x04, 0x00000001 },
128
+
{ 0x419a08, 1, 0x04, 0x00000023 },
129
+
{ 0x419a0c, 1, 0x04, 0x00020000 },
130
+
{ 0x419a10, 1, 0x04, 0x00000000 },
131
+
{ 0x419a14, 1, 0x04, 0x00000200 },
132
+
{ 0x419a1c, 1, 0x04, 0x00008000 },
133
+
{ 0x419a20, 1, 0x04, 0x00000800 },
134
+
{ 0x419ac4, 1, 0x04, 0x0017f440 },
135
+
{ 0x419c00, 1, 0x04, 0x0000000a },
136
+
{ 0x419c04, 1, 0x04, 0x00000006 },
137
+
{ 0x419c08, 1, 0x04, 0x00000002 },
138
+
{ 0x419c20, 1, 0x04, 0x00000000 },
139
+
{ 0x419c24, 1, 0x04, 0x00084210 },
140
+
{ 0x419c28, 1, 0x04, 0x3efbefbe },
141
+
{ 0x419cb0, 1, 0x04, 0x00020048 },
142
+
{ 0x419ce8, 1, 0x04, 0x00000000 },
143
+
{ 0x419cf4, 1, 0x04, 0x00000183 },
144
+
{ 0x419e04, 3, 0x04, 0x00000000 },
145
+
{ 0x419e10, 1, 0x04, 0x00000002 },
146
+
{ 0x419e44, 1, 0x04, 0x001beff2 },
147
+
{ 0x419e48, 1, 0x04, 0x00000000 },
148
+
{ 0x419e4c, 1, 0x04, 0x0000000f },
149
+
{ 0x419e50, 17, 0x04, 0x00000000 },
150
+
{ 0x419e98, 1, 0x04, 0x00000000 },
151
+
{ 0x419ee0, 1, 0x04, 0x00010110 },
152
+
{ 0x419f30, 11, 0x04, 0x00000000 },
153
+
{}
154
+
};
155
+
156
+
static struct nvc0_graph_init
157
+
nvd7_grctx_init_unk[] = {
158
+
{ 0x41be24, 1, 0x04, 0x00000002 },
159
+
{ 0x41bec0, 1, 0x04, 0x12180000 },
160
+
{ 0x41bec4, 1, 0x04, 0x00003fff },
161
+
{ 0x41bee4, 1, 0x04, 0x03240218 },
162
+
{ 0x41bf00, 1, 0x04, 0x0a418820 },
163
+
{ 0x41bf04, 1, 0x04, 0x062080e6 },
164
+
{ 0x41bf08, 1, 0x04, 0x020398a4 },
165
+
{ 0x41bf0c, 1, 0x04, 0x0e629062 },
166
+
{ 0x41bf10, 1, 0x04, 0x0a418820 },
167
+
{ 0x41bf14, 1, 0x04, 0x000000e6 },
168
+
{ 0x41bfd0, 1, 0x04, 0x00900103 },
169
+
{ 0x41bfe0, 1, 0x04, 0x00400001 },
170
+
{ 0x41bfe4, 1, 0x04, 0x00000000 },
171
+
{}
172
+
};
173
+
174
+
static void
175
+
nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
176
+
{
177
+
u32 magic[GPC_MAX][2];
178
+
u32 offset;
179
+
int gpc;
180
+
181
+
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
182
+
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
183
+
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
184
+
mmio_list(0x40800c, 0x00000000, 8, 1);
185
+
mmio_list(0x408010, 0x80000000, 0, 0);
186
+
mmio_list(0x419004, 0x00000000, 8, 1);
187
+
mmio_list(0x419008, 0x00000000, 0, 0);
188
+
mmio_list(0x408004, 0x00000000, 8, 0);
189
+
mmio_list(0x408008, 0x80000018, 0, 0);
190
+
mmio_list(0x418808, 0x00000000, 8, 0);
191
+
mmio_list(0x41880c, 0x80000018, 0, 0);
192
+
mmio_list(0x418810, 0x80000000, 12, 2);
193
+
mmio_list(0x419848, 0x10000000, 12, 2);
194
+
195
+
mmio_list(0x405830, 0x02180324, 0, 0);
196
+
mmio_list(0x4064c4, 0x00c9ffff, 0, 0);
197
+
198
+
for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
199
+
u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
200
+
u16 magic1 = 0x0324 * priv->tpc_nr[gpc];
201
+
magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
202
+
magic[gpc][1] = 0x00000000 | (magic1 << 16);
203
+
offset += 0x0324 * priv->tpc_nr[gpc];
204
+
}
205
+
206
+
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
207
+
mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
208
+
mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
209
+
offset += 0x07ff * priv->tpc_nr[gpc];
210
+
}
211
+
mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
212
+
}
213
+
214
+
void
215
+
nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
216
+
{
217
+
struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
218
+
int i;
219
+
220
+
nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
221
+
222
+
for (i = 0; oclass->hub[i]; i++)
223
+
nvc0_graph_mmio(priv, oclass->hub[i]);
224
+
for (i = 0; oclass->gpc[i]; i++)
225
+
nvc0_graph_mmio(priv, oclass->gpc[i]);
226
+
227
+
nv_wr32(priv, 0x404154, 0x00000000);
228
+
229
+
oclass->mods(priv, info);
230
+
231
+
nv_wr32(priv, 0x418c6c, 0x1);
232
+
nv_wr32(priv, 0x41980c, 0x10);
233
+
nv_wr32(priv, 0x41be08, 0x4);
234
+
nv_wr32(priv, 0x4064c0, 0x801a0078);
235
+
nv_wr32(priv, 0x405800, 0xf8000bf);
236
+
nv_wr32(priv, 0x419c00, 0xa);
237
+
238
+
nvc0_grctx_generate_tpcid(priv);
239
+
nvc0_grctx_generate_r406028(priv);
240
+
241
+
nv_wr32(priv, 0x40602c, 0x00000000);
242
+
nv_wr32(priv, 0x405874, 0x00000000);
243
+
nv_wr32(priv, 0x406030, 0x00000000);
244
+
nv_wr32(priv, 0x405878, 0x00000000);
245
+
nv_wr32(priv, 0x406034, 0x00000000);
246
+
nv_wr32(priv, 0x40587c, 0x00000000);
247
+
248
+
nvc0_grctx_generate_r4060a8(priv);
249
+
nve4_grctx_generate_r418bb8(priv);
250
+
nvc0_grctx_generate_r406800(priv);
251
+
252
+
for (i = 0; i < 8; i++)
253
+
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
254
+
255
+
nvc0_graph_icmd(priv, oclass->icmd);
256
+
nv_wr32(priv, 0x404154, 0x00000400);
257
+
nvc0_graph_mthd(priv, oclass->mthd);
258
+
nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
259
+
}
260
+
261
+
262
+
static struct nvc0_graph_init *
263
+
nvd7_grctx_init_hub[] = {
264
+
nvc0_grctx_init_base,
265
+
nvd7_grctx_init_unk40xx,
266
+
nvc0_grctx_init_unk44xx,
267
+
nvc0_grctx_init_unk46xx,
268
+
nvc0_grctx_init_unk47xx,
269
+
nvd7_grctx_init_unk58xx,
270
+
nvc0_grctx_init_unk60xx,
271
+
nvd7_grctx_init_unk64xx,
272
+
nvc0_grctx_init_unk78xx,
273
+
nvc0_grctx_init_unk80xx,
274
+
nvd9_grctx_init_rop,
275
+
};
276
+
277
+
struct nvc0_graph_init *
278
+
nvd7_grctx_init_gpc[] = {
279
+
nvd7_grctx_init_gpc_0,
280
+
nvc0_grctx_init_gpc_1,
281
+
nvd7_grctx_init_tpc,
282
+
nvd7_grctx_init_unk,
283
+
NULL
284
+
};
285
+
286
+
struct nouveau_oclass *
287
+
nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
288
+
.base.handle = NV_ENGCTX(GR, 0xd7),
289
+
.base.ofuncs = &(struct nouveau_ofuncs) {
290
+
.ctor = nvc0_graph_context_ctor,
291
+
.dtor = nvc0_graph_context_dtor,
292
+
.init = _nouveau_graph_context_init,
293
+
.fini = _nouveau_graph_context_fini,
294
+
.rd32 = _nouveau_graph_context_rd32,
295
+
.wr32 = _nouveau_graph_context_wr32,
296
+
},
297
+
.main = nvd7_grctx_generate_main,
298
+
.mods = nvd7_grctx_generate_mods,
299
+
.hub = nvd7_grctx_init_hub,
300
+
.gpc = nvd7_grctx_init_gpc,
301
+
.icmd = nvd9_grctx_init_icmd,
302
+
.mthd = nvd9_grctx_init_mthd,
303
+
}.base;
+3
-3
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+3
-3
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
···
41
41
tpc_count: .b32 0
42
42
tpc_mask: .b32 0
43
43
44
-
#ifdef NVGK
44
+
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
45
45
unk_count: .b32 1
46
46
unk_mask: .b32 1
47
47
#endif
···
145
145
add b32 $r2 $r14
146
146
add b32 $r3 $r14
147
147
148
-
#ifdef NVGK
148
+
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
149
149
// calculate per-UNK mmio context size
150
150
ld b32 $r14 D[$r0 + #unk_mmio_list_head]
151
151
ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
···
342
342
mov $r14 0x800 // stride = 0x800
343
343
call #mmctx_xfer
344
344
345
-
#ifdef NVGK
345
+
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
346
346
// per-UNK mmio context
347
347
xbit $r10 $flags $p1 // direction
348
348
or $r10 4 // last
+3
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+3
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+42
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
+42
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
···
1
+
/*
2
+
* Copyright 2013 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: Ben Skeggs <bskeggs@redhat.com>
23
+
*/
24
+
25
+
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001
26
+
27
+
#define CHIPSET GF117
28
+
#include "macros.fuc"
29
+
30
+
.section #nvd7_grgpc_data
31
+
#define INCLUDE_DATA
32
+
#include "com.fuc"
33
+
#include "gpc.fuc"
34
+
#undef INCLUDE_DATA
35
+
36
+
.section #nvd7_grgpc_code
37
+
#define INCLUDE_CODE
38
+
bra #init
39
+
#include "com.fuc"
40
+
#include "gpc.fuc"
41
+
.align 256
42
+
#undef INCLUDE_CODE
+472
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
+472
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
···
1
+
uint32_t nvd7_grgpc_data[] = {
2
+
/* 0x0000: gpc_mmio_list_head */
3
+
0x0000006c,
4
+
/* 0x0004: gpc_mmio_list_tail */
5
+
/* 0x0004: tpc_mmio_list_head */
6
+
0x0000006c,
7
+
/* 0x0008: tpc_mmio_list_tail */
8
+
/* 0x0008: unk_mmio_list_head */
9
+
0x0000006c,
10
+
/* 0x000c: unk_mmio_list_tail */
11
+
0x0000006c,
12
+
/* 0x0010: gpc_id */
13
+
0x00000000,
14
+
/* 0x0014: tpc_count */
15
+
0x00000000,
16
+
/* 0x0018: tpc_mask */
17
+
0x00000000,
18
+
/* 0x001c: unk_count */
19
+
0x00000001,
20
+
/* 0x0020: unk_mask */
21
+
0x00000001,
22
+
/* 0x0024: cmd_queue */
23
+
0x00000000,
24
+
0x00000000,
25
+
0x00000000,
26
+
0x00000000,
27
+
0x00000000,
28
+
0x00000000,
29
+
0x00000000,
30
+
0x00000000,
31
+
0x00000000,
32
+
0x00000000,
33
+
0x00000000,
34
+
0x00000000,
35
+
0x00000000,
36
+
0x00000000,
37
+
0x00000000,
38
+
0x00000000,
39
+
0x00000000,
40
+
0x00000000,
41
+
};
42
+
43
+
uint32_t nvd7_grgpc_code[] = {
44
+
0x03060ef5,
45
+
/* 0x0004: queue_put */
46
+
0x9800d898,
47
+
0x86f001d9,
48
+
0x0489b808,
49
+
0xf00c1bf4,
50
+
0x21f502f7,
51
+
0x00f802ec,
52
+
/* 0x001c: queue_put_next */
53
+
0xb60798c4,
54
+
0x8dbb0384,
55
+
0x0880b600,
56
+
0x80008e80,
57
+
0x90b6018f,
58
+
0x0f94f001,
59
+
0xf801d980,
60
+
/* 0x0039: queue_get */
61
+
0x0131f400,
62
+
0x9800d898,
63
+
0x89b801d9,
64
+
0x210bf404,
65
+
0xb60789c4,
66
+
0x9dbb0394,
67
+
0x0890b600,
68
+
0x98009e98,
69
+
0x80b6019f,
70
+
0x0f84f001,
71
+
0xf400d880,
72
+
/* 0x0066: queue_get_done */
73
+
0x00f80132,
74
+
/* 0x0068: nv_rd32 */
75
+
0x0728b7f1,
76
+
0xb906b4b6,
77
+
0xc9f002ec,
78
+
0x00bcd01f,
79
+
/* 0x0078: nv_rd32_wait */
80
+
0xc800bccf,
81
+
0x1bf41fcc,
82
+
0x06a7f0fa,
83
+
0x010321f5,
84
+
0xf840bfcf,
85
+
/* 0x008d: nv_wr32 */
86
+
0x28b7f100,
87
+
0x06b4b607,
88
+
0xb980bfd0,
89
+
0xc9f002ec,
90
+
0x1ec9f01f,
91
+
/* 0x00a3: nv_wr32_wait */
92
+
0xcf00bcd0,
93
+
0xccc800bc,
94
+
0xfa1bf41f,
95
+
/* 0x00ae: watchdog_reset */
96
+
0x87f100f8,
97
+
0x84b60430,
98
+
0x1ff9f006,
99
+
0xf8008fd0,
100
+
/* 0x00bd: watchdog_clear */
101
+
0x3087f100,
102
+
0x0684b604,
103
+
0xf80080d0,
104
+
/* 0x00c9: wait_donez */
105
+
0x3c87f100,
106
+
0x0684b608,
107
+
0x99f094bd,
108
+
0x0089d000,
109
+
0x081887f1,
110
+
0xd00684b6,
111
+
/* 0x00e2: wait_donez_ne */
112
+
0x87f1008a,
113
+
0x84b60400,
114
+
0x0088cf06,
115
+
0xf4888aff,
116
+
0x87f1f31b,
117
+
0x84b6085c,
118
+
0xf094bd06,
119
+
0x89d00099,
120
+
/* 0x0103: wait_doneo */
121
+
0xf100f800,
122
+
0xb6083c87,
123
+
0x94bd0684,
124
+
0xd00099f0,
125
+
0x87f10089,
126
+
0x84b60818,
127
+
0x008ad006,
128
+
/* 0x011c: wait_doneo_e */
129
+
0x040087f1,
130
+
0xcf0684b6,
131
+
0x8aff0088,
132
+
0xf30bf488,
133
+
0x085c87f1,
134
+
0xbd0684b6,
135
+
0x0099f094,
136
+
0xf80089d0,
137
+
/* 0x013d: mmctx_size */
138
+
/* 0x013f: nv_mmctx_size_loop */
139
+
0x9894bd00,
140
+
0x85b600e8,
141
+
0x0180b61a,
142
+
0xbb0284b6,
143
+
0xe0b60098,
144
+
0x04efb804,
145
+
0xb9eb1bf4,
146
+
0x00f8029f,
147
+
/* 0x015c: mmctx_xfer */
148
+
0x083c87f1,
149
+
0xbd0684b6,
150
+
0x0199f094,
151
+
0xf10089d0,
152
+
0xb6071087,
153
+
0x94bd0684,
154
+
0xf405bbfd,
155
+
0x8bd0090b,
156
+
0x0099f000,
157
+
/* 0x0180: mmctx_base_disabled */
158
+
0xf405eefd,
159
+
0x8ed00c0b,
160
+
0xc08fd080,
161
+
/* 0x018f: mmctx_multi_disabled */
162
+
0xb70199f0,
163
+
0xc8010080,
164
+
0xb4b600ab,
165
+
0x0cb9f010,
166
+
0xb601aec8,
167
+
0xbefd11e4,
168
+
0x008bd005,
169
+
/* 0x01a8: mmctx_exec_loop */
170
+
/* 0x01a8: mmctx_wait_free */
171
+
0xf0008ecf,
172
+
0x0bf41fe4,
173
+
0x00ce98fa,
174
+
0xd005e9fd,
175
+
0xc0b6c08e,
176
+
0x04cdb804,
177
+
0xc8e81bf4,
178
+
0x1bf402ab,
179
+
/* 0x01c9: mmctx_fini_wait */
180
+
0x008bcf18,
181
+
0xb01fb4f0,
182
+
0x1bf410b4,
183
+
0x02a7f0f7,
184
+
0xf4c921f4,
185
+
/* 0x01de: mmctx_stop */
186
+
0xabc81b0e,
187
+
0x10b4b600,
188
+
0xf00cb9f0,
189
+
0x8bd012b9,
190
+
/* 0x01ed: mmctx_stop_wait */
191
+
0x008bcf00,
192
+
0xf412bbc8,
193
+
/* 0x01f6: mmctx_done */
194
+
0x87f1fa1b,
195
+
0x84b6085c,
196
+
0xf094bd06,
197
+
0x89d00199,
198
+
/* 0x0207: strand_wait */
199
+
0xf900f800,
200
+
0x02a7f0a0,
201
+
0xfcc921f4,
202
+
/* 0x0213: strand_pre */
203
+
0xf100f8a0,
204
+
0xf04afc87,
205
+
0x97f00283,
206
+
0x0089d00c,
207
+
0x020721f5,
208
+
/* 0x0226: strand_post */
209
+
0x87f100f8,
210
+
0x83f04afc,
211
+
0x0d97f002,
212
+
0xf50089d0,
213
+
0xf8020721,
214
+
/* 0x0239: strand_set */
215
+
0xfca7f100,
216
+
0x02a3f04f,
217
+
0x0500aba2,
218
+
0xd00fc7f0,
219
+
0xc7f000ac,
220
+
0x00bcd00b,
221
+
0x020721f5,
222
+
0xf000aed0,
223
+
0xbcd00ac7,
224
+
0x0721f500,
225
+
/* 0x0263: strand_ctx_init */
226
+
0xf100f802,
227
+
0xb6083c87,
228
+
0x94bd0684,
229
+
0xd00399f0,
230
+
0x21f50089,
231
+
0xe7f00213,
232
+
0x3921f503,
233
+
0xfca7f102,
234
+
0x02a3f046,
235
+
0x0400aba0,
236
+
0xf040a0d0,
237
+
0xbcd001c7,
238
+
0x0721f500,
239
+
0x010c9202,
240
+
0xf000acd0,
241
+
0xbcd002c7,
242
+
0x0721f500,
243
+
0x2621f502,
244
+
0x8087f102,
245
+
0x0684b608,
246
+
0xb70089cf,
247
+
0x95220080,
248
+
/* 0x02ba: ctx_init_strand_loop */
249
+
0x8ed008fe,
250
+
0x408ed000,
251
+
0xb6808acf,
252
+
0xa0b606a5,
253
+
0x00eabb01,
254
+
0xb60480b6,
255
+
0x1bf40192,
256
+
0x08e4b6e8,
257
+
0xf1f2efbc,
258
+
0xb6085c87,
259
+
0x94bd0684,
260
+
0xd00399f0,
261
+
0x00f80089,
262
+
/* 0x02ec: error */
263
+
0xe7f1e0f9,
264
+
0xe3f09814,
265
+
0x8d21f440,
266
+
0x041ce0b7,
267
+
0xf401f7f0,
268
+
0xe0fc8d21,
269
+
/* 0x0306: init */
270
+
0x04bd00f8,
271
+
0xf10004fe,
272
+
0xf0120017,
273
+
0x12d00227,
274
+
0x2317f100,
275
+
0x0010fe04,
276
+
0x040017f1,
277
+
0xf0c010d0,
278
+
0x12d00427,
279
+
0x1031f400,
280
+
0x060817f1,
281
+
0xcf0614b6,
282
+
0x37f00012,
283
+
0x1f24f001,
284
+
0xb60432bb,
285
+
0x02800132,
286
+
0x06038005,
287
+
0x040010b7,
288
+
0x800012cf,
289
+
0x27f10402,
290
+
0x24b60800,
291
+
0x4022cf06,
292
+
0x47f134bd,
293
+
0x44b60700,
294
+
0x08259506,
295
+
0xd00045d0,
296
+
0x0e984045,
297
+
0x010f9800,
298
+
0x013d21f5,
299
+
0xbb002fbb,
300
+
0x0e98003f,
301
+
0x020f9801,
302
+
0x013d21f5,
303
+
0xfd050e98,
304
+
0x2ebb00ef,
305
+
0x003ebb00,
306
+
0x98020e98,
307
+
0x21f5030f,
308
+
0x0e98013d,
309
+
0x00effd07,
310
+
0xbb002ebb,
311
+
0x40b7003e,
312
+
0x35b61300,
313
+
0x0043d002,
314
+
0xb60825b6,
315
+
0x20b60635,
316
+
0x0130b601,
317
+
0xb60824b6,
318
+
0x2fb90834,
319
+
0x6321f502,
320
+
0x003fbb02,
321
+
0x080017f1,
322
+
0xd00614b6,
323
+
0x10b74013,
324
+
0x24bd0800,
325
+
0xd01f29f0,
326
+
/* 0x03e6: main */
327
+
0x31f40012,
328
+
0x0028f400,
329
+
0xf424d7f0,
330
+
0x01f43921,
331
+
0x04e4b0f4,
332
+
0xfe1e18f4,
333
+
0x27f00181,
334
+
0xfd20bd06,
335
+
0xe4b60412,
336
+
0x051efd01,
337
+
0xf50018fe,
338
+
0xf404a821,
339
+
/* 0x0416: main_not_ctx_xfer */
340
+
0xef94d30e,
341
+
0x01f5f010,
342
+
0x02ec21f5,
343
+
/* 0x0423: ih */
344
+
0xf9c60ef4,
345
+
0x0188fe80,
346
+
0x90f980f9,
347
+
0xb0f9a0f9,
348
+
0xe0f9d0f9,
349
+
0x0acff0f9,
350
+
0x04abc480,
351
+
0xf11d0bf4,
352
+
0xf01900b7,
353
+
0xbecf24d7,
354
+
0x00bfcf40,
355
+
0xb70421f4,
356
+
0xf00400b0,
357
+
0xbed001e7,
358
+
/* 0x0459: ih_no_fifo */
359
+
0x400ad000,
360
+
0xe0fcf0fc,
361
+
0xb0fcd0fc,
362
+
0x90fca0fc,
363
+
0x88fe80fc,
364
+
0xf480fc00,
365
+
0x01f80032,
366
+
/* 0x0474: hub_barrier_done */
367
+
0x9801f7f0,
368
+
0xfebb040e,
369
+
0x18e7f104,
370
+
0x40e3f094,
371
+
0xf88d21f4,
372
+
/* 0x0489: ctx_redswitch */
373
+
0x14e7f100,
374
+
0x06e4b606,
375
+
0xd020f7f0,
376
+
0xf7f000ef,
377
+
/* 0x0499: ctx_redswitch_delay */
378
+
0x01f2b608,
379
+
0xf1fd1bf4,
380
+
0xd00a20f7,
381
+
0x00f800ef,
382
+
/* 0x04a8: ctx_xfer */
383
+
0x0a0417f1,
384
+
0xd00614b6,
385
+
0x11f4001f,
386
+
0x8921f507,
387
+
/* 0x04b9: ctx_xfer_not_load */
388
+
0xfc17f104,
389
+
0x0213f04a,
390
+
0xd00c27f0,
391
+
0x21f50012,
392
+
0x27f10207,
393
+
0x23f047fc,
394
+
0x0020d002,
395
+
0xb6012cf0,
396
+
0x12d00320,
397
+
0x01acf000,
398
+
0xf002a5f0,
399
+
0xb3f000b7,
400
+
0x040c9850,
401
+
0xbb0fc4b6,
402
+
0x0c9800bc,
403
+
0x010d9800,
404
+
0xf500e7f0,
405
+
0xf0015c21,
406
+
0xb7f101ac,
407
+
0xb3f04000,
408
+
0x040c9850,
409
+
0xbb0fc4b6,
410
+
0x0c9800bc,
411
+
0x020d9801,
412
+
0xf1060f98,
413
+
0xf50800e7,
414
+
0xf0015c21,
415
+
0xa5f001ac,
416
+
0x00b7f104,
417
+
0x50b3f030,
418
+
0xb6040c98,
419
+
0xbcbb0fc4,
420
+
0x020c9800,
421
+
0x98030d98,
422
+
0xe7f1080f,
423
+
0x21f50200,
424
+
0x21f5015c,
425
+
0x01f40207,
426
+
0x1412f406,
427
+
/* 0x0554: ctx_xfer_post */
428
+
0x4afc17f1,
429
+
0xf00213f0,
430
+
0x12d00d27,
431
+
0x0721f500,
432
+
/* 0x0565: ctx_xfer_done */
433
+
0x7421f502,
434
+
0x0000f804,
435
+
0x00000000,
436
+
0x00000000,
437
+
0x00000000,
438
+
0x00000000,
439
+
0x00000000,
440
+
0x00000000,
441
+
0x00000000,
442
+
0x00000000,
443
+
0x00000000,
444
+
0x00000000,
445
+
0x00000000,
446
+
0x00000000,
447
+
0x00000000,
448
+
0x00000000,
449
+
0x00000000,
450
+
0x00000000,
451
+
0x00000000,
452
+
0x00000000,
453
+
0x00000000,
454
+
0x00000000,
455
+
0x00000000,
456
+
0x00000000,
457
+
0x00000000,
458
+
0x00000000,
459
+
0x00000000,
460
+
0x00000000,
461
+
0x00000000,
462
+
0x00000000,
463
+
0x00000000,
464
+
0x00000000,
465
+
0x00000000,
466
+
0x00000000,
467
+
0x00000000,
468
+
0x00000000,
469
+
0x00000000,
470
+
0x00000000,
471
+
0x00000000,
472
+
};
+3
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+3
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+5
-5
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
+5
-5
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
···
377
377
bclr $flags $p0
378
378
iret
379
379
380
-
#ifdef NVGF
380
+
#if CHIPSET < GK100
381
381
// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
382
382
ctx_4160s:
383
383
mov $r14 0x4160
···
541
541
// In: $r2 channel address
542
542
//
543
543
ctx_chan:
544
-
#ifdef NVGF
544
+
#if CHIPSET < GK100
545
545
call #ctx_4160s
546
546
#endif
547
547
call #ctx_load
···
555
555
iord $r2 I[$r1 + 0x000]
556
556
or $r2 $r2
557
557
bra ne #ctx_chan_wait
558
-
#ifdef NVGF
558
+
#if CHIPSET < GK100
559
559
call #ctx_4160c
560
560
#endif
561
561
ret
···
634
634
ctx_xfer_pre:
635
635
mov $r15 0x10
636
636
call #ctx_86c
637
-
#ifdef NVGF
637
+
#if CHIPSET < GK100
638
638
call #ctx_4160s
639
639
#endif
640
640
bra not $p1 #ctx_xfer_exec
···
725
725
call #ctx_mmio_exec
726
726
727
727
ctx_xfer_no_post_mmio:
728
-
#ifdef NVGF
728
+
#if CHIPSET < GK100
729
729
call #ctx_4160c
730
730
#endif
731
731
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+40
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
+40
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
···
1
+
/*
2
+
* Copyright 2013 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: Ben Skeggs <bskeggs@redhat.com>
23
+
*/
24
+
25
+
#define CHIPSET GF117
26
+
#include "macros.fuc"
27
+
28
+
.section #nvd7_grhub_data
29
+
#define INCLUDE_DATA
30
+
#include "com.fuc"
31
+
#include "hub.fuc"
32
+
#undef INCLUDE_DATA
33
+
34
+
.section #nvd7_grhub_code
35
+
#define INCLUDE_CODE
36
+
bra #init
37
+
#include "com.fuc"
38
+
#include "hub.fuc"
39
+
.align 256
40
+
#undef INCLUDE_CODE
+857
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
+857
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
···
1
+
uint32_t nvd7_grhub_data[] = {
2
+
/* 0x0000: hub_mmio_list_head */
3
+
0x00000300,
4
+
/* 0x0004: hub_mmio_list_tail */
5
+
0x00000304,
6
+
/* 0x0008: gpc_count */
7
+
0x00000000,
8
+
/* 0x000c: rop_count */
9
+
0x00000000,
10
+
/* 0x0010: cmd_queue */
11
+
0x00000000,
12
+
0x00000000,
13
+
0x00000000,
14
+
0x00000000,
15
+
0x00000000,
16
+
0x00000000,
17
+
0x00000000,
18
+
0x00000000,
19
+
0x00000000,
20
+
0x00000000,
21
+
0x00000000,
22
+
0x00000000,
23
+
0x00000000,
24
+
0x00000000,
25
+
0x00000000,
26
+
0x00000000,
27
+
0x00000000,
28
+
0x00000000,
29
+
/* 0x0058: ctx_current */
30
+
0x00000000,
31
+
0x00000000,
32
+
0x00000000,
33
+
0x00000000,
34
+
0x00000000,
35
+
0x00000000,
36
+
0x00000000,
37
+
0x00000000,
38
+
0x00000000,
39
+
0x00000000,
40
+
0x00000000,
41
+
0x00000000,
42
+
0x00000000,
43
+
0x00000000,
44
+
0x00000000,
45
+
0x00000000,
46
+
0x00000000,
47
+
0x00000000,
48
+
0x00000000,
49
+
0x00000000,
50
+
0x00000000,
51
+
0x00000000,
52
+
0x00000000,
53
+
0x00000000,
54
+
0x00000000,
55
+
0x00000000,
56
+
0x00000000,
57
+
0x00000000,
58
+
0x00000000,
59
+
0x00000000,
60
+
0x00000000,
61
+
0x00000000,
62
+
0x00000000,
63
+
0x00000000,
64
+
0x00000000,
65
+
0x00000000,
66
+
0x00000000,
67
+
0x00000000,
68
+
0x00000000,
69
+
0x00000000,
70
+
0x00000000,
71
+
0x00000000,
72
+
/* 0x0100: chan_data */
73
+
/* 0x0100: chan_mmio_count */
74
+
0x00000000,
75
+
/* 0x0104: chan_mmio_address */
76
+
0x00000000,
77
+
0x00000000,
78
+
0x00000000,
79
+
0x00000000,
80
+
0x00000000,
81
+
0x00000000,
82
+
0x00000000,
83
+
0x00000000,
84
+
0x00000000,
85
+
0x00000000,
86
+
0x00000000,
87
+
0x00000000,
88
+
0x00000000,
89
+
0x00000000,
90
+
0x00000000,
91
+
0x00000000,
92
+
0x00000000,
93
+
0x00000000,
94
+
0x00000000,
95
+
0x00000000,
96
+
0x00000000,
97
+
0x00000000,
98
+
0x00000000,
99
+
0x00000000,
100
+
0x00000000,
101
+
0x00000000,
102
+
0x00000000,
103
+
0x00000000,
104
+
0x00000000,
105
+
0x00000000,
106
+
0x00000000,
107
+
0x00000000,
108
+
0x00000000,
109
+
0x00000000,
110
+
0x00000000,
111
+
0x00000000,
112
+
0x00000000,
113
+
0x00000000,
114
+
0x00000000,
115
+
0x00000000,
116
+
0x00000000,
117
+
0x00000000,
118
+
0x00000000,
119
+
0x00000000,
120
+
0x00000000,
121
+
0x00000000,
122
+
0x00000000,
123
+
0x00000000,
124
+
0x00000000,
125
+
0x00000000,
126
+
0x00000000,
127
+
0x00000000,
128
+
0x00000000,
129
+
0x00000000,
130
+
0x00000000,
131
+
0x00000000,
132
+
0x00000000,
133
+
0x00000000,
134
+
0x00000000,
135
+
0x00000000,
136
+
0x00000000,
137
+
0x00000000,
138
+
0x00000000,
139
+
/* 0x0200: xfer_data */
140
+
0x00000000,
141
+
0x00000000,
142
+
0x00000000,
143
+
0x00000000,
144
+
0x00000000,
145
+
0x00000000,
146
+
0x00000000,
147
+
0x00000000,
148
+
0x00000000,
149
+
0x00000000,
150
+
0x00000000,
151
+
0x00000000,
152
+
0x00000000,
153
+
0x00000000,
154
+
0x00000000,
155
+
0x00000000,
156
+
0x00000000,
157
+
0x00000000,
158
+
0x00000000,
159
+
0x00000000,
160
+
0x00000000,
161
+
0x00000000,
162
+
0x00000000,
163
+
0x00000000,
164
+
0x00000000,
165
+
0x00000000,
166
+
0x00000000,
167
+
0x00000000,
168
+
0x00000000,
169
+
0x00000000,
170
+
0x00000000,
171
+
0x00000000,
172
+
0x00000000,
173
+
0x00000000,
174
+
0x00000000,
175
+
0x00000000,
176
+
0x00000000,
177
+
0x00000000,
178
+
0x00000000,
179
+
0x00000000,
180
+
0x00000000,
181
+
0x00000000,
182
+
0x00000000,
183
+
0x00000000,
184
+
0x00000000,
185
+
0x00000000,
186
+
0x00000000,
187
+
0x00000000,
188
+
0x00000000,
189
+
0x00000000,
190
+
0x00000000,
191
+
0x00000000,
192
+
0x00000000,
193
+
0x00000000,
194
+
0x00000000,
195
+
0x00000000,
196
+
0x00000000,
197
+
0x00000000,
198
+
0x00000000,
199
+
0x00000000,
200
+
0x00000000,
201
+
0x00000000,
202
+
0x00000000,
203
+
0x00000000,
204
+
/* 0x0300: hub_mmio_list_base */
205
+
0x0417e91c,
206
+
};
207
+
208
+
uint32_t nvd7_grhub_code[] = {
209
+
0x03090ef5,
210
+
/* 0x0004: queue_put */
211
+
0x9800d898,
212
+
0x86f001d9,
213
+
0x0489b808,
214
+
0xf00c1bf4,
215
+
0x21f502f7,
216
+
0x00f802ec,
217
+
/* 0x001c: queue_put_next */
218
+
0xb60798c4,
219
+
0x8dbb0384,
220
+
0x0880b600,
221
+
0x80008e80,
222
+
0x90b6018f,
223
+
0x0f94f001,
224
+
0xf801d980,
225
+
/* 0x0039: queue_get */
226
+
0x0131f400,
227
+
0x9800d898,
228
+
0x89b801d9,
229
+
0x210bf404,
230
+
0xb60789c4,
231
+
0x9dbb0394,
232
+
0x0890b600,
233
+
0x98009e98,
234
+
0x80b6019f,
235
+
0x0f84f001,
236
+
0xf400d880,
237
+
/* 0x0066: queue_get_done */
238
+
0x00f80132,
239
+
/* 0x0068: nv_rd32 */
240
+
0x0728b7f1,
241
+
0xb906b4b6,
242
+
0xc9f002ec,
243
+
0x00bcd01f,
244
+
/* 0x0078: nv_rd32_wait */
245
+
0xc800bccf,
246
+
0x1bf41fcc,
247
+
0x06a7f0fa,
248
+
0x010321f5,
249
+
0xf840bfcf,
250
+
/* 0x008d: nv_wr32 */
251
+
0x28b7f100,
252
+
0x06b4b607,
253
+
0xb980bfd0,
254
+
0xc9f002ec,
255
+
0x1ec9f01f,
256
+
/* 0x00a3: nv_wr32_wait */
257
+
0xcf00bcd0,
258
+
0xccc800bc,
259
+
0xfa1bf41f,
260
+
/* 0x00ae: watchdog_reset */
261
+
0x87f100f8,
262
+
0x84b60430,
263
+
0x1ff9f006,
264
+
0xf8008fd0,
265
+
/* 0x00bd: watchdog_clear */
266
+
0x3087f100,
267
+
0x0684b604,
268
+
0xf80080d0,
269
+
/* 0x00c9: wait_donez */
270
+
0x3c87f100,
271
+
0x0684b608,
272
+
0x99f094bd,
273
+
0x0089d000,
274
+
0x081887f1,
275
+
0xd00684b6,
276
+
/* 0x00e2: wait_donez_ne */
277
+
0x87f1008a,
278
+
0x84b60400,
279
+
0x0088cf06,
280
+
0xf4888aff,
281
+
0x87f1f31b,
282
+
0x84b6085c,
283
+
0xf094bd06,
284
+
0x89d00099,
285
+
/* 0x0103: wait_doneo */
286
+
0xf100f800,
287
+
0xb6083c87,
288
+
0x94bd0684,
289
+
0xd00099f0,
290
+
0x87f10089,
291
+
0x84b60818,
292
+
0x008ad006,
293
+
/* 0x011c: wait_doneo_e */
294
+
0x040087f1,
295
+
0xcf0684b6,
296
+
0x8aff0088,
297
+
0xf30bf488,
298
+
0x085c87f1,
299
+
0xbd0684b6,
300
+
0x0099f094,
301
+
0xf80089d0,
302
+
/* 0x013d: mmctx_size */
303
+
/* 0x013f: nv_mmctx_size_loop */
304
+
0x9894bd00,
305
+
0x85b600e8,
306
+
0x0180b61a,
307
+
0xbb0284b6,
308
+
0xe0b60098,
309
+
0x04efb804,
310
+
0xb9eb1bf4,
311
+
0x00f8029f,
312
+
/* 0x015c: mmctx_xfer */
313
+
0x083c87f1,
314
+
0xbd0684b6,
315
+
0x0199f094,
316
+
0xf10089d0,
317
+
0xb6071087,
318
+
0x94bd0684,
319
+
0xf405bbfd,
320
+
0x8bd0090b,
321
+
0x0099f000,
322
+
/* 0x0180: mmctx_base_disabled */
323
+
0xf405eefd,
324
+
0x8ed00c0b,
325
+
0xc08fd080,
326
+
/* 0x018f: mmctx_multi_disabled */
327
+
0xb70199f0,
328
+
0xc8010080,
329
+
0xb4b600ab,
330
+
0x0cb9f010,
331
+
0xb601aec8,
332
+
0xbefd11e4,
333
+
0x008bd005,
334
+
/* 0x01a8: mmctx_exec_loop */
335
+
/* 0x01a8: mmctx_wait_free */
336
+
0xf0008ecf,
337
+
0x0bf41fe4,
338
+
0x00ce98fa,
339
+
0xd005e9fd,
340
+
0xc0b6c08e,
341
+
0x04cdb804,
342
+
0xc8e81bf4,
343
+
0x1bf402ab,
344
+
/* 0x01c9: mmctx_fini_wait */
345
+
0x008bcf18,
346
+
0xb01fb4f0,
347
+
0x1bf410b4,
348
+
0x02a7f0f7,
349
+
0xf4c921f4,
350
+
/* 0x01de: mmctx_stop */
351
+
0xabc81b0e,
352
+
0x10b4b600,
353
+
0xf00cb9f0,
354
+
0x8bd012b9,
355
+
/* 0x01ed: mmctx_stop_wait */
356
+
0x008bcf00,
357
+
0xf412bbc8,
358
+
/* 0x01f6: mmctx_done */
359
+
0x87f1fa1b,
360
+
0x84b6085c,
361
+
0xf094bd06,
362
+
0x89d00199,
363
+
/* 0x0207: strand_wait */
364
+
0xf900f800,
365
+
0x02a7f0a0,
366
+
0xfcc921f4,
367
+
/* 0x0213: strand_pre */
368
+
0xf100f8a0,
369
+
0xf04afc87,
370
+
0x97f00283,
371
+
0x0089d00c,
372
+
0x020721f5,
373
+
/* 0x0226: strand_post */
374
+
0x87f100f8,
375
+
0x83f04afc,
376
+
0x0d97f002,
377
+
0xf50089d0,
378
+
0xf8020721,
379
+
/* 0x0239: strand_set */
380
+
0xfca7f100,
381
+
0x02a3f04f,
382
+
0x0500aba2,
383
+
0xd00fc7f0,
384
+
0xc7f000ac,
385
+
0x00bcd00b,
386
+
0x020721f5,
387
+
0xf000aed0,
388
+
0xbcd00ac7,
389
+
0x0721f500,
390
+
/* 0x0263: strand_ctx_init */
391
+
0xf100f802,
392
+
0xb6083c87,
393
+
0x94bd0684,
394
+
0xd00399f0,
395
+
0x21f50089,
396
+
0xe7f00213,
397
+
0x3921f503,
398
+
0xfca7f102,
399
+
0x02a3f046,
400
+
0x0400aba0,
401
+
0xf040a0d0,
402
+
0xbcd001c7,
403
+
0x0721f500,
404
+
0x010c9202,
405
+
0xf000acd0,
406
+
0xbcd002c7,
407
+
0x0721f500,
408
+
0x2621f502,
409
+
0x8087f102,
410
+
0x0684b608,
411
+
0xb70089cf,
412
+
0x95220080,
413
+
/* 0x02ba: ctx_init_strand_loop */
414
+
0x8ed008fe,
415
+
0x408ed000,
416
+
0xb6808acf,
417
+
0xa0b606a5,
418
+
0x00eabb01,
419
+
0xb60480b6,
420
+
0x1bf40192,
421
+
0x08e4b6e8,
422
+
0xf1f2efbc,
423
+
0xb6085c87,
424
+
0x94bd0684,
425
+
0xd00399f0,
426
+
0x00f80089,
427
+
/* 0x02ec: error */
428
+
0xe7f1e0f9,
429
+
0xe4b60814,
430
+
0x00efd006,
431
+
0x0c1ce7f1,
432
+
0xf006e4b6,
433
+
0xefd001f7,
434
+
0xf8e0fc00,
435
+
/* 0x0309: init */
436
+
0xfe04bd00,
437
+
0x07fe0004,
438
+
0x0017f100,
439
+
0x0227f012,
440
+
0xf10012d0,
441
+
0xfe058517,
442
+
0x17f10010,
443
+
0x10d00400,
444
+
0x0437f1c0,
445
+
0x0634b604,
446
+
0x200327f1,
447
+
0xf10032d0,
448
+
0xd0200427,
449
+
0x27f10132,
450
+
0x32d0200b,
451
+
0x0c27f102,
452
+
0x0732d020,
453
+
0x0c2427f1,
454
+
0xb90624b6,
455
+
0x23d00003,
456
+
0x0427f100,
457
+
0x0023f087,
458
+
0xb70012d0,
459
+
0xf0010012,
460
+
0x12d00427,
461
+
0x1031f400,
462
+
0x9604e7f1,
463
+
0xf440e3f0,
464
+
0xf1c76821,
465
+
0x03018090,
466
+
0x801ff4f0,
467
+
0x17f0020f,
468
+
0x041fbb01,
469
+
0xf10112b6,
470
+
0xb6040c27,
471
+
0x21d00624,
472
+
0x4021d000,
473
+
0x010017f1,
474
+
0x98000e98,
475
+
0x21f5010f,
476
+
0x37f1013d,
477
+
0x34b60700,
478
+
0x08149506,
479
+
0xd00034d0,
480
+
0x30b74034,
481
+
0x1fbb1300,
482
+
0x02f5b600,
483
+
0xb6003fd0,
484
+
0x10b60815,
485
+
0x0814b601,
486
+
0xf5021fb9,
487
+
0xbb026321,
488
+
0x0398001f,
489
+
0x0047f102,
490
+
0x5043f020,
491
+
/* 0x03e4: init_gpc */
492
+
0x08044ea0,
493
+
0xf4021fb9,
494
+
0x4ea08d21,
495
+
0xf4bd010c,
496
+
0xa08d21f4,
497
+
0xf401044e,
498
+
0x4ea08d21,
499
+
0xf7f00100,
500
+
0x8d21f402,
501
+
0x08004ea0,
502
+
/* 0x040c: init_gpc_wait */
503
+
0xc86821f4,
504
+
0x0bf41fff,
505
+
0x044ea0fa,
506
+
0x6821f408,
507
+
0xb7001fbb,
508
+
0xb6800040,
509
+
0x1bf40132,
510
+
0x0027f1be,
511
+
0x0624b608,
512
+
0xb74021d0,
513
+
0xbd080020,
514
+
0x1f19f014,
515
+
/* 0x043f: main */
516
+
0xf40021d0,
517
+
0x28f40031,
518
+
0x10d7f000,
519
+
0xf43921f4,
520
+
0xe4b1f401,
521
+
0x1bf54001,
522
+
0x87f100d1,
523
+
0x84b6083c,
524
+
0xf094bd06,
525
+
0x89d00499,
526
+
0x0017f100,
527
+
0x0614b60b,
528
+
0xcf4012cf,
529
+
0x13c80011,
530
+
0x7e0bf41f,
531
+
0xf41f23c8,
532
+
0x20f95a0b,
533
+
0xf10212b9,
534
+
0xb6083c87,
535
+
0x94bd0684,
536
+
0xd00799f0,
537
+
0x32f40089,
538
+
0x0231f401,
539
+
0x07f521f5,
540
+
0x085c87f1,
541
+
0xbd0684b6,
542
+
0x0799f094,
543
+
0xfc0089d0,
544
+
0x3c87f120,
545
+
0x0684b608,
546
+
0x99f094bd,
547
+
0x0089d006,
548
+
0xf50131f4,
549
+
0xf107f521,
550
+
0xb6085c87,
551
+
0x94bd0684,
552
+
0xd00699f0,
553
+
0x0ef40089,
554
+
/* 0x04d5: chsw_prev_no_next */
555
+
0xb920f931,
556
+
0x32f40212,
557
+
0x0232f401,
558
+
0x07f521f5,
559
+
0x17f120fc,
560
+
0x14b60b00,
561
+
0x0012d006,
562
+
/* 0x04f3: chsw_no_prev */
563
+
0xc8130ef4,
564
+
0x0bf41f23,
565
+
0x0131f40d,
566
+
0xf50232f4,
567
+
/* 0x0503: chsw_done */
568
+
0xf107f521,
569
+
0xb60b0c17,
570
+
0x27f00614,
571
+
0x0012d001,
572
+
0x085c87f1,
573
+
0xbd0684b6,
574
+
0x0499f094,
575
+
0xf50089d0,
576
+
/* 0x0523: main_not_ctx_switch */
577
+
0xb0ff200e,
578
+
0x1bf401e4,
579
+
0x02f2b90d,
580
+
0x078121f5,
581
+
/* 0x0533: main_not_ctx_chan */
582
+
0xb0420ef4,
583
+
0x1bf402e4,
584
+
0x3c87f12e,
585
+
0x0684b608,
586
+
0x99f094bd,
587
+
0x0089d007,
588
+
0xf40132f4,
589
+
0x21f50232,
590
+
0x87f107f5,
591
+
0x84b6085c,
592
+
0xf094bd06,
593
+
0x89d00799,
594
+
0x110ef400,
595
+
/* 0x0564: main_not_ctx_save */
596
+
0xf010ef94,
597
+
0x21f501f5,
598
+
0x0ef502ec,
599
+
/* 0x0572: main_done */
600
+
0x17f1fed1,
601
+
0x14b60820,
602
+
0xf024bd06,
603
+
0x12d01f29,
604
+
0xbe0ef500,
605
+
/* 0x0585: ih */
606
+
0xfe80f9fe,
607
+
0x80f90188,
608
+
0xa0f990f9,
609
+
0xd0f9b0f9,
610
+
0xf0f9e0f9,
611
+
0xc4800acf,
612
+
0x0bf404ab,
613
+
0x00b7f11d,
614
+
0x10d7f019,
615
+
0xcf40becf,
616
+
0x21f400bf,
617
+
0x00b0b704,
618
+
0x01e7f004,
619
+
/* 0x05bb: ih_no_fifo */
620
+
0xe400bed0,
621
+
0xf40100ab,
622
+
0xd7f00d0b,
623
+
0x01e7f110,
624
+
0x0421f440,
625
+
/* 0x05cc: ih_no_ctxsw */
626
+
0x0104b7f1,
627
+
0xabffb0bd,
628
+
0x0d0bf4b4,
629
+
0x0c1ca7f1,
630
+
0xd006a4b6,
631
+
/* 0x05e2: ih_no_other */
632
+
0x0ad000ab,
633
+
0xfcf0fc40,
634
+
0xfcd0fce0,
635
+
0xfca0fcb0,
636
+
0xfe80fc90,
637
+
0x80fc0088,
638
+
0xf80032f4,
639
+
/* 0x05fd: ctx_4160s */
640
+
0x60e7f101,
641
+
0x40e3f041,
642
+
0xf401f7f0,
643
+
/* 0x060a: ctx_4160s_wait */
644
+
0x21f48d21,
645
+
0x04ffc868,
646
+
0xf8fa0bf4,
647
+
/* 0x0615: ctx_4160c */
648
+
0x60e7f100,
649
+
0x40e3f041,
650
+
0x21f4f4bd,
651
+
/* 0x0623: ctx_4170s */
652
+
0xf100f88d,
653
+
0xf04170e7,
654
+
0xf5f040e3,
655
+
0x8d21f410,
656
+
/* 0x0632: ctx_4170w */
657
+
0xe7f100f8,
658
+
0xe3f04170,
659
+
0x6821f440,
660
+
0xf410f4f0,
661
+
0x00f8f31b,
662
+
/* 0x0644: ctx_redswitch */
663
+
0x0614e7f1,
664
+
0xf106e4b6,
665
+
0xd00270f7,
666
+
0xf7f000ef,
667
+
/* 0x0655: ctx_redswitch_delay */
668
+
0x01f2b608,
669
+
0xf1fd1bf4,
670
+
0xd00770f7,
671
+
0x00f800ef,
672
+
/* 0x0664: ctx_86c */
673
+
0x086ce7f1,
674
+
0xd006e4b6,
675
+
0xe7f100ef,
676
+
0xe3f08a14,
677
+
0x8d21f440,
678
+
0xa86ce7f1,
679
+
0xf441e3f0,
680
+
0x00f88d21,
681
+
/* 0x0684: ctx_load */
682
+
0x083c87f1,
683
+
0xbd0684b6,
684
+
0x0599f094,
685
+
0xf00089d0,
686
+
0x21f40ca7,
687
+
0x2417f1c9,
688
+
0x0614b60a,
689
+
0xf10010d0,
690
+
0xb60b0037,
691
+
0x32d00634,
692
+
0x0c17f140,
693
+
0x0614b60a,
694
+
0xd00747f0,
695
+
0x14d00012,
696
+
/* 0x06bd: ctx_chan_wait_0 */
697
+
0x4014cf40,
698
+
0xf41f44f0,
699
+
0x32d0fa1b,
700
+
0x000bfe00,
701
+
0xb61f2af0,
702
+
0x20b60424,
703
+
0x3c87f102,
704
+
0x0684b608,
705
+
0x99f094bd,
706
+
0x0089d008,
707
+
0x0a0417f1,
708
+
0xd00614b6,
709
+
0x17f10012,
710
+
0x14b60a20,
711
+
0x0227f006,
712
+
0x800023f1,
713
+
0xf00012d0,
714
+
0x27f11017,
715
+
0x23f00200,
716
+
0x0512fa02,
717
+
0x87f103f8,
718
+
0x84b6085c,
719
+
0xf094bd06,
720
+
0x89d00899,
721
+
0x81019800,
722
+
0x981814b6,
723
+
0x25b68002,
724
+
0x0512fd08,
725
+
0xf1160180,
726
+
0xb6083c87,
727
+
0x94bd0684,
728
+
0xd00999f0,
729
+
0x27f10089,
730
+
0x24b60a04,
731
+
0x0021d006,
732
+
0xf10127f0,
733
+
0xb60a2017,
734
+
0x12d00614,
735
+
0x0017f100,
736
+
0x0613f001,
737
+
0xf80501fa,
738
+
0x5c87f103,
739
+
0x0684b608,
740
+
0x99f094bd,
741
+
0x0089d009,
742
+
0x085c87f1,
743
+
0xbd0684b6,
744
+
0x0599f094,
745
+
0xf80089d0,
746
+
/* 0x0781: ctx_chan */
747
+
0xfd21f500,
748
+
0x8421f505,
749
+
0x0ca7f006,
750
+
0xf1c921f4,
751
+
0xb60a1017,
752
+
0x27f00614,
753
+
0x0012d005,
754
+
/* 0x079c: ctx_chan_wait */
755
+
0xfd0012cf,
756
+
0x1bf40522,
757
+
0x1521f5fa,
758
+
/* 0x07ab: ctx_mmio_exec */
759
+
0x9800f806,
760
+
0x27f14103,
761
+
0x24b60a04,
762
+
0x0023d006,
763
+
/* 0x07ba: ctx_mmio_loop */
764
+
0x34c434bd,
765
+
0x0f1bf4ff,
766
+
0x020057f1,
767
+
0xfa0653f0,
768
+
0x03f80535,
769
+
/* 0x07cc: ctx_mmio_pull */
770
+
0x98804e98,
771
+
0x21f4814f,
772
+
0x0830b68d,
773
+
0xf40112b6,
774
+
/* 0x07de: ctx_mmio_done */
775
+
0x0398df1b,
776
+
0x0023d016,
777
+
0xf1400080,
778
+
0xf0010017,
779
+
0x01fa0613,
780
+
0xf803f806,
781
+
/* 0x07f5: ctx_xfer */
782
+
0x00f7f100,
783
+
0x06f4b60c,
784
+
0xd004e7f0,
785
+
/* 0x0802: ctx_xfer_idle */
786
+
0xfecf80fe,
787
+
0x00e4f100,
788
+
0xf91bf420,
789
+
0xf40611f4,
790
+
/* 0x0812: ctx_xfer_pre */
791
+
0xf7f01102,
792
+
0x6421f510,
793
+
0xfd21f506,
794
+
0x1c11f405,
795
+
/* 0x0820: ctx_xfer_pre_load */
796
+
0xf502f7f0,
797
+
0xf5062321,
798
+
0xf5063221,
799
+
0xbd064421,
800
+
0x2321f5f4,
801
+
0x8421f506,
802
+
/* 0x0839: ctx_xfer_exec */
803
+
0x16019806,
804
+
0x041427f1,
805
+
0xd00624b6,
806
+
0xe7f10020,
807
+
0xe3f0a500,
808
+
0x021fb941,
809
+
0xb68d21f4,
810
+
0xfcf004e0,
811
+
0x022cf001,
812
+
0xfd0124b6,
813
+
0x21f405f2,
814
+
0xfc17f18d,
815
+
0x0213f04a,
816
+
0xd00c27f0,
817
+
0x21f50012,
818
+
0x27f10207,
819
+
0x23f047fc,
820
+
0x0020d002,
821
+
0xb6012cf0,
822
+
0x12d00320,
823
+
0x01acf000,
824
+
0xf006a5f0,
825
+
0x0c9800b7,
826
+
0x010d9800,
827
+
0xf500e7f0,
828
+
0xf0015c21,
829
+
0x21f508a7,
830
+
0x21f50103,
831
+
0x01f40207,
832
+
0x0ca7f022,
833
+
0xf1c921f4,
834
+
0xb60a1017,
835
+
0x27f00614,
836
+
0x0012d005,
837
+
/* 0x08c0: ctx_xfer_post_save_wait */
838
+
0xfd0012cf,
839
+
0x1bf40522,
840
+
0x3202f4fa,
841
+
/* 0x08cc: ctx_xfer_post */
842
+
0xf502f7f0,
843
+
0xbd062321,
844
+
0x6421f5f4,
845
+
0x2621f506,
846
+
0x3221f502,
847
+
0xf5f4bd06,
848
+
0xf4062321,
849
+
0x01981011,
850
+
0x0511fd40,
851
+
0xf5070bf4,
852
+
/* 0x08f7: ctx_xfer_no_post_mmio */
853
+
0xf507ab21,
854
+
/* 0x08fb: ctx_xfer_done */
855
+
0xf8061521,
856
+
0x00000000,
857
+
};
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+4
drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
+4
drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
+14
-6
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+14
-6
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
···
282
282
{}
283
283
};
284
284
285
+
struct nvc0_graph_init
286
+
nvc0_graph_tpc_0[] = {
287
+
{ 0x50405c, 1, 0x04, 0x00000001 },
288
+
{}
289
+
};
290
+
285
291
void
286
292
nvc0_graph_mmio(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init)
287
293
{
···
988
982
for (i = 0; oclass->mmio[i]; i++)
989
983
nvc0_graph_mmio(priv, oclass->mmio[i]);
990
984
991
-
/* affects TFB offset queries */
992
-
nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1);
993
-
994
985
memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
995
986
for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
996
987
do {
···
1011
1008
nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
1012
1009
}
1013
1010
1014
-
nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
1011
+
if (nv_device(priv)->chipset != 0xd7)
1012
+
nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
1013
+
else
1014
+
nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
1015
+
1015
1016
nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
1016
1017
1017
1018
nv_wr32(priv, 0x400500, 0x00010001);
···
1130
1123
struct nvc0_graph_oclass *oclass = (void *)bclass;
1131
1124
struct nouveau_device *device = nv_device(parent);
1132
1125
struct nvc0_graph_priv *priv;
1133
-
bool enable = device->chipset != 0xd7;
1134
1126
int ret, i;
1135
1127
1136
-
ret = nouveau_graph_create(parent, engine, bclass, enable, &priv);
1128
+
ret = nouveau_graph_create(parent, engine, bclass, true, &priv);
1137
1129
*pobject = nv_object(priv);
1138
1130
if (ret)
1139
1131
return ret;
···
1205
1199
case 0xcf: /* 4/0/0/0, 3 */
1206
1200
priv->magic_not_rop_nr = 0x03;
1207
1201
break;
1202
+
case 0xd7:
1208
1203
case 0xd9: /* 1/0/0/0, 1 */
1209
1204
priv->magic_not_rop_nr = 0x01;
1210
1205
break;
···
1228
1221
nvc0_graph_init_gpc,
1229
1222
nvc0_graph_init_tpc,
1230
1223
nvc0_graph_init_unk88xx,
1224
+
nvc0_graph_tpc_0,
1231
1225
NULL
1232
1226
};
1233
1227
+6
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+6
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
···
193
193
extern struct nvc0_graph_init nvc0_graph_init_unk80xx[];
194
194
extern struct nvc0_graph_init nvc0_graph_init_gpc[];
195
195
extern struct nvc0_graph_init nvc0_graph_init_unk88xx[];
196
+
extern struct nvc0_graph_init nvc0_graph_tpc_0[];
196
197
197
198
extern struct nvc0_graph_init nvc3_graph_init_unk58xx[];
198
199
200
+
extern struct nvc0_graph_init nvd9_graph_init_unk58xx[];
199
201
extern struct nvc0_graph_init nvd9_graph_init_unk64xx[];
200
202
201
203
extern struct nvc0_graph_init nve4_graph_init_regs[];
···
211
209
void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
212
210
void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
213
211
void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
212
+
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
214
213
void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
215
214
216
215
extern struct nouveau_oclass *nvc0_grctx_oclass;
···
247
244
extern struct nvc0_graph_init nvc8_grctx_init_9197[];
248
245
extern struct nvc0_graph_init nvc8_grctx_init_9297[];
249
246
247
+
extern struct nouveau_oclass *nvd7_grctx_oclass;
248
+
250
249
extern struct nouveau_oclass *nvd9_grctx_oclass;
251
250
extern struct nvc0_graph_init nvd9_grctx_init_rop[];
251
+
extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[];
252
252
253
253
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
254
254
void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
+1
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
+1
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
+1
drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
+1
drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
+1
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
+1
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
+167
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
+167
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
···
1
+
/*
2
+
* Copyright 2013 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: Ben Skeggs <bskeggs@redhat.com>
23
+
*/
24
+
25
+
#include "nvc0.h"
26
+
27
+
/*******************************************************************************
28
+
* PGRAPH engine/subdev functions
29
+
******************************************************************************/
30
+
31
+
#include "fuc/hubnvd7.fuc.h"
32
+
33
+
struct nvc0_graph_ucode
34
+
nvd7_graph_fecs_ucode = {
35
+
.code.data = nvd7_grhub_code,
36
+
.code.size = sizeof(nvd7_grhub_code),
37
+
.data.data = nvd7_grhub_data,
38
+
.data.size = sizeof(nvd7_grhub_data),
39
+
};
40
+
41
+
#include "fuc/gpcnvd7.fuc.h"
42
+
43
+
struct nvc0_graph_ucode
44
+
nvd7_graph_gpccs_ucode = {
45
+
.code.data = nvd7_grgpc_code,
46
+
.code.size = sizeof(nvd7_grgpc_code),
47
+
.data.data = nvd7_grgpc_data,
48
+
.data.size = sizeof(nvd7_grgpc_data),
49
+
};
50
+
51
+
static struct nvc0_graph_init
52
+
nvd7_graph_init_gpc[] = {
53
+
{ 0x418408, 1, 0x04, 0x00000000 },
54
+
{ 0x4184a0, 1, 0x04, 0x00000000 },
55
+
{ 0x4184a4, 2, 0x04, 0x00000000 },
56
+
{ 0x418604, 1, 0x04, 0x00000000 },
57
+
{ 0x418680, 1, 0x04, 0x00000000 },
58
+
{ 0x418714, 1, 0x04, 0x00000000 },
59
+
{ 0x418384, 1, 0x04, 0x00000000 },
60
+
{ 0x418814, 3, 0x04, 0x00000000 },
61
+
{ 0x418b04, 1, 0x04, 0x00000000 },
62
+
{ 0x4188c8, 2, 0x04, 0x00000000 },
63
+
{ 0x4188d0, 1, 0x04, 0x00010000 },
64
+
{ 0x4188d4, 1, 0x04, 0x00000001 },
65
+
{ 0x418910, 1, 0x04, 0x00010001 },
66
+
{ 0x418914, 1, 0x04, 0x00000301 },
67
+
{ 0x418918, 1, 0x04, 0x00800000 },
68
+
{ 0x418980, 1, 0x04, 0x77777770 },
69
+
{ 0x418984, 3, 0x04, 0x77777777 },
70
+
{ 0x418c04, 1, 0x04, 0x00000000 },
71
+
{ 0x418c64, 1, 0x04, 0x00000000 },
72
+
{ 0x418c68, 1, 0x04, 0x00000000 },
73
+
{ 0x418c88, 1, 0x04, 0x00000000 },
74
+
{ 0x418cb4, 2, 0x04, 0x00000000 },
75
+
{ 0x418d00, 1, 0x04, 0x00000000 },
76
+
{ 0x418d28, 1, 0x04, 0x00000000 },
77
+
{ 0x418f00, 1, 0x04, 0x00000000 },
78
+
{ 0x418f08, 1, 0x04, 0x00000000 },
79
+
{ 0x418f20, 2, 0x04, 0x00000000 },
80
+
{ 0x418e00, 1, 0x04, 0x00000003 },
81
+
{ 0x418e08, 1, 0x04, 0x00000000 },
82
+
{ 0x418e1c, 1, 0x04, 0x00000000 },
83
+
{ 0x418e20, 1, 0x04, 0x00000000 },
84
+
{ 0x41900c, 1, 0x04, 0x00000000 },
85
+
{ 0x419018, 1, 0x04, 0x00000000 },
86
+
{}
87
+
};
88
+
89
+
static struct nvc0_graph_init
90
+
nvd7_graph_init_tpc[] = {
91
+
{ 0x419d08, 2, 0x04, 0x00000000 },
92
+
{ 0x419d10, 1, 0x04, 0x00000014 },
93
+
{ 0x419ab0, 1, 0x04, 0x00000000 },
94
+
{ 0x419ac8, 1, 0x04, 0x00000000 },
95
+
{ 0x419ab8, 1, 0x04, 0x000000e7 },
96
+
{ 0x419abc, 2, 0x04, 0x00000000 },
97
+
{ 0x419ab4, 1, 0x04, 0x00000000 },
98
+
{ 0x41980c, 1, 0x04, 0x00000010 },
99
+
{ 0x419844, 1, 0x04, 0x00000000 },
100
+
{ 0x41984c, 1, 0x04, 0x00005bc8 },
101
+
{ 0x419850, 2, 0x04, 0x00000000 },
102
+
{ 0x419c98, 1, 0x04, 0x00000000 },
103
+
{ 0x419ca8, 1, 0x04, 0x80000000 },
104
+
{ 0x419cb4, 1, 0x04, 0x00000000 },
105
+
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
106
+
{ 0x419cbc, 1, 0x04, 0x28137606 },
107
+
{ 0x419cc0, 2, 0x04, 0x00000000 },
108
+
{ 0x419c0c, 1, 0x04, 0x00000000 },
109
+
{ 0x419e00, 1, 0x04, 0x00000000 },
110
+
{ 0x419ea0, 1, 0x04, 0x00000000 },
111
+
{ 0x419ea4, 1, 0x04, 0x00000100 },
112
+
{ 0x419ea8, 1, 0x04, 0x02001100 },
113
+
{ 0x419eac, 1, 0x04, 0x11100702 },
114
+
{ 0x419eb0, 1, 0x04, 0x00000003 },
115
+
{ 0x419eb4, 4, 0x04, 0x00000000 },
116
+
{ 0x419ec8, 1, 0x04, 0x0e063818 },
117
+
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
118
+
{ 0x419ed0, 1, 0x04, 0x00003818 },
119
+
{ 0x419ed4, 1, 0x04, 0x011104f1 },
120
+
{ 0x419edc, 1, 0x04, 0x00000000 },
121
+
{ 0x419f00, 1, 0x04, 0x00000000 },
122
+
{ 0x419f2c, 1, 0x04, 0x00000000 },
123
+
{}
124
+
};
125
+
126
+
static struct nvc0_graph_init
127
+
nvd7_graph_init_tpc_0[] = {
128
+
{ 0x40402c, 1, 0x04, 0x00000000 },
129
+
{ 0x4040f0, 1, 0x04, 0x00000000 },
130
+
{ 0x404174, 1, 0x04, 0x00000000 },
131
+
{ 0x503018, 1, 0x04, 0x00000001 },
132
+
{}
133
+
};
134
+
135
+
static struct nvc0_graph_init *
136
+
nvd7_graph_init_mmio[] = {
137
+
nvc0_graph_init_regs,
138
+
nvc0_graph_init_unk40xx,
139
+
nvc0_graph_init_unk44xx,
140
+
nvc0_graph_init_unk78xx,
141
+
nvc0_graph_init_unk60xx,
142
+
nvd9_graph_init_unk64xx,
143
+
nvd9_graph_init_unk58xx,
144
+
nvc0_graph_init_unk80xx,
145
+
nvd7_graph_init_gpc,
146
+
nvd7_graph_init_tpc,
147
+
nve4_graph_init_unk,
148
+
nvc0_graph_init_unk88xx,
149
+
nvd7_graph_init_tpc_0,
150
+
NULL
151
+
};
152
+
153
+
struct nouveau_oclass *
154
+
nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
155
+
.base.handle = NV_ENGINE(GR, 0xd7),
156
+
.base.ofuncs = &(struct nouveau_ofuncs) {
157
+
.ctor = nvc0_graph_ctor,
158
+
.dtor = nvc0_graph_dtor,
159
+
.init = nvc0_graph_init,
160
+
.fini = _nouveau_graph_fini,
161
+
},
162
+
.cclass = &nvd7_grctx_oclass,
163
+
.sclass = nvc8_graph_sclass,
164
+
.mmio = nvd7_graph_init_mmio,
165
+
.fecs.ucode = &nvd7_graph_fecs_ucode,
166
+
.gpccs.ucode = &nvd7_graph_gpccs_ucode,
167
+
}.base;
+2
-1
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
+2
-1
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
···
34
34
{}
35
35
};
36
36
37
-
static struct nvc0_graph_init
37
+
struct nvc0_graph_init
38
38
nvd9_graph_init_unk58xx[] = {
39
39
{ 0x405844, 1, 0x04, 0x00ffffff },
40
40
{ 0x405850, 1, 0x04, 0x00000000 },
···
144
144
nvd9_graph_init_gpc,
145
145
nvd9_graph_init_tpc,
146
146
nvc0_graph_init_unk88xx,
147
+
nvc0_graph_tpc_0,
147
148
NULL
148
149
};
149
150
+1
drivers/gpu/drm/nouveau/core/include/engine/graph.h
+1
drivers/gpu/drm/nouveau/core/include/engine/graph.h
···
65
65
extern struct nouveau_oclass *nvc1_graph_oclass;
66
66
extern struct nouveau_oclass *nvc3_graph_oclass;
67
67
extern struct nouveau_oclass *nvc8_graph_oclass;
68
+
extern struct nouveau_oclass *nvd7_graph_oclass;
68
69
extern struct nouveau_oclass *nvd9_graph_oclass;
69
70
extern struct nouveau_oclass *nve4_graph_oclass;
70
71
extern struct nouveau_oclass *nvf0_graph_oclass;