tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

staging: rtl8723au: odm.c: Further reduce the use of ODM_SetBBReg()

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Jes Sorensen and committed by
Greg Kroah-Hartman 2635f19c 3f9cb6a0

+119 -49
+119 -49
drivers/staging/rtl8723au/hal/odm.c
··· 441 441 442 442 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI) 443 443 { 444 + struct rtw_adapter *adapter = pDM_Odm->Adapter; 444 445 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable; 445 - 446 - ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 447 - ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n", 448 - ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 446 + u32 val32; 449 447 450 448 if (pDM_DigTable->CurIGValue != CurrentIGI) { 451 - ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), 452 - ODM_BIT(IGI, pDM_Odm), CurrentIGI); 449 + val32 = rtl8723au_read32(adapter, ODM_REG_IGI_A_11N); 450 + val32 &= ~ODM_BIT_IGI_11N; 451 + val32 |= CurrentIGI; 452 + rtl8723au_write32(adapter, ODM_REG_IGI_A_11N, val32); 453 453 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 454 454 ("CurrentIGI(0x%02x). \n", CurrentIGI)); 455 455 pDM_DigTable->CurIGValue = CurrentIGI; ··· 722 722 { 723 723 struct rtw_adapter *adapter = pDM_Odm->Adapter; 724 724 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt; 725 - u32 ret_value; 725 + u32 ret_value, val32; 726 726 727 727 /* hold ofdm counter */ 728 728 /* hold page C counter */ 729 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); 729 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_HOLDC_11N); 730 + val32 |= BIT(31); 731 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_HOLDC_11N, val32); 730 732 /* hold page D counter */ 731 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); 733 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_RSTD_11N); 734 + val32 |= BIT(31); 735 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_RSTD_11N, val32); 732 736 ret_value = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_TYPE1_11N); 733 737 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 734 738 FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff0000)>>16; ··· 752 748 FalseAlmCnt->Cnt_Fast_Fsync + 753 749 FalseAlmCnt->Cnt_SB_Search_fail; 754 750 /* hold cck counter */ 755 - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); 756 - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); 751 + val32 = rtl8723au_read32(adapter, ODM_REG_CCK_FA_RST_11N); 752 + val32 |= (BIT(12) | BIT(14)); 753 + rtl8723au_write32(adapter, ODM_REG_CCK_FA_RST_11N, val32); 757 754 758 755 ret_value = rtl8723au_read32(adapter, ODM_REG_CCK_FA_LSB_11N) & 0xff; 759 756 FalseAlmCnt->Cnt_Cck_fail = ret_value; ··· 778 773 779 774 if (pDM_Odm->SupportICType >= ODM_RTL8723A) { 780 775 /* reset false alarm counter registers */ 781 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1); 782 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0); 783 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1); 784 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0); 776 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_RSTC_11N); 777 + val32 |= BIT(31); 778 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_RSTC_11N, val32); 779 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_RSTC_11N); 780 + val32 &= ~BIT(31); 781 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_RSTC_11N, val32); 782 + 783 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_RSTD_11N); 784 + val32 |= BIT(27); 785 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_RSTD_11N, val32); 786 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_RSTD_11N); 787 + val32 &= ~BIT(27); 788 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_RSTD_11N, val32); 789 + 785 790 /* update ofdm counter */ 786 791 /* update page C counter */ 787 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); 792 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_HOLDC_11N); 793 + val32 &= ~BIT(31); 794 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_HOLDC_11N, val32); 795 + 788 796 /* update page D counter */ 789 - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); 797 + val32 = rtl8723au_read32(adapter, ODM_REG_OFDM_FA_RSTD_11N); 798 + val32 &= ~BIT(31); 799 + rtl8723au_write32(adapter, ODM_REG_OFDM_FA_RSTD_11N, val32); 790 800 791 801 /* reset CCK CCA counter */ 792 - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, 793 - BIT(13) | BIT(12), 0); 794 - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, 795 - BIT(13) | BIT(12), 2); 796 - /* reset CCK FA counter */ 797 - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, 798 - BIT(15) | BIT(14), 0); 799 - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, 800 - BIT(15) | BIT(14), 2); 802 + val32 = rtl8723au_read32(adapter, ODM_REG_CCK_FA_RST_11N); 803 + val32 &= ~(BIT(12) | BIT(13) | BIT(14) | BIT(15)); 804 + rtl8723au_write32(adapter, ODM_REG_CCK_FA_RST_11N, val32); 805 + 806 + val32 = rtl8723au_read32(adapter, ODM_REG_CCK_FA_RST_11N); 807 + val32 |= (BIT(13) | BIT(15)); 808 + rtl8723au_write32(adapter, ODM_REG_CCK_FA_RST_11N, val32); 801 809 } 802 810 803 811 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ··· 903 885 { 904 886 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable; 905 887 struct rtw_adapter *adapter = pDM_Odm->Adapter; 888 + u32 val32; 906 889 u8 Rssi_Up_bound = 30; 907 890 u8 Rssi_Low_bound = 25; 908 891 if (pDM_PSTable->initialize == 0) { ··· 945 926 * Set 0x874[5]= 1 when enter BB power saving mode. */ 946 927 /* Suggested by SD3 Yu-Nan. 2011.01.20. */ 947 928 /* Reg874[5]= 1b'1 */ 948 - if (pDM_Odm->SupportICType == ODM_RTL8723A) 949 - ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); 929 + if (pDM_Odm->SupportICType == ODM_RTL8723A) { 930 + val32 = rtl8723au_read32(adapter, 0x874); 931 + val32 |= BIT(5); 932 + rtl8723au_write32(adapter, 0x874, val32); 933 + } 950 934 /* Reg874[20:18]= 3'b010 */ 951 - ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); 935 + val32 = rtl8723au_read32(adapter, 0x874); 936 + val32 &= ~(BIT(18) | BIT(20)); 937 + val32 |= BIT(19); 938 + rtl8723au_write32(adapter, 0x874, val32); 952 939 /* RegC70[3]= 1'b0 */ 953 - ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); 940 + val32 = rtl8723au_read32(adapter, 0xc70); 941 + val32 &= ~BIT(3); 942 + rtl8723au_write32(adapter, 0xc70, val32); 954 943 /* Reg85C[31:24]= 0x63 */ 955 - ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); 944 + val32 = rtl8723au_read32(adapter, 0x85c); 945 + val32 &= 0x00ffffff; 946 + val32 |= 0x63000000; 947 + rtl8723au_write32(adapter, 0x85c, val32); 956 948 /* Reg874[15:14]= 2'b10 */ 957 - ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); 949 + val32 = rtl8723au_read32(adapter, 0x874); 950 + val32 &= ~BIT(14); 951 + val32 |= BIT(15); 952 + rtl8723au_write32(adapter, 0x874, val32); 958 953 /* RegA75[7:4]= 0x3 */ 959 - ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); 954 + val32 = rtl8723au_read32(adapter, 0xa74); 955 + val32 &= ~(BIT(14) | BIT(15)); 956 + val32 |= (BIT(12) | BIT(13)); 957 + rtl8723au_write32(adapter, 0xa74, val32); 960 958 /* Reg818[28]= 1'b0 */ 961 - ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); 959 + val32 = rtl8723au_read32(adapter, 0x818); 960 + val32 &= ~BIT(28); 961 + rtl8723au_write32(adapter, 0x818, val32); 962 962 /* Reg818[28]= 1'b1 */ 963 - ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); 963 + val32 = rtl8723au_read32(adapter, 0x818); 964 + val32 |= BIT(28); 965 + rtl8723au_write32(adapter, 0x818, val32); 964 966 } else { 965 967 ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, 966 968 pDM_PSTable->Reg874); ··· 991 951 pDM_PSTable->Reg85C); 992 952 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 993 953 pDM_PSTable->RegA74); 994 - ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); 954 + val32 = rtl8723au_read32(adapter, 0x818); 955 + val32 &= ~BIT(28); 956 + rtl8723au_write32(adapter, 0x818, val32); 995 957 996 958 /* Reg874[5]= 1b'0 */ 997 - if (pDM_Odm->SupportICType == ODM_RTL8723A) 998 - ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); 959 + if (pDM_Odm->SupportICType == ODM_RTL8723A) { 960 + val32 = rtl8723au_read32(adapter, 0x874); 961 + val32 &= ~BIT(5); 962 + rtl8723au_write32(adapter, 0x874, val32); 963 + } 999 964 } 1000 965 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 1001 966 } ··· 1417 1372 u8 initial_gain_psd) 1418 1373 { 1419 1374 struct rtw_adapter *adapter = pDM_Odm->Adapter; 1420 - u32 psd_report; 1375 + u32 psd_report, val32; 1421 1376 1422 1377 /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */ 1423 - ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); 1378 + val32 = rtl8723au_read32(adapter, 0x808); 1379 + val32 &= ~0x3ff; 1380 + val32 |= (point & 0x3ff); 1381 + rtl8723au_write32(adapter, 0x808, val32); 1424 1382 1425 1383 /* Start PSD calculation, Reg808[22]= 0->1 */ 1426 - ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1); 1384 + val32 = rtl8723au_read32(adapter, 0x808); 1385 + val32 |= BIT(22); 1386 + rtl8723au_write32(adapter, 0x808, val32); 1427 1387 /* Need to wait for HW PSD report */ 1428 1388 udelay(30); 1429 - ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0); 1389 + val32 = rtl8723au_read32(adapter, 0x808); 1390 + val32 &= ~BIT(22); 1391 + rtl8723au_write32(adapter, 0x808, val32); 1430 1392 /* Read PSD report, Reg8B4[15:0] */ 1431 1393 psd_report = rtl8723au_read32(adapter, 0x8B4) & 0x0000FFFF; 1432 1394 ··· 1514 1462 struct rtw_adapter *adapter = pDM_Odm->Adapter; 1515 1463 u32 CurrentChannel, RfLoopReg; 1516 1464 u8 n; 1517 - u32 Reg88c, Regc08, Reg874, Regc50; 1465 + u32 Reg88c, Regc08, Reg874, Regc50, val32; 1518 1466 u8 initial_gain = 0x5a; 1519 1467 u32 PSD_report_tmp; 1520 1468 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; ··· 1541 1489 bRFRegOffsetMask); 1542 1490 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask); 1543 1491 /* change to Antenna A */ 1544 - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); 1492 + val32 = rtl8723au_read32(adapter, rFPGA0_XA_RFInterfaceOE); 1493 + val32 &= ~0x300; 1494 + val32 |= 0x100; /* Enable antenna A */ 1495 + rtl8723au_write32(adapter, rFPGA0_XA_RFInterfaceOE, val32); 1496 + 1545 1497 /* Step 1: USE IQK to transmitter single tone */ 1546 1498 1547 1499 udelay(10); ··· 1560 1504 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 1561 1505 1562 1506 /* Set PSD 128 pts */ 1563 - ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0); 1507 + val32 = rtl8723au_read32(adapter, rFPGA0_PSDFunction); 1508 + val32 &= ~(BIT(14) | BIT(15)); 1509 + rtl8723au_write32(adapter, rFPGA0_PSDFunction, val32); 1564 1510 1565 1511 /* To SET CH1 to do */ 1566 1512 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); ··· 1622 1564 1623 1565 PSD_report_tmp = 0x0; 1624 1566 1625 - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */ 1567 + val32 = rtl8723au_read32(adapter, rFPGA0_XA_RFInterfaceOE); 1568 + val32 &= ~0x300; 1569 + val32 |= 0x200; /* Enable antenna B */ 1570 + rtl8723au_write32(adapter, rFPGA0_XA_RFInterfaceOE, val32); 1626 1571 udelay(10); 1627 1572 1628 1573 for (n = 0; n < 2; n++) { ··· 1636 1575 1637 1576 /* change to open case */ 1638 1577 /* change to Ant A and B all open case */ 1639 - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); 1578 + val32 = rtl8723au_read32(adapter, rFPGA0_XA_RFInterfaceOE); 1579 + val32 &= ~0x300; 1580 + rtl8723au_write32(adapter, rFPGA0_XA_RFInterfaceOE, val32); 1640 1581 udelay(10); 1641 1582 1642 1583 for (n = 0; n < 2; n++) { ··· 1652 1589 PSD_report_tmp = 0x0; 1653 1590 1654 1591 /* 1 Return to antanna A */ 1655 - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 1592 + val32 = rtl8723au_read32(adapter, rFPGA0_XA_RFInterfaceOE); 1593 + val32 &= ~0x300; 1594 + val32 |= 0x100; /* Enable antenna A */ 1595 + rtl8723au_write32(adapter, rFPGA0_XA_RFInterfaceOE, val32); 1656 1596 rtl8723au_write32(adapter, rFPGA0_AnalogParameter4, Reg88c); 1657 1597 rtl8723au_write32(adapter, rOFDM0_TRMuxPar, Regc08); 1658 1598 rtl8723au_write32(adapter, rFPGA0_XCD_RFInterfaceSW, Reg874); 1659 - ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); 1599 + val32 = rtl8723au_read32(adapter, rOFDM0_XAAGCCore1); 1600 + val32 &= ~0x7f; 1601 + val32 |= 0x40; 1602 + rtl8723au_write32(adapter, rOFDM0_XAAGCCore1, val32); 1603 + 1660 1604 rtl8723au_write32(adapter, rOFDM0_XAAGCCore1, Regc50); 1661 1605 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 1662 1606 CurrentChannel);