drm/amdgpu: expand cg_flags from u32 to u64

tjh.dev / kernel

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

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drm/amdgpu: expand cg_flags from u32 to u64

With this, we can support more CG flags.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by

Alex Deucher 4 years ago 25faeddc 49aa98ca

+95 -92

53 changed files

expand all collapse all

drivers

gpu

drm

amd

amdgpu

amdgpu.h

amdgpu_debugfs.c

amdgpu_device.c

amdgpu_df.h

amdgpu_drv.c

amdgpu_hdp.h

amdgpu_mmhub.h

amdgpu_nbio.h

amdgpu_smuio.h

athub_v1_0.c

athub_v1_0.h

athub_v2_0.c

athub_v2_0.h

athub_v2_1.c

athub_v2_1.h

df_v1_7.c

df_v3_6.c

gfx_v10_0.c

gfx_v8_0.c

gfx_v9_0.c

gmc_v10_0.c

gmc_v8_0.c

gmc_v9_0.c

hdp_v4_0.c

hdp_v5_0.c

mmhub_v1_0.c

mmhub_v1_7.c

mmhub_v2_0.c

mmhub_v2_3.c

mmhub_v9_4.c

navi10_ih.c

nbio_v2_3.c

nbio_v6_1.c

nbio_v7_0.c

nbio_v7_2.c

nbio_v7_4.c

nv.c

sdma_v3_0.c

sdma_v4_0.c

sdma_v5_0.c

sdma_v5_2.c

smuio_v11_0.c

smuio_v11_0_6.c

smuio_v13_0.c

smuio_v9_0.c

soc15.c

uvd_v5_0.c

uvd_v6_0.c

vce_v3_0.c

vi.c

include

amd_shared.h

amdgpu_pm.c

inc

amdgpu_pm.h

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 179 179 extern int amdgpu_sched_hw_submission; 180 180 extern uint amdgpu_pcie_gen_cap; 181 181 extern uint amdgpu_pcie_lane_cap; 182 182 - extern uint amdgpu_cg_mask; 182 182 + extern u64 amdgpu_cg_mask; 183 183 extern uint amdgpu_pg_mask; 184 184 extern uint amdgpu_sdma_phase_quantum; 185 185 extern char *amdgpu_disable_cu; ··· 322 322 enum amd_ip_block_type block_type, 323 323 enum amd_powergating_state state); 324 324 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 325 325 - u32 *flags); 325 325 + u64 *flags); 326 326 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 327 327 enum amd_ip_block_type block_type); 328 328 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, ··· 860 860 /* powerplay */ 861 861 struct amd_powerplay powerplay; 862 862 struct amdgpu_pm pm; 863 863 - u32 cg_flags; 863 863 + u64 cg_flags; 864 864 u32 pg_flags; 865 865 866 866 /* nbio */

+4 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

reviewed

··· 758 758 /* rev==1 */ 759 759 config[no_regs++] = adev->rev_id; 760 760 config[no_regs++] = adev->pg_flags; 761 761 - config[no_regs++] = adev->cg_flags; 761 761 + config[no_regs++] = lower_32_bits(adev->cg_flags); 762 762 763 763 /* rev==2 */ 764 764 config[no_regs++] = adev->family; ··· 772 772 773 773 /* rev==4 APU flag */ 774 774 config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0; 775 775 + 776 776 + /* rev==5 CG flag upper 32bit */ 777 777 + config[no_regs++] = upper_32_bits(adev->cg_flags); 775 778 776 779 while (size && (*pos < no_regs * 4)) { 777 780 uint32_t value;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 1703 1703 * clockgating is enabled. 1704 1704 */ 1705 1705 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 1706 1706 - u32 *flags) 1706 1706 + u64 *flags) 1707 1707 { 1708 1708 int i; 1709 1709

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_df.h

reviewed

··· 40 40 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 41 41 bool enable); 42 42 void (*get_clockgating_state)(struct amdgpu_device *adev, 43 43 - u32 *flags); 43 43 + u64 *flags); 44 44 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 45 45 bool enable); 46 46 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,

+4 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

reviewed

··· 136 136 int amdgpu_sched_hw_submission = 2; 137 137 uint amdgpu_pcie_gen_cap; 138 138 uint amdgpu_pcie_lane_cap; 139 139 - uint amdgpu_cg_mask = 0xffffffff; 139 139 + u64 amdgpu_cg_mask = 0xffffffffffffffff; 140 140 uint amdgpu_pg_mask = 0xffffffff; 141 141 uint amdgpu_sdma_phase_quantum = 32; 142 142 char *amdgpu_disable_cu = NULL; ··· 454 454 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 455 455 456 456 /** 457 457 - * DOC: cg_mask (uint) 457 457 + * DOC: cg_mask (ullong) 458 458 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 459 459 - * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 459 459 + * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 460 460 */ 461 461 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 462 462 - module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 462 462 + module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 463 463 464 464 /** 465 465 * DOC: pg_mask (uint)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h

reviewed

··· 33 33 void (*invalidate_hdp)(struct amdgpu_device *adev, 34 34 struct amdgpu_ring *ring); 35 35 void (*update_clock_gating)(struct amdgpu_device *adev, bool enable); 36 36 - void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags); 36 36 + void (*get_clock_gating_state)(struct amdgpu_device *adev, u64 *flags); 37 37 void (*init_registers)(struct amdgpu_device *adev); 38 38 }; 39 39

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h

reviewed

··· 34 34 void (*gart_disable)(struct amdgpu_device *adev); 35 35 int (*set_clockgating)(struct amdgpu_device *adev, 36 36 enum amd_clockgating_state state); 37 37 - void (*get_clockgating)(struct amdgpu_device *adev, u32 *flags); 37 37 + void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags); 38 38 void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 39 39 uint64_t page_table_base); 40 40 void (*update_power_gating)(struct amdgpu_device *adev,

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h

reviewed

··· 83 83 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 84 84 bool enable); 85 85 void (*get_clockgating_state)(struct amdgpu_device *adev, 86 86 - u32 *flags); 86 86 + u64 *flags); 87 87 void (*ih_control)(struct amdgpu_device *adev); 88 88 void (*init_registers)(struct amdgpu_device *adev); 89 89 void (*remap_hdp_registers)(struct amdgpu_device *adev);

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h

reviewed

··· 27 27 u32 (*get_rom_index_offset)(struct amdgpu_device *adev); 28 28 u32 (*get_rom_data_offset)(struct amdgpu_device *adev); 29 29 void (*update_rom_clock_gating)(struct amdgpu_device *adev, bool enable); 30 30 - void (*get_clock_gating_state)(struct amdgpu_device *adev, u32 *flags); 30 30 + void (*get_clock_gating_state)(struct amdgpu_device *adev, u64 *flags); 31 31 u32 (*get_die_id)(struct amdgpu_device *adev); 32 32 u32 (*get_socket_id)(struct amdgpu_device *adev); 33 33 bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev);

+1 -1

drivers/gpu/drm/amd/amdgpu/athub_v1_0.c

reviewed

··· 87 87 return 0; 88 88 } 89 89 90 90 - void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 90 90 + void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 91 91 { 92 92 int data; 93 93

+1 -1

drivers/gpu/drm/amd/amdgpu/athub_v1_0.h

reviewed

··· 25 25 26 26 int athub_v1_0_set_clockgating(struct amdgpu_device *adev, 27 27 enum amd_clockgating_state state); 28 28 - void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags); 28 28 + void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags); 29 29 30 30 #endif

+1 -1

drivers/gpu/drm/amd/amdgpu/athub_v2_0.c

reviewed

··· 93 93 return 0; 94 94 } 95 95 96 96 - void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 96 96 + void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 97 97 { 98 98 int data; 99 99

+1 -1

drivers/gpu/drm/amd/amdgpu/athub_v2_0.h

reviewed

··· 25 25 26 26 int athub_v2_0_set_clockgating(struct amdgpu_device *adev, 27 27 enum amd_clockgating_state state); 28 28 - void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags); 28 28 + void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags); 29 29 30 30 #endif

+1 -1

drivers/gpu/drm/amd/amdgpu/athub_v2_1.c

reviewed

··· 85 85 return 0; 86 86 } 87 87 88 88 - void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u32 *flags) 88 88 + void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags) 89 89 { 90 90 int data; 91 91

+1 -1

drivers/gpu/drm/amd/amdgpu/athub_v2_1.h

reviewed

··· 25 25 26 26 int athub_v2_1_set_clockgating(struct amdgpu_device *adev, 27 27 enum amd_clockgating_state state); 28 28 - void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u32 *flags); 28 28 + void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags); 29 29 30 30 #endif

+1 -1

drivers/gpu/drm/amd/amdgpu/df_v1_7.c

reviewed

··· 99 99 } 100 100 101 101 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev, 102 102 - u32 *flags) 102 102 + u64 *flags) 103 103 { 104 104 u32 tmp; 105 105

+1 -1

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

reviewed

··· 332 332 } 333 333 334 334 static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev, 335 335 - u32 *flags) 335 335 + u64 *flags) 336 336 { 337 337 u32 tmp; 338 338

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

reviewed

··· 8451 8451 return 0; 8452 8452 } 8453 8453 8454 8454 - static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 8454 8454 + static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8455 8455 { 8456 8456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8457 8457 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

reviewed

··· 5475 5475 return 0; 5476 5476 } 5477 5477 5478 5478 - static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags) 5478 5478 + static void gfx_v8_0_get_clockgating_state(void *handle, u64 *flags) 5479 5479 { 5480 5480 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5481 5481 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

reviewed

··· 5233 5233 return 0; 5234 5234 } 5235 5235 5236 5236 - static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 5236 5236 + static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5237 5237 { 5238 5238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5239 5239 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

reviewed

··· 1161 1161 return athub_v2_0_set_clockgating(adev, state); 1162 1162 } 1163 1163 1164 1164 - static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1164 1164 + static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1165 1165 { 1166 1166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1167 1167

+1 -1

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

reviewed

··· 1690 1690 return 0; 1691 1691 } 1692 1692 1693 1693 - static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1693 1693 + static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags) 1694 1694 { 1695 1695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1696 1696 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

reviewed

··· 1948 1948 return 0; 1949 1949 } 1950 1950 1951 1951 - static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1951 1951 + static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 1952 1952 { 1953 1953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1954 1954

+1 -1

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

reviewed

··· 124 124 } 125 125 126 126 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, 127 127 - u32 *flags) 127 127 + u64 *flags) 128 128 { 129 129 int data; 130 130

+1 -1

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

reviewed

··· 181 181 } 182 182 183 183 static void hdp_v5_0_get_clockgating_state(struct amdgpu_device *adev, 184 184 - u32 *flags) 184 184 + u64 *flags) 185 185 { 186 186 uint32_t tmp; 187 187

+1 -1

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

reviewed

··· 546 546 return 0; 547 547 } 548 548 549 549 - static void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 549 549 + static void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 550 550 { 551 551 int data, data1; 552 552

+1 -1

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

reviewed

··· 542 542 return 0; 543 543 } 544 544 545 545 - static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u32 *flags) 545 545 + static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags) 546 546 { 547 547 int data, data1; 548 548

+1 -1

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

reviewed

··· 682 682 return 0; 683 683 } 684 684 685 685 - static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 685 685 + static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 686 686 { 687 687 int data, data1; 688 688

+1 -1

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

reviewed

··· 577 577 return 0; 578 578 } 579 579 580 580 - static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags) 580 580 + static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) 581 581 { 582 582 int data, data1, data2, data3; 583 583

+1 -1

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

reviewed

··· 647 647 return 0; 648 648 } 649 649 650 650 - static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags) 650 650 + static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags) 651 651 { 652 652 int data, data1; 653 653

+1 -1

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

reviewed

··· 685 685 return 0; 686 686 } 687 687 688 688 - static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 688 688 + static void navi10_ih_get_clockgating_state(void *handle, u64 *flags) 689 689 { 690 690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 691 691

+1 -1

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

reviewed

··· 278 278 } 279 279 280 280 static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, 281 281 - u32 *flags) 281 281 + u64 *flags) 282 282 { 283 283 int data; 284 284

+1 -1

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

reviewed

··· 210 210 } 211 211 212 212 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, 213 213 - u32 *flags) 213 213 + u64 *flags) 214 214 { 215 215 int data; 216 216

+1 -1

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

reviewed

··· 205 205 } 206 206 207 207 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev, 208 208 - u32 *flags) 208 208 + u64 *flags) 209 209 { 210 210 int data; 211 211

+1 -1

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

reviewed

··· 306 306 } 307 307 308 308 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev, 309 309 - u32 *flags) 309 309 + u64 *flags) 310 310 { 311 311 int data; 312 312

+1 -1

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

reviewed

··· 273 273 } 274 274 275 275 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 276 276 - u32 *flags) 276 276 + u64 *flags) 277 277 { 278 278 int data; 279 279

+1 -1

drivers/gpu/drm/amd/amdgpu/nv.c

reviewed

··· 1115 1115 return 0; 1116 1116 } 1117 1117 1118 1118 - static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1118 1118 + static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1119 1119 { 1120 1120 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1121 1121

+1 -1

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

reviewed

··· 1535 1535 return 0; 1536 1536 } 1537 1537 1538 1538 - static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1538 1538 + static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags) 1539 1539 { 1540 1540 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1541 1541 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

reviewed

··· 2372 2372 return 0; 2373 2373 } 2374 2374 2375 2375 - static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2375 2375 + static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) 2376 2376 { 2377 2377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2378 2378 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

reviewed

··· 1648 1648 return 0; 1649 1649 } 1650 1650 1651 1651 - static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1651 1651 + static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags) 1652 1652 { 1653 1653 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1654 1654 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

reviewed

··· 1645 1645 return 0; 1646 1646 } 1647 1647 1648 1648 - static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags) 1648 1648 + static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1649 1649 { 1650 1650 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1651 1651 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c

reviewed

··· 59 59 WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data); 60 60 } 61 61 62 62 - static void smuio_v11_0_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) 62 62 + static void smuio_v11_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags) 63 63 { 64 64 u32 data; 65 65

+1 -1

drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c

reviewed

··· 56 56 WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data); 57 57 } 58 58 59 59 - static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) 59 59 + static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags) 60 60 { 61 61 u32 data; 62 62

+1 -1

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

reviewed

··· 58 58 WREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0, data); 59 59 } 60 60 61 61 - static void smuio_v13_0_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) 61 61 + static void smuio_v13_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags) 62 62 { 63 63 u32 data; 64 64

+1 -1

drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c

reviewed

··· 56 56 WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data); 57 57 } 58 58 59 59 - static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags) 59 59 + static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags) 60 60 { 61 61 u32 data; 62 62

+1 -1

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 1419 1419 return 0; 1420 1420 } 1421 1421 1422 1422 - static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1422 1422 + static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 1423 1423 { 1424 1424 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1425 1425 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

reviewed

··· 833 833 return ret; 834 834 } 835 835 836 836 - static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 836 836 + static void uvd_v5_0_get_clockgating_state(void *handle, u64 *flags) 837 837 { 838 838 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 839 839 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

reviewed

··· 1494 1494 return ret; 1495 1495 } 1496 1496 1497 1497 - static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags) 1497 1497 + static void uvd_v6_0_get_clockgating_state(void *handle, u64 *flags) 1498 1498 { 1499 1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1500 1500 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

reviewed

··· 831 831 return ret; 832 832 } 833 833 834 834 - static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags) 834 834 + static void vce_v3_0_get_clockgating_state(void *handle, u64 *flags) 835 835 { 836 836 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 837 837 int data;

+1 -1

drivers/gpu/drm/amd/amdgpu/vi.c

reviewed

··· 2033 2033 return 0; 2034 2034 } 2035 2035 2036 2036 - static void vi_common_get_clockgating_state(void *handle, u32 *flags) 2036 2036 + static void vi_common_get_clockgating_state(void *handle, u64 *flags) 2037 2037 { 2038 2038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2039 2039 int data;

+33 -33

drivers/gpu/drm/amd/include/amd_shared.h

reviewed

··· 116 116 117 117 118 118 /* CG flags */ 119 119 - #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 120 120 - #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 121 121 - #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 122 122 - #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 123 123 - #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 124 124 - #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 125 125 - #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 126 126 - #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 127 127 - #define AMD_CG_SUPPORT_MC_LS (1 << 8) 128 128 - #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 129 129 - #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 130 130 - #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 131 131 - #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 132 132 - #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 133 133 - #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 134 134 - #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 135 135 - #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 136 136 - #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 137 137 - #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 138 138 - #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 139 139 - #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 140 140 - #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 141 141 - #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 142 142 - #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 143 143 - #define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) 144 144 - #define AMD_CG_SUPPORT_HDP_DS (1 << 25) 145 145 - #define AMD_CG_SUPPORT_HDP_SD (1 << 26) 146 146 - #define AMD_CG_SUPPORT_IH_CG (1 << 27) 147 147 - #define AMD_CG_SUPPORT_ATHUB_LS (1 << 28) 148 148 - #define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29) 149 149 - #define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30) 150 150 - #define AMD_CG_SUPPORT_GFX_FGCG (1 << 31) 119 119 + #define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0) 120 120 + #define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1) 121 121 + #define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2) 122 122 + #define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3) 123 123 + #define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4) 124 124 + #define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5) 125 125 + #define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6) 126 126 + #define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7) 127 127 + #define AMD_CG_SUPPORT_MC_LS (1ULL << 8) 128 128 + #define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9) 129 129 + #define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10) 130 130 + #define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11) 131 131 + #define AMD_CG_SUPPORT_BIF_LS (1ULL << 12) 132 132 + #define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13) 133 133 + #define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14) 134 134 + #define AMD_CG_SUPPORT_HDP_LS (1ULL << 15) 135 135 + #define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16) 136 136 + #define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17) 137 137 + #define AMD_CG_SUPPORT_DRM_LS (1ULL << 18) 138 138 + #define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19) 139 139 + #define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20) 140 140 + #define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21) 141 141 + #define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22) 142 142 + #define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23) 143 143 + #define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24) 144 144 + #define AMD_CG_SUPPORT_HDP_DS (1ULL << 25) 145 145 + #define AMD_CG_SUPPORT_HDP_SD (1ULL << 26) 146 146 + #define AMD_CG_SUPPORT_IH_CG (1ULL << 27) 147 147 + #define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28) 148 148 + #define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29) 149 149 + #define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30) 150 150 + #define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31) 151 151 /* PG flags */ 152 152 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 153 153 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) ··· 298 298 enum amd_clockgating_state state); 299 299 int (*set_powergating_state)(void *handle, 300 300 enum amd_powergating_state state); 301 301 - void (*get_clockgating_state)(void *handle, u32 *flags); 301 301 + void (*get_clockgating_state)(void *handle, u64 *flags); 302 302 }; 303 303 304 304

+3 -3

drivers/gpu/drm/amd/pm/amdgpu_pm.c

reviewed

··· 3526 3526 return 0; 3527 3527 } 3528 3528 3529 3529 - static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags) 3529 3529 + static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 3530 3530 { 3531 3531 int i; 3532 3532 ··· 3539 3539 { 3540 3540 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3541 3541 struct drm_device *dev = adev_to_drm(adev); 3542 3542 - u32 flags = 0; 3542 3542 + u64 flags = 0; 3543 3543 int r; 3544 3544 3545 3545 if (amdgpu_in_reset(adev)) ··· 3561 3561 3562 3562 amdgpu_device_ip_get_clockgating_state(adev, &flags); 3563 3563 3564 3564 - seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); 3564 3564 + seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 3565 3565 amdgpu_parse_cg_state(m, flags); 3566 3566 seq_printf(m, "\n"); 3567 3567

+1 -1

drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h

reviewed

··· 26 26 27 27 struct cg_flag_name 28 28 { 29 29 - u32 flag; 29 29 + u64 flag; 30 30 const char *name; 31 31 }; 32 32