tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format
Convert nxp,lpc1850-rgu.txt to yaml format.
Additional changes:
- remove label in example.
- remove reset consumer in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250602144046.943982-1-Frank.Li@nxp.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
authored by
Frank Li
and committed by
Philipp Zabel
25ef9563
e73bfb4c
+101
-83
-83
Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt
-83
Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt
···
1
-
NXP LPC1850 Reset Generation Unit (RGU)
2
-
========================================
3
-
4
-
Please also refer to reset.txt in this directory for common reset
5
-
controller binding usage.
6
-
7
-
Required properties:
8
-
- compatible: Should be "nxp,lpc1850-rgu"
9
-
- reg: register base and length
10
-
- clocks: phandle and clock specifier to RGU clocks
11
-
- clock-names: should contain "delay" and "reg"
12
-
- #reset-cells: should be 1
13
-
14
-
See table below for valid peripheral reset numbers. Numbers not
15
-
in the table below are either reserved or not applicable for
16
-
normal operation.
17
-
18
-
Reset Peripheral
19
-
9 System control unit (SCU)
20
-
12 ARM Cortex-M0 subsystem core (LPC43xx only)
21
-
13 CPU core
22
-
16 LCD controller
23
-
17 USB0
24
-
18 USB1
25
-
19 DMA
26
-
20 SDIO
27
-
21 External memory controller (EMC)
28
-
22 Ethernet
29
-
25 Flash bank A
30
-
27 EEPROM
31
-
28 GPIO
32
-
29 Flash bank B
33
-
32 Timer0
34
-
33 Timer1
35
-
34 Timer2
36
-
35 Timer3
37
-
36 Repetitive Interrupt timer (RIT)
38
-
37 State Configurable Timer (SCT)
39
-
38 Motor control PWM (MCPWM)
40
-
39 QEI
41
-
40 ADC0
42
-
41 ADC1
43
-
42 DAC
44
-
44 USART0
45
-
45 UART1
46
-
46 USART2
47
-
47 USART3
48
-
48 I2C0
49
-
49 I2C1
50
-
50 SSP0
51
-
51 SSP1
52
-
52 I2S0 and I2S1
53
-
53 Serial Flash Interface (SPIFI)
54
-
54 C_CAN1
55
-
55 C_CAN0
56
-
56 ARM Cortex-M0 application core (LPC4370 only)
57
-
57 SGPIO (LPC43xx only)
58
-
58 SPI (LPC43xx only)
59
-
60 ADCHS (12-bit ADC) (LPC4370 only)
60
-
61
-
Refer to NXP LPC18xx or LPC43xx user manual for more details about
62
-
the reset signals and the connected block/peripheral.
63
-
64
-
Reset provider example:
65
-
rgu: reset-controller@40053000 {
66
-
compatible = "nxp,lpc1850-rgu";
67
-
reg = <0x40053000 0x1000>;
68
-
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
69
-
clock-names = "delay", "reg";
70
-
#reset-cells = <1>;
71
-
};
72
-
73
-
Reset consumer example:
74
-
mac: ethernet@40010000 {
75
-
compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
76
-
reg = <0x40010000 0x2000>;
77
-
interrupts = <5>;
78
-
interrupt-names = "macirq";
79
-
clocks = <&ccu1 CLK_CPU_ETHERNET>;
80
-
clock-names = "stmmaceth";
81
-
resets = <&rgu 22>;
82
-
reset-names = "stmmaceth";
83
-
};
+101
Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.yaml
+101
Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP LPC1850 Reset Generation Unit (RGU)
8
+
9
+
maintainers:
10
+
- Frank Li <Frank.Li@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: nxp,lpc1850-rgu
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
maxItems: 2
21
+
22
+
clock-names:
23
+
items:
24
+
- const: delay
25
+
- const: reg
26
+
27
+
'#reset-cells':
28
+
const: 1
29
+
description: |
30
+
See table below for valid peripheral reset numbers. Numbers not
31
+
in the table below are either reserved or not applicable for
32
+
normal operation.
33
+
34
+
Reset Peripheral
35
+
9 System control unit (SCU)
36
+
12 ARM Cortex-M0 subsystem core (LPC43xx only)
37
+
13 CPU core
38
+
16 LCD controller
39
+
17 USB0
40
+
18 USB1
41
+
19 DMA
42
+
20 SDIO
43
+
21 External memory controller (EMC)
44
+
22 Ethernet
45
+
25 Flash bank A
46
+
27 EEPROM
47
+
28 GPIO
48
+
29 Flash bank B
49
+
32 Timer0
50
+
33 Timer1
51
+
34 Timer2
52
+
35 Timer3
53
+
36 Repetitive Interrupt timer (RIT)
54
+
37 State Configurable Timer (SCT)
55
+
38 Motor control PWM (MCPWM)
56
+
39 QEI
57
+
40 ADC0
58
+
41 ADC1
59
+
42 DAC
60
+
44 USART0
61
+
45 UART1
62
+
46 USART2
63
+
47 USART3
64
+
48 I2C0
65
+
49 I2C1
66
+
50 SSP0
67
+
51 SSP1
68
+
52 I2S0 and I2S1
69
+
53 Serial Flash Interface (SPIFI)
70
+
54 C_CAN1
71
+
55 C_CAN0
72
+
56 ARM Cortex-M0 application core (LPC4370 only)
73
+
57 SGPIO (LPC43xx only)
74
+
58 SPI (LPC43xx only)
75
+
60 ADCHS (12-bit ADC) (LPC4370 only)
76
+
77
+
Refer to NXP LPC18xx or LPC43xx user manual for more details about
78
+
the reset signals and the connected block/peripheral.
79
+
80
+
required:
81
+
- compatible
82
+
- reg
83
+
- clocks
84
+
- clock-names
85
+
- '#reset-cells'
86
+
87
+
additionalProperties: false
88
+
89
+
examples:
90
+
- |
91
+
#include <dt-bindings/clock/lpc18xx-ccu.h>
92
+
#include <dt-bindings/clock/lpc18xx-cgu.h>
93
+
94
+
reset-controller@40053000 {
95
+
compatible = "nxp,lpc1850-rgu";
96
+
reg = <0x40053000 0x1000>;
97
+
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
98
+
clock-names = "delay", "reg";
99
+
#reset-cells = <1>;
100
+
};
101
+