Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
[AGP] intel_agp: Add support for Intel 4 series chipsets
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
authored by Zhenyu Wang and committed by Dave Airlie 25ce77ab 598d1448
+73
-10
drivers/char/agp/intel-agp.c
+73
-10
drivers/char/agp/intel-agp.c
···
34
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35
#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36
#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
37
38
/* cover 915 and 945 variants */
39
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
···
60
#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
61
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
62
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
63
64
extern int agp_memory_reserved;
65
···
90
#define I915_PTEADDR 0x1C
91
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
92
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
93
-
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
94
-
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
95
#define I915_IFPADDR 0x60
96
97
/* Intel 965G registers */
···
521
size = 512;
522
}
523
size += 4;
524
} else {
525
/* On previous hardware, the GTT size was just what was
526
* required to map the aperture.
···
573
break;
574
case I915_GMCH_GMS_STOLEN_48M:
575
/* Check it's really I915G */
576
-
if (IS_I915 || IS_I965 || IS_G33)
577
gtt_entries = MB(48) - KB(size);
578
else
579
gtt_entries = 0;
580
break;
581
case I915_GMCH_GMS_STOLEN_64M:
582
/* Check it's really I915G */
583
-
if (IS_I915 || IS_I965 || IS_G33)
584
gtt_entries = MB(64) - KB(size);
585
else
586
gtt_entries = 0;
587
break;
588
case G33_GMCH_GMS_STOLEN_128M:
589
-
if (IS_G33 || IS_I965)
590
gtt_entries = MB(128) - KB(size);
591
else
592
gtt_entries = 0;
593
break;
594
case G33_GMCH_GMS_STOLEN_256M:
595
-
if (IS_G33 || IS_I965)
596
gtt_entries = MB(256) - KB(size);
597
else
598
gtt_entries = 0;
599
break;
···
1179
return addr | bridge->driver->masks[type].mask;
1180
}
1181
1182
/* The intel i965 automatically initializes the agp aperture during POST.
1183
* Use the memory already set aside for in the GTT.
1184
*/
···
1213
1214
temp &= 0xfff00000;
1215
1216
-
if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1217
-
gtt_offset = gtt_size = MB(2);
1218
-
else
1219
-
gtt_offset = gtt_size = KB(512);
1220
1221
intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1222
···
2119
NULL, &intel_g33_driver },
2120
{ PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2121
"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2122
{ 0, 0, 0, NULL, NULL, NULL }
2123
};
2124
···
2316
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2317
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2318
ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2319
{ }
2320
};
2321
···
34
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35
#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36
#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
37
+
#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38
+
#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39
+
#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40
+
#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41
+
#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42
+
#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
43
44
/* cover 915 and 945 variants */
45
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
···
54
#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
55
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
56
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
57
+
58
+
#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
59
+
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
60
+
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
61
62
extern int agp_memory_reserved;
63
···
80
#define I915_PTEADDR 0x1C
81
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
82
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
83
+
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
84
+
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
85
+
#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
86
+
#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
87
+
#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
88
+
#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
89
+
90
#define I915_IFPADDR 0x60
91
92
/* Intel 965G registers */
···
506
size = 512;
507
}
508
size += 4;
509
+
} else if (IS_G4X) {
510
+
/* On 4 series hardware, GTT stolen is separate from graphics
511
+
* stolen, ignore it in stolen gtt entries counting */
512
+
size = 0;
513
} else {
514
/* On previous hardware, the GTT size was just what was
515
* required to map the aperture.
···
554
break;
555
case I915_GMCH_GMS_STOLEN_48M:
556
/* Check it's really I915G */
557
+
if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
558
gtt_entries = MB(48) - KB(size);
559
else
560
gtt_entries = 0;
561
break;
562
case I915_GMCH_GMS_STOLEN_64M:
563
/* Check it's really I915G */
564
+
if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
565
gtt_entries = MB(64) - KB(size);
566
else
567
gtt_entries = 0;
568
break;
569
case G33_GMCH_GMS_STOLEN_128M:
570
+
if (IS_G33 || IS_I965 || IS_G4X)
571
gtt_entries = MB(128) - KB(size);
572
else
573
gtt_entries = 0;
574
break;
575
case G33_GMCH_GMS_STOLEN_256M:
576
+
if (IS_G33 || IS_I965 || IS_G4X)
577
gtt_entries = MB(256) - KB(size);
578
+
else
579
+
gtt_entries = 0;
580
+
break;
581
+
case INTEL_GMCH_GMS_STOLEN_96M:
582
+
if (IS_I965 || IS_G4X)
583
+
gtt_entries = MB(96) - KB(size);
584
+
else
585
+
gtt_entries = 0;
586
+
break;
587
+
case INTEL_GMCH_GMS_STOLEN_160M:
588
+
if (IS_I965 || IS_G4X)
589
+
gtt_entries = MB(160) - KB(size);
590
+
else
591
+
gtt_entries = 0;
592
+
break;
593
+
case INTEL_GMCH_GMS_STOLEN_224M:
594
+
if (IS_I965 || IS_G4X)
595
+
gtt_entries = MB(224) - KB(size);
596
+
else
597
+
gtt_entries = 0;
598
+
break;
599
+
case INTEL_GMCH_GMS_STOLEN_352M:
600
+
if (IS_I965 || IS_G4X)
601
+
gtt_entries = MB(352) - KB(size);
602
else
603
gtt_entries = 0;
604
break;
···
1136
return addr | bridge->driver->masks[type].mask;
1137
}
1138
1139
+
static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1140
+
{
1141
+
switch (agp_bridge->dev->device) {
1142
+
case PCI_DEVICE_ID_INTEL_IGD_HB:
1143
+
case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1144
+
case PCI_DEVICE_ID_INTEL_Q45_HB:
1145
+
case PCI_DEVICE_ID_INTEL_G45_HB:
1146
+
*gtt_offset = *gtt_size = MB(2);
1147
+
break;
1148
+
default:
1149
+
*gtt_offset = *gtt_size = KB(512);
1150
+
}
1151
+
}
1152
+
1153
/* The intel i965 automatically initializes the agp aperture during POST.
1154
* Use the memory already set aside for in the GTT.
1155
*/
···
1156
1157
temp &= 0xfff00000;
1158
1159
+
intel_i965_get_gtt_range(>t_offset, >t_size);
1160
1161
intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1162
···
2065
NULL, &intel_g33_driver },
2066
{ PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2067
"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2068
+
{ PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2069
+
"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2070
+
{ PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2071
+
"Q45/Q43", NULL, &intel_i965_driver },
2072
+
{ PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2073
+
"G45/G43", NULL, &intel_i965_driver },
2074
{ 0, 0, 0, NULL, NULL, NULL }
2075
};
2076
···
2256
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2257
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2258
ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2259
+
ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2260
+
ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2261
+
ID(PCI_DEVICE_ID_INTEL_G45_HB),
2262
{ }
2263
};
2264