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linux
m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx
The ColdFire 54xx family shares the same interrupt controller used
on the 523x, 527x and 528x ColdFire parts, but it isn't offset
relative to the IPSBAR register. The 54xx doesn't have an IPSBAR
register.
By including the base address of the peripheral registers in the register
definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid
having to define a fake IPSBAR for the 54xx. And this makes the register
address definitions of these more consistent, the majority of the other
register address defines include the peripheral base address already.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
+18
-18
+1
-3
arch/m68k/include/asm/coldfire.h
+1
-3
arch/m68k/include/asm/coldfire.h
···
31
31
* This is generally setup by the boards start up code.
32
32
*/
33
33
#define MCF_MBAR 0x10000000
34
-
#if defined(CONFIG_M54xx)
35
-
#define MCF_IPSBAR MCF_MBAR
36
-
#elif defined(CONFIG_M520x)
34
+
#if defined(CONFIG_M520x)
37
35
#define MCF_IPSBAR 0xFC000000
38
36
#else
39
37
#define MCF_IPSBAR 0x40000000
+3
-2
arch/m68k/include/asm/m523xsim.h
+3
-2
arch/m68k/include/asm/m523xsim.h
···
19
19
/*
20
20
* Define the 523x SIM register set addresses.
21
21
*/
22
-
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
23
-
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
22
+
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23
+
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
24
+
24
25
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25
26
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26
27
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+3
-2
arch/m68k/include/asm/m527xsim.h
+3
-2
arch/m68k/include/asm/m527xsim.h
···
19
19
/*
20
20
* Define the 5270/5271 SIM register set addresses.
21
21
*/
22
-
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
23
-
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
22
+
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23
+
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
24
+
24
25
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25
26
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26
27
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+3
-2
arch/m68k/include/asm/m528xsim.h
+3
-2
arch/m68k/include/asm/m528xsim.h
···
19
19
/*
20
20
* Define the 5280/5282 SIM register set addresses.
21
21
*/
22
-
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
23
-
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
22
+
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
23
+
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
24
+
24
25
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25
26
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26
27
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+2
-1
arch/m68k/include/asm/m54xxsim.h
+2
-1
arch/m68k/include/asm/m54xxsim.h
···
15
15
/*
16
16
* Interrupt Controller Registers
17
17
*/
18
-
#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
18
+
#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
19
+
19
20
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
20
21
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
21
22
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+6
-8
arch/m68knommu/platform/coldfire/intc-2.c
+6
-8
arch/m68knommu/platform/coldfire/intc-2.c
···
52
52
u32 val, imrbit;
53
53
54
54
irq -= MCFINT_VECBASE;
55
-
imraddr = MCF_IPSBAR;
56
55
#ifdef MCFICM_INTC1
57
-
imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
56
+
imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
58
57
#else
59
-
imraddr += MCFICM_INTC0;
58
+
imraddr = MCFICM_INTC0;
60
59
#endif
61
60
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
62
61
imrbit = 0x1 << (irq & 0x1f);
···
74
75
u32 val, imrbit;
75
76
76
77
irq -= MCFINT_VECBASE;
77
-
intaddr = MCF_IPSBAR;
78
78
#ifdef MCFICM_INTC1
79
-
intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
79
+
intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
80
80
#else
81
-
intaddr += MCFICM_INTC0;
81
+
intaddr = MCFICM_INTC0;
82
82
#endif
83
83
imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
84
84
icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
···
114
116
init_vectors();
115
117
116
118
/* Mask all interrupt sources */
117
-
__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
119
+
__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
118
120
#ifdef MCFICM_INTC1
119
-
__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
121
+
__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
120
122
#endif
121
123
122
124
for (irq = 0; (irq < NR_IRQS); irq++) {