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dt-bindings: pinctrl: add schema for NXP S32 SoCs
Add DT schema for the pinctrl driver of NXP S32 SoC family.
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230220023320.3499-2-clin@suse.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Chester Lin
and committed by
Linus Walleij
2545625b
00408f28
+123
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Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
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Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2022 NXP
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP S32G2 pin controller
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maintainers:
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- Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
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- Chester Lin <clin@suse.com>
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description: |
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S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
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whose memory map is split into two regions:
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SIUL2_0 @ 0x4009c000
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SIUL2_1 @ 0x44010000
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Every SIUL2 region has multiple register types, and here only MSCR and
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IMCR registers need to be revealed for kernel to configure pinmux.
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Please note that some register indexes are reserved in S32G2, such as
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MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
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properties:
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compatible:
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enum:
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- nxp,s32g2-siul2-pinctrl
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reg:
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description: |
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A list of MSCR/IMCR register regions to be reserved.
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- MSCR (Multiplexed Signal Configuration Register)
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An MSCR register can configure the associated pin as either a GPIO pin
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or a function output pin depends on the selected signal source.
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- IMCR (Input Multiplexed Signal Configuration Register)
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An IMCR register can configure the associated pin as function input
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pin depends on the selected signal source.
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items:
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- description: MSCR registers group 0 in SIUL2_0
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- description: MSCR registers group 1 in SIUL2_1
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- description: MSCR registers group 2 in SIUL2_1
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- description: IMCR registers group 0 in SIUL2_0
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- description: IMCR registers group 1 in SIUL2_1
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- description: IMCR registers group 2 in SIUL2_1
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patternProperties:
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'-pins$':
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type: object
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additionalProperties: false
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patternProperties:
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'-grp[0-9]$':
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type: object
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allOf:
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- $ref: pinmux-node.yaml#
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- $ref: pincfg-node.yaml#
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description: |
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Pinctrl node's client devices specify pin muxes using subnodes,
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which in turn use the standard properties below.
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properties:
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bias-disable: true
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bias-high-impedance: true
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bias-pull-up: true
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bias-pull-down: true
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drive-open-drain: true
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input-enable: true
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output-enable: true
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pinmux:
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description: |
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An integer array for representing pinmux configurations of
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a device. Each integer consists of a PIN_ID and a 4-bit
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selected signal source(SSS) as IOMUX setting, which is
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calculated as: pinmux = (PIN_ID << 4 | SSS)
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slew-rate:
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description: Supported slew rate based on Fmax values (MHz)
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enum: [83, 133, 150, 166, 208]
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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pinctrl@4009c240 {
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compatible = "nxp,s32g2-siul2-pinctrl";
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/* MSCR0-MSCR101 registers on siul2_0 */
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reg = <0x4009c240 0x198>,
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/* MSCR112-MSCR122 registers on siul2_1 */
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<0x44010400 0x2c>,
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/* MSCR144-MSCR190 registers on siul2_1 */
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<0x44010480 0xbc>,
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/* IMCR0-IMCR83 registers on siul2_0 */
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<0x4009ca40 0x150>,
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/* IMCR119-IMCR397 registers on siul2_1 */
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<0x44010c1c 0x45c>,
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/* IMCR430-IMCR495 registers on siul2_1 */
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<0x440110f8 0x108>;
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llce-can0-pins {
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llce-can0-grp0 {
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pinmux = <0x2b0>;
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input-enable;
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slew-rate = <208>;
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};
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llce-can0-grp1 {
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pinmux = <0x2c2>;
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output-enable;
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slew-rate = <208>;
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};
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};
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};
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...