Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/kms/blit: fix blit copy for very large buffers
drm/radeon/kms: fix TRAVIS panel setup
drm/radeon: fix use after free in ATRM bios reading code.
drm/radeon/kms: Fix device tree linkage of DP i2c buses too
drm/radeon: Set DESKTOP_HEIGHT register to the framebuffer (not mode) height.
drm/radeon/kms: disable output polling when suspended
drm/nv50/pm: signedness bug in nv50_pm_clocks_pre()
drm/nouveau/gem: fix fence_sync race / oops
drm/nouveau: fix typo on mxmdcb option
drm/nouveau/mxm: pretend to succeed, even if we can't shadow the MXM-SIS
drm/nouveau/disp: check that panel power gpio is enabled at init time

+95 -23
+3 -2
drivers/gpu/drm/nouveau/nouveau_bios.h
··· 54 54 int bit_table(struct drm_device *, u8 id, struct bit_entry *); 55 55 56 56 enum dcb_gpio_tag { 57 - DCB_GPIO_TVDAC0 = 0xc, 57 + DCB_GPIO_PANEL_POWER = 0x01, 58 + DCB_GPIO_TVDAC0 = 0x0c, 58 59 DCB_GPIO_TVDAC1 = 0x2d, 59 - DCB_GPIO_PWM_FAN = 0x9, 60 + DCB_GPIO_PWM_FAN = 0x09, 60 61 DCB_GPIO_FAN_SENSE = 0x3d, 61 62 DCB_GPIO_UNUSED = 0xff 62 63 };
+10
drivers/gpu/drm/nouveau/nouveau_display.c
··· 219 219 if (ret) 220 220 return ret; 221 221 222 + /* power on internal panel if it's not already. the init tables of 223 + * some vbios default this to off for some reason, causing the 224 + * panel to not work after resume 225 + */ 226 + if (nouveau_gpio_func_get(dev, DCB_GPIO_PANEL_POWER) == 0) { 227 + nouveau_gpio_func_set(dev, DCB_GPIO_PANEL_POWER, true); 228 + msleep(300); 229 + } 230 + 231 + /* enable polling for external displays */ 222 232 drm_kms_helper_poll_enable(dev); 223 233 224 234 /* enable hotplug interrupts */
+1 -1
drivers/gpu/drm/nouveau/nouveau_drv.c
··· 124 124 int nouveau_ctxfw; 125 125 module_param_named(ctxfw, nouveau_ctxfw, int, 0400); 126 126 127 - MODULE_PARM_DESC(ctxfw, "Santise DCB table according to MXM-SIS\n"); 127 + MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS\n"); 128 128 int nouveau_mxmdcb = 1; 129 129 module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400); 130 130
+21 -2
drivers/gpu/drm/nouveau/nouveau_gem.c
··· 380 380 } 381 381 382 382 static int 383 + validate_sync(struct nouveau_channel *chan, struct nouveau_bo *nvbo) 384 + { 385 + struct nouveau_fence *fence = NULL; 386 + int ret = 0; 387 + 388 + spin_lock(&nvbo->bo.bdev->fence_lock); 389 + if (nvbo->bo.sync_obj) 390 + fence = nouveau_fence_ref(nvbo->bo.sync_obj); 391 + spin_unlock(&nvbo->bo.bdev->fence_lock); 392 + 393 + if (fence) { 394 + ret = nouveau_fence_sync(fence, chan); 395 + nouveau_fence_unref(&fence); 396 + } 397 + 398 + return ret; 399 + } 400 + 401 + static int 383 402 validate_list(struct nouveau_channel *chan, struct list_head *list, 384 403 struct drm_nouveau_gem_pushbuf_bo *pbbo, uint64_t user_pbbo_ptr) 385 404 { ··· 412 393 list_for_each_entry(nvbo, list, entry) { 413 394 struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index]; 414 395 415 - ret = nouveau_fence_sync(nvbo->bo.sync_obj, chan); 396 + ret = validate_sync(chan, nvbo); 416 397 if (unlikely(ret)) { 417 398 NV_ERROR(dev, "fail pre-validate sync\n"); 418 399 return ret; ··· 435 416 return ret; 436 417 } 437 418 438 - ret = nouveau_fence_sync(nvbo->bo.sync_obj, chan); 419 + ret = validate_sync(chan, nvbo); 439 420 if (unlikely(ret)) { 440 421 NV_ERROR(dev, "fail post-validate sync\n"); 441 422 return ret;
+9
drivers/gpu/drm/nouveau/nouveau_mxm.c
··· 656 656 657 657 if (mxm_shadow(dev, mxm[0])) { 658 658 MXM_MSG(dev, "failed to locate valid SIS\n"); 659 + #if 0 660 + /* we should, perhaps, fall back to some kind of limited 661 + * mode here if the x86 vbios hasn't already done the 662 + * work for us (so we prevent loading with completely 663 + * whacked vbios tables). 664 + */ 659 665 return -EINVAL; 666 + #else 667 + return 0; 668 + #endif 660 669 } 661 670 662 671 MXM_MSG(dev, "MXMS Version %d.%d\n",
+2 -2
drivers/gpu/drm/nouveau/nv50_pm.c
··· 495 495 struct drm_nouveau_private *dev_priv = dev->dev_private; 496 496 struct nv50_pm_state *info; 497 497 struct pll_lims pll; 498 - int ret = -EINVAL; 498 + int clk, ret = -EINVAL; 499 499 int N, M, P1, P2; 500 - u32 clk, out; 500 + u32 out; 501 501 502 502 if (dev_priv->chipset == 0xaa || 503 503 dev_priv->chipset == 0xac)
+2 -2
drivers/gpu/drm/radeon/atombios_crtc.c
··· 1184 1184 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1185 1185 1186 1186 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1187 - crtc->mode.vdisplay); 1187 + target_fb->height); 1188 1188 x &= ~3; 1189 1189 y &= ~1; 1190 1190 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, ··· 1353 1353 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1354 1354 1355 1355 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1356 - crtc->mode.vdisplay); 1356 + target_fb->height); 1357 1357 x &= ~3; 1358 1358 y &= ~1; 1359 1359 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
+15 -3
drivers/gpu/drm/radeon/atombios_dp.c
··· 564 564 ENCODER_OBJECT_ID_NUTMEG) 565 565 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 566 566 else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 567 - ENCODER_OBJECT_ID_TRAVIS) 568 - panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 569 - else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 567 + ENCODER_OBJECT_ID_TRAVIS) { 568 + u8 id[6]; 569 + int i; 570 + for (i = 0; i < 6; i++) 571 + id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i); 572 + if (id[0] == 0x73 && 573 + id[1] == 0x69 && 574 + id[2] == 0x76 && 575 + id[3] == 0x61 && 576 + id[4] == 0x72 && 577 + id[5] == 0x54) 578 + panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 579 + else 580 + panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 581 + } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 570 582 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 571 583 if (tmp & 1) 572 584 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+25 -10
drivers/gpu/drm/radeon/r600_blit_kms.c
··· 468 468 radeon_ring_write(ring, sq_stack_resource_mgmt_2); 469 469 } 470 470 471 + #define I2F_MAX_BITS 15 472 + #define I2F_MAX_INPUT ((1 << I2F_MAX_BITS) - 1) 473 + #define I2F_SHIFT (24 - I2F_MAX_BITS) 474 + 475 + /* 476 + * Converts unsigned integer into 32-bit IEEE floating point representation. 477 + * Conversion is not universal and only works for the range from 0 478 + * to 2^I2F_MAX_BITS-1. Currently we only use it with inputs between 479 + * 0 and 16384 (inclusive), so I2F_MAX_BITS=15 is enough. If necessary, 480 + * I2F_MAX_BITS can be increased, but that will add to the loop iterations 481 + * and slow us down. Conversion is done by shifting the input and counting 482 + * down until the first 1 reaches bit position 23. The resulting counter 483 + * and the shifted input are, respectively, the exponent and the fraction. 484 + * The sign is always zero. 485 + */ 471 486 static uint32_t i2f(uint32_t input) 472 487 { 473 488 u32 result, i, exponent, fraction; 474 489 475 - if ((input & 0x3fff) == 0) 476 - result = 0; /* 0 is a special case */ 490 + WARN_ON_ONCE(input > I2F_MAX_INPUT); 491 + 492 + if ((input & I2F_MAX_INPUT) == 0) 493 + result = 0; 477 494 else { 478 - exponent = 140; /* exponent biased by 127; */ 479 - fraction = (input & 0x3fff) << 10; /* cheat and only 480 - handle numbers below 2^^15 */ 481 - for (i = 0; i < 14; i++) { 495 + exponent = 126 + I2F_MAX_BITS; 496 + fraction = (input & I2F_MAX_INPUT) << I2F_SHIFT; 497 + 498 + for (i = 0; i < I2F_MAX_BITS; i++) { 482 499 if (fraction & 0x800000) 483 500 break; 484 501 else { 485 - fraction = fraction << 1; /* keep 486 - shifting left until top bit = 1 */ 502 + fraction = fraction << 1; 487 503 exponent = exponent - 1; 488 504 } 489 505 } 490 - result = exponent << 23 | (fraction & 0x7fffff); /* mask 491 - off top bit; assumed 1 */ 506 + result = exponent << 23 | (fraction & 0x7fffff); 492 507 } 493 508 return result; 494 509 }
+2 -1
drivers/gpu/drm/radeon/radeon_atpx_handler.c
··· 59 59 60 60 obj = (union acpi_object *)buffer.pointer; 61 61 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 62 + len = obj->buffer.length; 62 63 kfree(buffer.pointer); 63 - return obj->buffer.length; 64 + return len; 64 65 } 65 66 66 67 bool radeon_atrm_supported(struct pci_dev *pdev)
+4
drivers/gpu/drm/radeon/radeon_device.c
··· 883 883 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 884 884 return 0; 885 885 886 + drm_kms_helper_poll_disable(dev); 887 + 886 888 /* turn off display hw */ 887 889 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 888 890 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); ··· 974 972 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 975 973 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 976 974 } 975 + 976 + drm_kms_helper_poll_enable(dev); 977 977 return 0; 978 978 } 979 979
+1
drivers/gpu/drm/radeon/radeon_i2c.c
··· 958 958 i2c->rec = *rec; 959 959 i2c->adapter.owner = THIS_MODULE; 960 960 i2c->adapter.class = I2C_CLASS_DDC; 961 + i2c->adapter.dev.parent = &dev->pdev->dev; 961 962 i2c->dev = dev; 962 963 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 963 964 "Radeon aux bus %s", name);