tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/uvd7: add sriov uvd initialization sequences
Add UVD initialization for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Frank Min
and committed by
Alex Deucher
247ac951
7006dde2
+246
+246
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+246
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
···
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#include "amdgpu_uvd.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#include "mmsch_v1_0.h"
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#include "vega10/soc15ip.h"
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#include "vega10/UVD/uvd_7_0_offset.h"
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#include "vega10/UVD/uvd_7_0_sh_mask.h"
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#include "vega10/VCE/vce_4_0_offset.h"
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#include "vega10/VCE/vce_4_0_default.h"
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#include "vega10/VCE/vce_4_0_sh_mask.h"
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#include "vega10/NBIF/nbif_6_1_offset.h"
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#include "vega10/HDP/hdp_4_0_offset.h"
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#include "vega10/MMHUB/mmhub_1_0_offset.h"
···
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static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
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static int uvd_v7_0_start(struct amdgpu_device *adev);
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static void uvd_v7_0_stop(struct amdgpu_device *adev);
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static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
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/**
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* uvd_v7_0_ring_get_rptr - get read pointer
···
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adev->gfx.config.gb_addr_config);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
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}
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static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
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struct amdgpu_mm_table *table)
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{
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uint32_t data = 0, loop;
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uint64_t addr = table->gpu_addr;
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struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
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uint32_t size;
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size = header->header_size + header->vce_table_size + header->uvd_table_size;
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/* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));
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/* 2, update vmid of descriptor */
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data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
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data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
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data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
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/* 3, notify mmsch about the size of this descriptor */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);
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/* 4, set resp to zero */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
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/* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
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WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
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data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
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loop = 1000;
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while ((data & 0x10000002) != 0x10000002) {
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udelay(10);
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data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
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loop--;
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if (!loop)
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break;
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}
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if (!loop) {
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dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
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return -EBUSY;
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}
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return 0;
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}
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static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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uint32_t offset, size, tmp;
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uint32_t table_size = 0;
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struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
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struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
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struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
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//struct mmsch_v1_0_cmd_indirect_write indirect_wt = {{0}};
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struct mmsch_v1_0_cmd_end end = { {0} };
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uint32_t *init_table = adev->virt.mm_table.cpu_addr;
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struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
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direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
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direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
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direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
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end.cmd_header.command_type = MMSCH_COMMAND__END;
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if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
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header->version = MMSCH_VERSION;
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header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
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if (header->vce_table_offset == 0 && header->vce_table_size == 0)
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header->uvd_table_offset = header->header_size;
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else
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header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
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init_table += header->uvd_table_offset;
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ring = &adev->uvd.ring;
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size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
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/* disable clock gating */
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
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~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
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0xFFFFFFFF, 0x00000004);
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/* mc resume*/
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
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offset = 0;
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} else {
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
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lower_32_bits(adev->uvd.gpu_addr));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
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upper_32_bits(adev->uvd.gpu_addr));
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offset = size;
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}
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
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AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
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lower_32_bits(adev->uvd.gpu_addr + offset));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
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upper_32_bits(adev->uvd.gpu_addr + offset));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
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lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
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upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
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AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
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adev->gfx.config.gb_addr_config);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
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adev->gfx.config.gb_addr_config);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
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adev->gfx.config.gb_addr_config);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
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/* mc resume end*/
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/* disable clock gating */
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
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~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
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/* disable interupt */
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
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~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
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/* stall UMC and register bus before resetting VCPU */
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
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UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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/* put LMI, VCPU, RBC etc... into reset */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
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(uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
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UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
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UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
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UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
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UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
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UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
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UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
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/* initialize UVD memory controller */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
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(uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
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UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
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UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
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UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
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UVD_LMI_CTRL__REQ_MODE_MASK |
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0x00100000L));
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/* disable byte swapping */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), 0);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), 0);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
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+
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/* take all subblocks out of reset, except VCPU */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
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UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
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+
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/* enable VCPU clock */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
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UVD_VCPU_CNTL__CLK_EN_MASK);
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+
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/* enable UMC */
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
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+
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/* boot up the VCPU */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
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+
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MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
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+
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/* enable master interrupt */
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
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~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
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(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
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/* clear the bit 4 of UVD_STATUS */
815
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MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
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~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
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+
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/* force RBC into idle state */
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size = order_base_2(ring->ring_size);
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tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
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tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
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+
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/* set the write pointer delay */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
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+
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/* set the wb address */
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
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(upper_32_bits(ring->gpu_addr) >> 2));
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+
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/* programm the RB_BASE for ring buffer */
836
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
837
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lower_32_bits(ring->gpu_addr));
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
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upper_32_bits(ring->gpu_addr));
840
+
841
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ring->wptr = 0;
842
+
ring = &adev->uvd.ring_enc[0];
843
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
844
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
845
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
846
+
847
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ring = &adev->uvd.ring_enc[1];
848
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);
849
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MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
850
+
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);
851
+
852
+
/* add end packet */
853
+
memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
854
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table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
855
+
header->uvd_table_size = table_size;
856
+
857
+
return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
858
+
}
859
+
return -EINVAL; /* already initializaed ? */
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}
625
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862
/**