tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: net: Convert fsl-fman to yaml
Convert fsl-fman from txt to yaml format and split it fsl,fman.yam,
fsl,fman-port.yaml, fsl-muram.yaml, fsl-mdio.yaml.
Addition changes:
fsl,fman.yaml:
- Fixed interrupts in example.
- Fixed ethernet@e8000 miss } in example.
- ptp-timer add label in example.
- Ref to new fsl,fman*.yaml.
- Reorder property in example.
- Keep only one example.
- Add const for #address-cells and #size-cells.
- Use defined interrupt type.
- ptp example use node name phc.
fsl,fman-port:
- Keep only one example.
fsl,fman-mdio:
- Add little-endian property.
- Add ref to mdio.yaml.
- Remove suppress-preamble.
- Add #address-cells and #size-cells in example.
- Remove clock-frequency, which already describe in mmio.yaml.
fsl,muram.yaml:
- Add reg property.
- Remove range property.
- Use reg instead of range in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20240618-ls_fman-v2-2-f00a82623d8e@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Frank Li
and committed by
Jakub Kicinski
243996d1
01479f1b
+443
-549
+123
Documentation/devicetree/bindings/net/fsl,fman-mdio.yaml
+123
Documentation/devicetree/bindings/net/fsl,fman-mdio.yaml
···
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+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Frame Manager MDIO Device
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description: FMan MDIO Node.
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The MDIO is a bus to which the PHY devices are connected.
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properties:
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compatible:
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enum:
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- fsl,fman-mdio
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- fsl,fman-xmdio
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- fsl,fman-memac-mdio
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description:
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Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
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Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
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Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
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FMan v3.
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reg:
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maxItems: 1
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+
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clocks:
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items:
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- description: A reference to the input clock of the controller
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from which the MDC frequency is derived.
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+
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interrupts:
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maxItems: 1
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+
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fsl,fman-internal-mdio:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Fman has internal MDIO for internal PCS(Physical
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Coding Sublayer) PHYs and external MDIO for external PHYs.
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The settings and programming routines for internal/external
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MDIO are different. Must be included for internal MDIO.
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+
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fsl,erratum-a009885:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Indicates the presence of the A009885
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erratum describing that the contents of MDIO_DATA may
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become corrupt unless it is read within 16 MDC cycles
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of MDIO_CFG[BSY] being cleared, when performing an
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MDIO read operation.
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+
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fsl,erratum-a011043:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Indicates the presence of the A011043 erratum
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describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
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set when reading internal PCS registers. MDIO reads to
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internal PCS registers may result in having the
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MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
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read data (MDIO_DATA[MDIO_DATA]) is correct.
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Software may get false read error when reading internal
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PCS registers through MDIO. As a workaround, all internal
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MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
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For internal PHY device on internal mdio bus, a PHY node should be created.
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See the definition of the PHY node in booting-without-of.txt for an
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example of how to define a PHY (Internal PHY has no interrupt line).
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- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
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- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
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The PCS PHY address should correspond to the value of the appropriate
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MDEV_PORT.
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little-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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IP block is little-endian mode. The default endian mode is big-endian.
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required:
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- compatible
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- reg
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+
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allOf:
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- $ref: mdio.yaml#
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unevaluatedProperties: false
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examples:
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- |
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mdio@f1000 {
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compatible = "fsl,fman-xmdio";
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reg = <0xf1000 0x1000>;
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interrupts = <101 2 0 0>;
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};
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+
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- |
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mdio@e3120 {
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compatible = "fsl,fman-mdio";
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reg = <0xe3120 0xee0>;
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fsl,fman-internal-mdio;
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#address-cells = <1>;
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#size-cells = <0>;
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+
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tbi-phy@8 {
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reg = <0x8>;
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device_type = "tbi-phy";
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};
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};
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+
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- |
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mdio@f1000 {
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compatible = "fsl,fman-memac-mdio";
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reg = <0xf1000 0x1000>;
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fsl,fman-internal-mdio;
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#address-cells = <1>;
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#size-cells = <0>;
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+
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pcsphy6: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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+40
Documentation/devicetree/bindings/net/fsl,fman-muram.yaml
+40
Documentation/devicetree/bindings/net/fsl,fman-muram.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,fman-muram.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Frame Manager MURAM Device
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description: |
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FMan Internal memory - shared between all the FMan modules.
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It contains data structures that are common and written to or read by
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the modules.
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+
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FMan internal memory is split into the following parts:
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Packet buffering (Tx/Rx FIFOs)
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Frames internal context
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+
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properties:
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compatible:
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enum:
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- fsl,fman-muram
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+
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reg:
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maxItems: 1
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+
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required:
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- compatible
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- reg
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+
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additionalProperties: false
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+
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examples:
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- |
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muram@0 {
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compatible = "fsl,fman-muram";
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reg = <0x0 0x28000>;
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};
+75
Documentation/devicetree/bindings/net/fsl,fman-port.yaml
+75
Documentation/devicetree/bindings/net/fsl,fman-port.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,fman-port.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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title: Freescale Frame Manager Port Device
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+
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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+
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description: |
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The Frame Manager (FMan) supports several types of hardware ports:
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Ethernet receiver (RX)
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Ethernet transmitter (TX)
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Offline/Host command (O/H)
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+
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properties:
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compatible:
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enum:
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- fsl,fman-v2-port-oh
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- fsl,fman-v2-port-rx
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- fsl,fman-v2-port-tx
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- fsl,fman-v3-port-oh
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- fsl,fman-v3-port-rx
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- fsl,fman-v3-port-tx
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+
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Specifies the hardware port id.
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Each hardware port on the FMan has its own hardware PortID.
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Super set of all hardware Port IDs available at FMan Reference
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Manual under "FMan Hardware Ports in Freescale Devices" table.
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+
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Each hardware port is assigned a 4KB, port-specific page in
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the FMan hardware port memory region (which is part of the
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FMan memory map). The first 4 KB in the FMan hardware ports
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memory region is used for what are called common registers.
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The subsequent 63 4KB pages are allocated to the hardware
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ports.
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The page of a specific port is determined by the cell-index.
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+
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reg:
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items:
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- description: There is one reg region describing the port
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configuration registers.
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+
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fsl,fman-10g-port:
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$ref: /schemas/types.yaml#/definitions/flag
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description: The default port rate is 1G.
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If this property exists, the port is s 10G port.
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+
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fsl,fman-best-effort-port:
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$ref: /schemas/types.yaml#/definitions/flag
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description: The default port rate is 1G.
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Can be defined only if 10G-support is set.
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This property marks a best-effort 10G port (10G port that
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may not be capable of line rate).
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+
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required:
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- compatible
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- reg
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- cell-index
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+
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additionalProperties: false
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+
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examples:
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- |
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port@a8000 {
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compatible = "fsl,fman-v2-port-tx";
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reg = <0xa8000 0x1000>;
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cell-index = <0x28>;
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};
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+
+204
Documentation/devicetree/bindings/net/fsl,fman.yaml
+204
Documentation/devicetree/bindings/net/fsl,fman.yaml
···
1
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,fman.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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title: Freescale Frame Manager Device
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+
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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+
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description:
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Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
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etc.) the FMan node will have child nodes for each of them.
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+
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properties:
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compatible:
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enum:
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- fsl,fman
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description:
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FMan version can be determined via FM_IP_REV_1 register in the
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FMan block. The offset is 0xc4 from the beginning of the
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Frame Processing Manager memory map (0xc3000 from the
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beginning of the FMan node).
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+
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Specifies the index of the FMan unit.
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+
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The cell-index value may be used by the SoC, to identify the
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FMan unit in the SoC memory map. In the table below,
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there's a description of the cell-index use in each SoC:
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+
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- P1023:
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register[bit] FMan unit cell-index
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============================================================
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DEVDISR[1] 1 0
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+
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- P2041, P3041, P4080 P5020, P5040:
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register[bit] FMan unit cell-index
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============================================================
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DCFG_DEVDISR2[6] 1 0
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DCFG_DEVDISR2[14] 2 1
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(Second FM available only in P4080 and P5040)
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+
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- B4860, T1040, T2080, T4240:
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register[bit] FMan unit cell-index
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============================================================
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DCFG_CCSR_DEVDISR2[24] 1 0
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DCFG_CCSR_DEVDISR2[25] 2 1
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(Second FM available only in T4240)
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+
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DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
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the specific SoC "Device Configuration/Pin Control" Memory
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Map.
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+
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reg:
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items:
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- description: BMI configuration registers.
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- description: QMI configuration registers.
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- description: DMA configuration registers.
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- description: FPM configuration registers.
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- description: FMan controller configuration registers.
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minItems: 1
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+
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ranges: true
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+
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clocks:
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maxItems: 1
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+
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clock-names:
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items:
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- const: fmanclk
75
+
76
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interrupts:
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items:
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- description: The first element is associated with the event interrupts.
79
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- description: the second element is associated with the error interrupts.
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+
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+
fsl,qman-channel-range:
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$ref: /schemas/types.yaml#/definitions/uint32-array
83
+
description:
84
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Specifies the range of the available dedicated
85
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channels in the FMan. The first cell specifies the beginning
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+
of the range and the second cell specifies the number of
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+
channels
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items:
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- description: The first cell specifies the beginning of the range.
90
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- description: |
91
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The second cell specifies the number of channels.
92
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Further information available at:
93
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"Work Queue (WQ) Channel Assignments in the QMan" section
94
+
in DPAA Reference Manual.
95
+
96
+
fsl,qman:
97
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$ref: /schemas/types.yaml#/definitions/phandle
98
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description: See soc/fsl/qman.txt
99
+
100
+
fsl,bman:
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$ref: /schemas/types.yaml#/definitions/phandle
102
+
description: See soc/fsl/bman.txt
103
+
104
+
fsl,erratum-a050385:
105
+
$ref: /schemas/types.yaml#/definitions/flag
106
+
description: A boolean property. Indicates the presence of the
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erratum A050385 which indicates that DMA transactions that are
108
+
split can result in a FMan lock.
109
+
110
+
'#address-cells':
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const: 1
112
+
113
+
'#size-cells':
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+
const: 1
115
+
116
+
patternProperties:
117
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'^muram@[a-f0-9]+$':
118
+
$ref: fsl,fman-muram.yaml
119
+
120
+
'^port@[a-f0-9]+$':
121
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$ref: fsl,fman-port.yaml
122
+
123
+
'^ethernet@[a-f0-9]+$':
124
+
$ref: fsl,fman-dtsec.yaml
125
+
126
+
'^mdio@[a-f0-9]+$':
127
+
$ref: fsl,fman-mdio.yaml
128
+
129
+
'^phc@[a-f0-9]+$':
130
+
$ref: /schemas/ptp/fsl,ptp.yaml
131
+
132
+
required:
133
+
- compatible
134
+
- cell-index
135
+
- reg
136
+
- ranges
137
+
- clocks
138
+
- clock-names
139
+
- interrupts
140
+
- fsl,qman-channel-range
141
+
142
+
additionalProperties: false
143
+
144
+
examples:
145
+
- |
146
+
#include <dt-bindings/interrupt-controller/irq.h>
147
+
148
+
fman@400000 {
149
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compatible = "fsl,fman";
150
+
reg = <0x400000 0x100000>;
151
+
ranges = <0 0x400000 0x100000>;
152
+
#address-cells = <1>;
153
+
#size-cells = <1>;
154
+
cell-index = <1>;
155
+
clocks = <&fman_clk>;
156
+
clock-names = "fmanclk";
157
+
interrupts = <96 IRQ_TYPE_EDGE_FALLING>,
158
+
<16 IRQ_TYPE_EDGE_FALLING>;
159
+
fsl,qman-channel-range = <0x40 0xc>;
160
+
161
+
muram@0 {
162
+
compatible = "fsl,fman-muram";
163
+
reg = <0x0 0x28000>;
164
+
};
165
+
166
+
port@81000 {
167
+
cell-index = <1>;
168
+
compatible = "fsl,fman-v2-port-oh";
169
+
reg = <0x81000 0x1000>;
170
+
};
171
+
172
+
fman1_rx_0x8: port@88000 {
173
+
cell-index = <0x8>;
174
+
compatible = "fsl,fman-v2-port-rx";
175
+
reg = <0x88000 0x1000>;
176
+
};
177
+
178
+
fman1_tx_0x28: port@a8000 {
179
+
cell-index = <0x28>;
180
+
compatible = "fsl,fman-v2-port-tx";
181
+
reg = <0xa8000 0x1000>;
182
+
};
183
+
184
+
ethernet@e0000 {
185
+
compatible = "fsl,fman-dtsec";
186
+
cell-index = <0>;
187
+
reg = <0xe0000 0x1000>;
188
+
ptp-timer = <&ptp_timer>;
189
+
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
190
+
tbi-handle = <&tbi5>;
191
+
};
192
+
193
+
ptp_timer: phc@fe000 {
194
+
compatible = "fsl,fman-ptp-timer";
195
+
reg = <0xfe000 0x1000>;
196
+
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
197
+
};
198
+
199
+
mdio@f1000 {
200
+
compatible = "fsl,fman-xmdio";
201
+
reg = <0xf1000 0x1000>;
202
+
interrupts = <101 IRQ_TYPE_EDGE_FALLING>;
203
+
};
204
+
};
-548
Documentation/devicetree/bindings/net/fsl-fman.txt
-548
Documentation/devicetree/bindings/net/fsl-fman.txt
···
1
-
=============================================================================
2
-
Freescale Frame Manager Device Bindings
3
-
4
-
CONTENTS
5
-
- FMan Node
6
-
- FMan Port Node
7
-
- FMan MURAM Node
8
-
- FMan dTSEC/XGEC/mEMAC Node
9
-
- FMan IEEE 1588 Node
10
-
- FMan MDIO Node
11
-
- Example
12
-
13
-
=============================================================================
14
-
FMan Node
15
-
16
-
DESCRIPTION
17
-
18
-
Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19
-
etc.) the FMan node will have child nodes for each of them.
20
-
21
-
PROPERTIES
22
-
23
-
- compatible
24
-
Usage: required
25
-
Value type: <stringlist>
26
-
Definition: Must include "fsl,fman"
27
-
FMan version can be determined via FM_IP_REV_1 register in the
28
-
FMan block. The offset is 0xc4 from the beginning of the
29
-
Frame Processing Manager memory map (0xc3000 from the
30
-
beginning of the FMan node).
31
-
32
-
- cell-index
33
-
Usage: required
34
-
Value type: <u32>
35
-
Definition: Specifies the index of the FMan unit.
36
-
37
-
The cell-index value may be used by the SoC, to identify the
38
-
FMan unit in the SoC memory map. In the table below,
39
-
there's a description of the cell-index use in each SoC:
40
-
41
-
- P1023:
42
-
register[bit] FMan unit cell-index
43
-
============================================================
44
-
DEVDISR[1] 1 0
45
-
46
-
- P2041, P3041, P4080 P5020, P5040:
47
-
register[bit] FMan unit cell-index
48
-
============================================================
49
-
DCFG_DEVDISR2[6] 1 0
50
-
DCFG_DEVDISR2[14] 2 1
51
-
(Second FM available only in P4080 and P5040)
52
-
53
-
- B4860, T1040, T2080, T4240:
54
-
register[bit] FMan unit cell-index
55
-
============================================================
56
-
DCFG_CCSR_DEVDISR2[24] 1 0
57
-
DCFG_CCSR_DEVDISR2[25] 2 1
58
-
(Second FM available only in T4240)
59
-
60
-
DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
61
-
the specific SoC "Device Configuration/Pin Control" Memory
62
-
Map.
63
-
64
-
- reg
65
-
Usage: required
66
-
Value type: <prop-encoded-array>
67
-
Definition: A standard property. Specifies the offset of the
68
-
following configuration registers:
69
-
- BMI configuration registers.
70
-
- QMI configuration registers.
71
-
- DMA configuration registers.
72
-
- FPM configuration registers.
73
-
- FMan controller configuration registers.
74
-
75
-
- ranges
76
-
Usage: required
77
-
Value type: <prop-encoded-array>
78
-
Definition: A standard property.
79
-
80
-
- clocks
81
-
Usage: required
82
-
Value type: <prop-encoded-array>
83
-
Definition: phandle for the fman input clock.
84
-
85
-
- clock-names
86
-
usage: required
87
-
Value type: <stringlist>
88
-
Definition: "fmanclk" for the fman input clock.
89
-
90
-
- interrupts
91
-
Usage: required
92
-
Value type: <prop-encoded-array>
93
-
Definition: A pair of IRQs are specified in this property.
94
-
The first element is associated with the event interrupts and
95
-
the second element is associated with the error interrupts.
96
-
97
-
- fsl,qman-channel-range
98
-
Usage: required
99
-
Value type: <prop-encoded-array>
100
-
Definition: Specifies the range of the available dedicated
101
-
channels in the FMan. The first cell specifies the beginning
102
-
of the range and the second cell specifies the number of
103
-
channels.
104
-
Further information available at:
105
-
"Work Queue (WQ) Channel Assignments in the QMan" section
106
-
in DPAA Reference Manual.
107
-
108
-
- fsl,qman
109
-
- fsl,bman
110
-
Usage: required
111
-
Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
112
-
113
-
- fsl,erratum-a050385
114
-
Usage: optional
115
-
Value type: boolean
116
-
Definition: A boolean property. Indicates the presence of the
117
-
erratum A050385 which indicates that DMA transactions that are
118
-
split can result in a FMan lock.
119
-
120
-
=============================================================================
121
-
FMan MURAM Node
122
-
123
-
DESCRIPTION
124
-
125
-
FMan Internal memory - shared between all the FMan modules.
126
-
It contains data structures that are common and written to or read by
127
-
the modules.
128
-
FMan internal memory is split into the following parts:
129
-
Packet buffering (Tx/Rx FIFOs)
130
-
Frames internal context
131
-
132
-
PROPERTIES
133
-
134
-
- compatible
135
-
Usage: required
136
-
Value type: <stringlist>
137
-
Definition: Must include "fsl,fman-muram"
138
-
139
-
- ranges
140
-
Usage: required
141
-
Value type: <prop-encoded-array>
142
-
Definition: A standard property.
143
-
Specifies the multi-user memory offset and the size within
144
-
the FMan.
145
-
146
-
EXAMPLE
147
-
148
-
muram@0 {
149
-
compatible = "fsl,fman-muram";
150
-
ranges = <0 0x000000 0x28000>;
151
-
};
152
-
153
-
=============================================================================
154
-
FMan Port Node
155
-
156
-
DESCRIPTION
157
-
158
-
The Frame Manager (FMan) supports several types of hardware ports:
159
-
Ethernet receiver (RX)
160
-
Ethernet transmitter (TX)
161
-
Offline/Host command (O/H)
162
-
163
-
PROPERTIES
164
-
165
-
- compatible
166
-
Usage: required
167
-
Value type: <stringlist>
168
-
Definition: A standard property.
169
-
Must include one of the following:
170
-
- "fsl,fman-v2-port-oh" for FManV2 OH ports
171
-
- "fsl,fman-v2-port-rx" for FManV2 RX ports
172
-
- "fsl,fman-v2-port-tx" for FManV2 TX ports
173
-
- "fsl,fman-v3-port-oh" for FManV3 OH ports
174
-
- "fsl,fman-v3-port-rx" for FManV3 RX ports
175
-
- "fsl,fman-v3-port-tx" for FManV3 TX ports
176
-
177
-
- cell-index
178
-
Usage: required
179
-
Value type: <u32>
180
-
Definition: Specifies the hardware port id.
181
-
Each hardware port on the FMan has its own hardware PortID.
182
-
Super set of all hardware Port IDs available at FMan Reference
183
-
Manual under "FMan Hardware Ports in Freescale Devices" table.
184
-
185
-
Each hardware port is assigned a 4KB, port-specific page in
186
-
the FMan hardware port memory region (which is part of the
187
-
FMan memory map). The first 4 KB in the FMan hardware ports
188
-
memory region is used for what are called common registers.
189
-
The subsequent 63 4KB pages are allocated to the hardware
190
-
ports.
191
-
The page of a specific port is determined by the cell-index.
192
-
193
-
- reg
194
-
Usage: required
195
-
Value type: <prop-encoded-array>
196
-
Definition: There is one reg region describing the port
197
-
configuration registers.
198
-
199
-
- fsl,fman-10g-port
200
-
Usage: optional
201
-
Value type: boolean
202
-
Definition: The default port rate is 1G.
203
-
If this property exists, the port is s 10G port.
204
-
205
-
- fsl,fman-best-effort-port
206
-
Usage: optional
207
-
Value type: boolean
208
-
Definition: Can be defined only if 10G-support is set.
209
-
This property marks a best-effort 10G port (10G port that
210
-
may not be capable of line rate).
211
-
212
-
EXAMPLE
213
-
214
-
port@a8000 {
215
-
cell-index = <0x28>;
216
-
compatible = "fsl,fman-v2-port-tx";
217
-
reg = <0xa8000 0x1000>;
218
-
};
219
-
220
-
port@88000 {
221
-
cell-index = <0x8>;
222
-
compatible = "fsl,fman-v2-port-rx";
223
-
reg = <0x88000 0x1000>;
224
-
};
225
-
226
-
port@81000 {
227
-
cell-index = <0x1>;
228
-
compatible = "fsl,fman-v2-port-oh";
229
-
reg = <0x81000 0x1000>;
230
-
};
231
-
232
-
=============================================================================
233
-
FMan dTSEC/XGEC/mEMAC Node
234
-
235
-
Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
236
-
237
-
============================================================================
238
-
FMan IEEE 1588 Node
239
-
240
-
Refer to Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
241
-
242
-
=============================================================================
243
-
FMan MDIO Node
244
-
245
-
DESCRIPTION
246
-
247
-
The MDIO is a bus to which the PHY devices are connected.
248
-
249
-
PROPERTIES
250
-
251
-
- compatible
252
-
Usage: required
253
-
Value type: <stringlist>
254
-
Definition: A standard property.
255
-
Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
256
-
Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
257
-
Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
258
-
FMan v3.
259
-
260
-
- reg
261
-
Usage: required
262
-
Value type: <prop-encoded-array>
263
-
Definition: A standard property.
264
-
265
-
- clocks
266
-
Usage: optional
267
-
Value type: <phandle>
268
-
Definition: A reference to the input clock of the controller
269
-
from which the MDC frequency is derived.
270
-
271
-
- clock-frequency
272
-
Usage: optional
273
-
Value type: <u32>
274
-
Definition: Specifies the external MDC frequency, in Hertz, to
275
-
be used. Requires that the input clock is specified in the
276
-
"clocks" property. See also: mdio.yaml.
277
-
278
-
- suppress-preamble
279
-
Usage: optional
280
-
Value type: <boolean>
281
-
Definition: Disable generation of preamble bits. See also:
282
-
mdio.yaml.
283
-
284
-
- interrupts
285
-
Usage: required for external MDIO
286
-
Value type: <prop-encoded-array>
287
-
Definition: Event interrupt of external MDIO controller.
288
-
289
-
- fsl,fman-internal-mdio
290
-
Usage: required for internal MDIO
291
-
Value type: boolean
292
-
Definition: Fman has internal MDIO for internal PCS(Physical
293
-
Coding Sublayer) PHYs and external MDIO for external PHYs.
294
-
The settings and programming routines for internal/external
295
-
MDIO are different. Must be included for internal MDIO.
296
-
297
-
- fsl,erratum-a009885
298
-
Usage: optional
299
-
Value type: <boolean>
300
-
Definition: Indicates the presence of the A009885
301
-
erratum describing that the contents of MDIO_DATA may
302
-
become corrupt unless it is read within 16 MDC cycles
303
-
of MDIO_CFG[BSY] being cleared, when performing an
304
-
MDIO read operation.
305
-
306
-
- fsl,erratum-a011043
307
-
Usage: optional
308
-
Value type: <boolean>
309
-
Definition: Indicates the presence of the A011043 erratum
310
-
describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
311
-
set when reading internal PCS registers. MDIO reads to
312
-
internal PCS registers may result in having the
313
-
MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
314
-
read data (MDIO_DATA[MDIO_DATA]) is correct.
315
-
Software may get false read error when reading internal
316
-
PCS registers through MDIO. As a workaround, all internal
317
-
MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
318
-
319
-
For internal PHY device on internal mdio bus, a PHY node should be created.
320
-
See the definition of the PHY node in booting-without-of.txt for an
321
-
example of how to define a PHY (Internal PHY has no interrupt line).
322
-
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
323
-
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
324
-
The PCS PHY address should correspond to the value of the appropriate
325
-
MDEV_PORT.
326
-
327
-
EXAMPLE
328
-
329
-
Example for FMan v2 external MDIO:
330
-
331
-
mdio@f1000 {
332
-
compatible = "fsl,fman-xmdio";
333
-
reg = <0xf1000 0x1000>;
334
-
interrupts = <101 2 0 0>;
335
-
};
336
-
337
-
Example for FMan v2 internal MDIO:
338
-
339
-
mdio@e3120 {
340
-
compatible = "fsl,fman-mdio";
341
-
reg = <0xe3120 0xee0>;
342
-
fsl,fman-internal-mdio;
343
-
344
-
tbi1: tbi-phy@8 {
345
-
reg = <0x8>;
346
-
device_type = "tbi-phy";
347
-
};
348
-
};
349
-
350
-
Example for FMan v3 internal MDIO:
351
-
352
-
mdio@f1000 {
353
-
compatible = "fsl,fman-memac-mdio";
354
-
reg = <0xf1000 0x1000>;
355
-
fsl,fman-internal-mdio;
356
-
357
-
pcsphy6: ethernet-phy@0 {
358
-
reg = <0x0>;
359
-
};
360
-
};
361
-
362
-
=============================================================================
363
-
Example
364
-
365
-
fman@400000 {
366
-
#address-cells = <1>;
367
-
#size-cells = <1>;
368
-
cell-index = <1>;
369
-
compatible = "fsl,fman"
370
-
ranges = <0 0x400000 0x100000>;
371
-
reg = <0x400000 0x100000>;
372
-
clocks = <&fman_clk>;
373
-
clock-names = "fmanclk";
374
-
interrupts = <
375
-
96 2 0 0
376
-
16 2 1 1>;
377
-
fsl,qman-channel-range = <0x40 0xc>;
378
-
379
-
muram@0 {
380
-
compatible = "fsl,fman-muram";
381
-
reg = <0x0 0x28000>;
382
-
};
383
-
384
-
port@81000 {
385
-
cell-index = <1>;
386
-
compatible = "fsl,fman-v2-port-oh";
387
-
reg = <0x81000 0x1000>;
388
-
};
389
-
390
-
port@82000 {
391
-
cell-index = <2>;
392
-
compatible = "fsl,fman-v2-port-oh";
393
-
reg = <0x82000 0x1000>;
394
-
};
395
-
396
-
port@83000 {
397
-
cell-index = <3>;
398
-
compatible = "fsl,fman-v2-port-oh";
399
-
reg = <0x83000 0x1000>;
400
-
};
401
-
402
-
port@84000 {
403
-
cell-index = <4>;
404
-
compatible = "fsl,fman-v2-port-oh";
405
-
reg = <0x84000 0x1000>;
406
-
};
407
-
408
-
port@85000 {
409
-
cell-index = <5>;
410
-
compatible = "fsl,fman-v2-port-oh";
411
-
reg = <0x85000 0x1000>;
412
-
};
413
-
414
-
port@86000 {
415
-
cell-index = <6>;
416
-
compatible = "fsl,fman-v2-port-oh";
417
-
reg = <0x86000 0x1000>;
418
-
};
419
-
420
-
fman1_rx_0x8: port@88000 {
421
-
cell-index = <0x8>;
422
-
compatible = "fsl,fman-v2-port-rx";
423
-
reg = <0x88000 0x1000>;
424
-
};
425
-
426
-
fman1_rx_0x9: port@89000 {
427
-
cell-index = <0x9>;
428
-
compatible = "fsl,fman-v2-port-rx";
429
-
reg = <0x89000 0x1000>;
430
-
};
431
-
432
-
fman1_rx_0xa: port@8a000 {
433
-
cell-index = <0xa>;
434
-
compatible = "fsl,fman-v2-port-rx";
435
-
reg = <0x8a000 0x1000>;
436
-
};
437
-
438
-
fman1_rx_0xb: port@8b000 {
439
-
cell-index = <0xb>;
440
-
compatible = "fsl,fman-v2-port-rx";
441
-
reg = <0x8b000 0x1000>;
442
-
};
443
-
444
-
fman1_rx_0xc: port@8c000 {
445
-
cell-index = <0xc>;
446
-
compatible = "fsl,fman-v2-port-rx";
447
-
reg = <0x8c000 0x1000>;
448
-
};
449
-
450
-
fman1_rx_0x10: port@90000 {
451
-
cell-index = <0x10>;
452
-
compatible = "fsl,fman-v2-port-rx";
453
-
reg = <0x90000 0x1000>;
454
-
};
455
-
456
-
fman1_tx_0x28: port@a8000 {
457
-
cell-index = <0x28>;
458
-
compatible = "fsl,fman-v2-port-tx";
459
-
reg = <0xa8000 0x1000>;
460
-
};
461
-
462
-
fman1_tx_0x29: port@a9000 {
463
-
cell-index = <0x29>;
464
-
compatible = "fsl,fman-v2-port-tx";
465
-
reg = <0xa9000 0x1000>;
466
-
};
467
-
468
-
fman1_tx_0x2a: port@aa000 {
469
-
cell-index = <0x2a>;
470
-
compatible = "fsl,fman-v2-port-tx";
471
-
reg = <0xaa000 0x1000>;
472
-
};
473
-
474
-
fman1_tx_0x2b: port@ab000 {
475
-
cell-index = <0x2b>;
476
-
compatible = "fsl,fman-v2-port-tx";
477
-
reg = <0xab000 0x1000>;
478
-
};
479
-
480
-
fman1_tx_0x2c: port@ac0000 {
481
-
cell-index = <0x2c>;
482
-
compatible = "fsl,fman-v2-port-tx";
483
-
reg = <0xac000 0x1000>;
484
-
};
485
-
486
-
fman1_tx_0x30: port@b0000 {
487
-
cell-index = <0x30>;
488
-
compatible = "fsl,fman-v2-port-tx";
489
-
reg = <0xb0000 0x1000>;
490
-
};
491
-
492
-
ethernet@e0000 {
493
-
compatible = "fsl,fman-dtsec";
494
-
cell-index = <0>;
495
-
reg = <0xe0000 0x1000>;
496
-
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
497
-
tbi-handle = <&tbi5>;
498
-
};
499
-
500
-
ethernet@e2000 {
501
-
compatible = "fsl,fman-dtsec";
502
-
cell-index = <1>;
503
-
reg = <0xe2000 0x1000>;
504
-
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
505
-
tbi-handle = <&tbi6>;
506
-
};
507
-
508
-
ethernet@e4000 {
509
-
compatible = "fsl,fman-dtsec";
510
-
cell-index = <2>;
511
-
reg = <0xe4000 0x1000>;
512
-
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
513
-
tbi-handle = <&tbi7>;
514
-
};
515
-
516
-
ethernet@e6000 {
517
-
compatible = "fsl,fman-dtsec";
518
-
cell-index = <3>;
519
-
reg = <0xe6000 0x1000>;
520
-
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
521
-
tbi-handle = <&tbi8>;
522
-
};
523
-
524
-
ethernet@e8000 {
525
-
compatible = "fsl,fman-dtsec";
526
-
cell-index = <4>;
527
-
reg = <0xf0000 0x1000>;
528
-
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
529
-
tbi-handle = <&tbi9>;
530
-
531
-
ethernet@f0000 {
532
-
cell-index = <8>;
533
-
compatible = "fsl,fman-xgec";
534
-
reg = <0xf0000 0x1000>;
535
-
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
536
-
};
537
-
538
-
ptp-timer@fe000 {
539
-
compatible = "fsl,fman-ptp-timer";
540
-
reg = <0xfe000 0x1000>;
541
-
};
542
-
543
-
mdio@f1000 {
544
-
compatible = "fsl,fman-xmdio";
545
-
reg = <0xf1000 0x1000>;
546
-
interrupts = <101 2 0 0>;
547
-
};
548
-
};
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
8809
8809
R: Sean Anderson <sean.anderson@seco.com>
8810
8810
L: netdev@vger.kernel.org
8811
8811
S: Maintained
8812
-
F: Documentation/devicetree/bindings/net/fsl-fman.txt
8812
+
F: Documentation/devicetree/bindings/net/fsl-fman.yaml
8813
8813
F: drivers/net/ethernet/freescale/fman
8814
8814
8815
8815
FREESCALE QORIQ PTP CLOCK DRIVER