tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: rockchip: Add clock controller support for RV1126 SoC
Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.
This patch is trying to add minimal Clock-Architecture Diagram's
inferred from [1] authored by Finley Xiao.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220915163947.1922183-5-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Jagan Teki
and committed by
Heiko Stuebner
2408ab5a
a1f65e64
+1165
+7
drivers/clk/rockchip/Kconfig
+7
drivers/clk/rockchip/Kconfig
···
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help
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Build the driver for RV110x Clock Driver.
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config CLK_RV1126
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bool "Rockchip RV1126 clock controller support"
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depends on ARM || COMPILE_TEST
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default y
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help
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Build the driver for RV1126 Clock Driver.
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+
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config CLK_RK3036
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bool "Rockchip RK3036 clock controller support"
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depends on ARM || COMPILE_TEST
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
+1138
drivers/clk/rockchip/clk-rv1126.c
+1138
drivers/clk/rockchip/clk-rv1126.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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+
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/rockchip,rv1126-cru.h>
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#include "clk.h"
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+
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#define RV1126_GMAC_CON 0x460
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#define RV1126_GRF_IOFUNC_CON1 0x10264
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#define RV1126_GRF_SOC_STATUS0 0x10
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+
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#define RV1126_FRAC_MAX_PRATE 1200000000
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#define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
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+
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enum rv1126_pmu_plls {
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gpll,
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};
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+
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enum rv1126_plls {
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apll, dpll, cpll, hpll,
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};
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+
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static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
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/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
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RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
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RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
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RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
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RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
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RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
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RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
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RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
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RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
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RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
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RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
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RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
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RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
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RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
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RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
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RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
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RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
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RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
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RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
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RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
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RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
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RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
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RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
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RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
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RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
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RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
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RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
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RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
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RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
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RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
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RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
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RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
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RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
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RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
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RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
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RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
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RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
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RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
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RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
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RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
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RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
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RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
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RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
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RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
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{ /* sentinel */ },
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};
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#define RV1126_DIV_ACLK_CORE_MASK 0xf
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#define RV1126_DIV_ACLK_CORE_SHIFT 4
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#define RV1126_DIV_PCLK_DBG_MASK 0x7
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#define RV1126_DIV_PCLK_DBG_SHIFT 0
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+
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#define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
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{ \
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.reg = RV1126_CLKSEL_CON(1), \
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.val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
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RV1126_DIV_ACLK_CORE_SHIFT) | \
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HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
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RV1126_DIV_PCLK_DBG_SHIFT), \
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}
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+
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#define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
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{ \
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.prate = _prate, \
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.divs = { \
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RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
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}, \
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}
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static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
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RV1126_CPUCLK_RATE(1608000000, 1, 7),
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RV1126_CPUCLK_RATE(1584000000, 1, 7),
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RV1126_CPUCLK_RATE(1560000000, 1, 7),
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RV1126_CPUCLK_RATE(1536000000, 1, 7),
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RV1126_CPUCLK_RATE(1512000000, 1, 7),
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RV1126_CPUCLK_RATE(1488000000, 1, 5),
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RV1126_CPUCLK_RATE(1464000000, 1, 5),
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RV1126_CPUCLK_RATE(1440000000, 1, 5),
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RV1126_CPUCLK_RATE(1416000000, 1, 5),
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RV1126_CPUCLK_RATE(1392000000, 1, 5),
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RV1126_CPUCLK_RATE(1368000000, 1, 5),
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RV1126_CPUCLK_RATE(1344000000, 1, 5),
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RV1126_CPUCLK_RATE(1320000000, 1, 5),
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RV1126_CPUCLK_RATE(1296000000, 1, 5),
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RV1126_CPUCLK_RATE(1272000000, 1, 5),
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RV1126_CPUCLK_RATE(1248000000, 1, 5),
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RV1126_CPUCLK_RATE(1224000000, 1, 5),
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RV1126_CPUCLK_RATE(1200000000, 1, 5),
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RV1126_CPUCLK_RATE(1104000000, 1, 5),
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RV1126_CPUCLK_RATE(1008000000, 1, 5),
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RV1126_CPUCLK_RATE(912000000, 1, 5),
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RV1126_CPUCLK_RATE(816000000, 1, 3),
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RV1126_CPUCLK_RATE(696000000, 1, 3),
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RV1126_CPUCLK_RATE(600000000, 1, 3),
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RV1126_CPUCLK_RATE(408000000, 1, 1),
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RV1126_CPUCLK_RATE(312000000, 1, 1),
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RV1126_CPUCLK_RATE(216000000, 1, 1),
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RV1126_CPUCLK_RATE(96000000, 1, 1),
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};
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static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
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.core_reg[0] = RV1126_CLKSEL_CON(0),
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.div_core_shift[0] = 0,
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.div_core_mask[0] = 0x1f,
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.num_cores = 1,
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.mux_core_alt = 0,
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.mux_core_main = 2,
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.mux_core_shift = 6,
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.mux_core_mask = 0x3,
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};
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+
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PNAME(mux_pll_p) = { "xin24m" };
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PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
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PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
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PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
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PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
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PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
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PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
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PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
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PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
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PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
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PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
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PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
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PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
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PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
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PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
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PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
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PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
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PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
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PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
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PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
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PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
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PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
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PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
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PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
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PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
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PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
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PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
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PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
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PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
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PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
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PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
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PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
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PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
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PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
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PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
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PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
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PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
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PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
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PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
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PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
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PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
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+
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static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
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+
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static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
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[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
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0, RV1126_PMU_PLL_CON(0),
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RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
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};
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+
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static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
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[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
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0, RV1126_PLL_CON(0),
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RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
199
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[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
200
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0, RV1126_PLL_CON(8),
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RV1126_MODE_CON, 2, 1, 0, NULL),
202
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[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
203
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0, RV1126_PLL_CON(16),
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RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
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[hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
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0, RV1126_PLL_CON(24),
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RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
208
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};
209
+
210
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#define MFLAGS CLK_MUX_HIWORD_MASK
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#define DFLAGS CLK_DIVIDER_HIWORD_MASK
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#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
213
+
214
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static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
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MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
216
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RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
217
+
218
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static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
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MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
220
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RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
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+
222
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static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
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MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
224
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RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
225
+
226
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static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
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MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
228
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RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
229
+
230
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static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
231
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MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
232
+
RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
233
+
234
+
static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
235
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MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
236
+
RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
237
+
238
+
static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
239
+
MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
240
+
RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
241
+
242
+
static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
243
+
MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
244
+
RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
245
+
246
+
static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
247
+
MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
248
+
RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
249
+
250
+
static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
251
+
MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
252
+
RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
253
+
254
+
static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
255
+
MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
256
+
RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
257
+
258
+
static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
259
+
MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
260
+
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
261
+
262
+
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
263
+
/*
264
+
* Clock-Architecture Diagram 2
265
+
*/
266
+
/* PD_PMU */
267
+
COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
268
+
RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
269
+
RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
270
+
271
+
COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
272
+
RV1126_PMU_CLKSEL_CON(13), 0,
273
+
RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
274
+
&rv1126_rtc32k_fracmux),
275
+
276
+
COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
277
+
RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
278
+
RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
279
+
GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
280
+
RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
281
+
MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
282
+
RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
283
+
284
+
GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
285
+
RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
286
+
287
+
GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
288
+
RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
289
+
COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
290
+
RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
291
+
RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
292
+
COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div",
293
+
CLK_SET_RATE_PARENT,
294
+
RV1126_PMU_CLKSEL_CON(5), 0,
295
+
RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
296
+
&rv1126_uart1_fracmux),
297
+
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
298
+
RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
299
+
300
+
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
301
+
RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
302
+
COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
303
+
RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
304
+
RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
305
+
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
306
+
RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
307
+
COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
308
+
RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
309
+
RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
310
+
311
+
GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
312
+
RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
313
+
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
314
+
RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
315
+
COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
316
+
RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
317
+
RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
318
+
GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
319
+
RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
320
+
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
321
+
RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
322
+
COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
323
+
RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
324
+
RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
325
+
326
+
GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
327
+
RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
328
+
COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
329
+
RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
330
+
RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
331
+
332
+
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
333
+
RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
334
+
COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
335
+
RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
336
+
RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
337
+
338
+
GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
339
+
RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
340
+
GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
341
+
RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
342
+
GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
343
+
RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
344
+
345
+
COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
346
+
RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
347
+
RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
348
+
GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
349
+
RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
350
+
GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
351
+
RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
352
+
FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
353
+
FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
354
+
MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
355
+
RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
356
+
MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
357
+
RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
358
+
359
+
COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
360
+
RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
361
+
RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
362
+
GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
363
+
RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
364
+
MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
365
+
RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
366
+
367
+
GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
368
+
RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
369
+
370
+
GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
371
+
RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
372
+
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
373
+
RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
374
+
GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
375
+
RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
376
+
GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
377
+
RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
378
+
GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
379
+
RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
380
+
381
+
GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
382
+
RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
383
+
};
384
+
385
+
static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
386
+
/*
387
+
* Clock-Architecture Diagram 1
388
+
*/
389
+
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
390
+
RV1126_MODE_CON, 10, 2, MFLAGS),
391
+
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
392
+
393
+
/*
394
+
* Clock-Architecture Diagram 3
395
+
*/
396
+
/* PD_CORE */
397
+
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
398
+
RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
399
+
RV1126_CLKGATE_CON(0), 6, GFLAGS),
400
+
GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
401
+
RV1126_CLKGATE_CON(0), 12, GFLAGS),
402
+
GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
403
+
RV1126_CLKGATE_CON(0), 10, GFLAGS),
404
+
GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
405
+
RV1126_CLKGATE_CON(0), 11, GFLAGS),
406
+
COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
407
+
RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
408
+
RV1126_CLKGATE_CON(0), 8, GFLAGS),
409
+
410
+
/*
411
+
* Clock-Architecture Diagram 4
412
+
*/
413
+
/* PD_BUS */
414
+
COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
415
+
RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
416
+
RV1126_CLKGATE_CON(2), 0, GFLAGS),
417
+
GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
418
+
RV1126_CLKGATE_CON(2), 11, GFLAGS),
419
+
COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
420
+
RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
421
+
RV1126_CLKGATE_CON(2), 1, GFLAGS),
422
+
GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
423
+
RV1126_CLKGATE_CON(2), 12, GFLAGS),
424
+
COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
425
+
RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
426
+
RV1126_CLKGATE_CON(2), 2, GFLAGS),
427
+
GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
428
+
RV1126_CLKGATE_CON(2), 13, GFLAGS),
429
+
/* aclk_dmac is controlled by sgrf_clkgat_con. */
430
+
SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
431
+
GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
432
+
RV1126_CLKGATE_CON(3), 6, GFLAGS),
433
+
GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
434
+
RV1126_CLKGATE_CON(3), 7, GFLAGS),
435
+
GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
436
+
RV1126_CLKGATE_CON(6), 14, GFLAGS),
437
+
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
438
+
RV1126_CLKGATE_CON(7), 10, GFLAGS),
439
+
440
+
COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
441
+
RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
442
+
RV1126_CLKGATE_CON(4), 7, GFLAGS),
443
+
GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
444
+
RV1126_CLKGATE_CON(2), 14, GFLAGS),
445
+
GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
446
+
RV1126_CLKGATE_CON(4), 8, GFLAGS),
447
+
GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
448
+
RV1126_CLKGATE_CON(4), 9, GFLAGS),
449
+
GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
450
+
RV1126_CLKGATE_CON(4), 10, GFLAGS),
451
+
452
+
GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
453
+
RV1126_CLKGATE_CON(5), 0, GFLAGS),
454
+
COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
455
+
RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
456
+
RV1126_CLKGATE_CON(5), 1, GFLAGS),
457
+
COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
458
+
RV1126_CLKSEL_CON(11), 0,
459
+
RV1126_CLKGATE_CON(5), 2, GFLAGS,
460
+
&rv1126_uart0_fracmux),
461
+
GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
462
+
RV1126_CLKGATE_CON(5), 3, GFLAGS),
463
+
GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
464
+
RV1126_CLKGATE_CON(5), 4, GFLAGS),
465
+
COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
466
+
RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
467
+
RV1126_CLKGATE_CON(5), 5, GFLAGS),
468
+
COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
469
+
RV1126_CLKSEL_CON(13), 0,
470
+
RV1126_CLKGATE_CON(5), 6, GFLAGS,
471
+
&rv1126_uart2_fracmux),
472
+
GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
473
+
RV1126_CLKGATE_CON(5), 7, GFLAGS),
474
+
GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
475
+
RV1126_CLKGATE_CON(5), 8, GFLAGS),
476
+
COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
477
+
RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
478
+
RV1126_CLKGATE_CON(5), 9, GFLAGS),
479
+
COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
480
+
RV1126_CLKSEL_CON(15), 0,
481
+
RV1126_CLKGATE_CON(5), 10, GFLAGS,
482
+
&rv1126_uart3_fracmux),
483
+
GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
484
+
RV1126_CLKGATE_CON(5), 11, GFLAGS),
485
+
GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
486
+
RV1126_CLKGATE_CON(5), 12, GFLAGS),
487
+
COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
488
+
RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
489
+
DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
490
+
COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
491
+
RV1126_CLKSEL_CON(17), 0,
492
+
RV1126_CLKGATE_CON(5), 14, GFLAGS,
493
+
&rv1126_uart4_fracmux),
494
+
GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
495
+
RV1126_CLKGATE_CON(5), 15, GFLAGS),
496
+
GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
497
+
RV1126_CLKGATE_CON(6), 0, GFLAGS),
498
+
COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
499
+
RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
500
+
DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
501
+
COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
502
+
RV1126_CLKSEL_CON(19), 0,
503
+
RV1126_CLKGATE_CON(6), 2, GFLAGS,
504
+
&rv1126_uart5_fracmux),
505
+
GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
506
+
RV1126_CLKGATE_CON(6), 3, GFLAGS),
507
+
508
+
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
509
+
RV1126_CLKGATE_CON(3), 10, GFLAGS),
510
+
COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
511
+
RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
512
+
RV1126_CLKGATE_CON(3), 11, GFLAGS),
513
+
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
514
+
RV1126_CLKGATE_CON(3), 12, GFLAGS),
515
+
COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
516
+
RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
517
+
RV1126_CLKGATE_CON(3), 13, GFLAGS),
518
+
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
519
+
RV1126_CLKGATE_CON(3), 14, GFLAGS),
520
+
COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
521
+
RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
522
+
RV1126_CLKGATE_CON(3), 15, GFLAGS),
523
+
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
524
+
RV1126_CLKGATE_CON(4), 0, GFLAGS),
525
+
COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
526
+
RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
527
+
RV1126_CLKGATE_CON(4), 1, GFLAGS),
528
+
529
+
GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
530
+
RV1126_CLKGATE_CON(4), 2, GFLAGS),
531
+
COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
532
+
RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
533
+
RV1126_CLKGATE_CON(4), 3, GFLAGS),
534
+
535
+
GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
536
+
RV1126_CLKGATE_CON(4), 6, GFLAGS),
537
+
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
538
+
RV1126_CLKGATE_CON(4), 4, GFLAGS),
539
+
COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
540
+
RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
541
+
RV1126_CLKGATE_CON(4), 5, GFLAGS),
542
+
543
+
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
544
+
RV1126_CLKGATE_CON(7), 0, GFLAGS),
545
+
COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
546
+
RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
547
+
RV1126_CLKGATE_CON(7), 1, GFLAGS),
548
+
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
549
+
RV1126_CLKGATE_CON(7), 2, GFLAGS),
550
+
COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
551
+
RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
552
+
RV1126_CLKGATE_CON(7), 3, GFLAGS),
553
+
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
554
+
RV1126_CLKGATE_CON(7), 4, GFLAGS),
555
+
COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
556
+
RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
557
+
RV1126_CLKGATE_CON(7), 5, GFLAGS),
558
+
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
559
+
RV1126_CLKGATE_CON(7), 6, GFLAGS),
560
+
COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
561
+
RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
562
+
RV1126_CLKGATE_CON(7), 7, GFLAGS),
563
+
564
+
GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
565
+
RV1126_CLKGATE_CON(6), 4, GFLAGS),
566
+
COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
567
+
RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
568
+
RV1126_CLKGATE_CON(6), 5, GFLAGS),
569
+
570
+
GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
571
+
RV1126_CLKGATE_CON(6), 7, GFLAGS),
572
+
GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
573
+
RV1126_CLKGATE_CON(6), 8, GFLAGS),
574
+
GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
575
+
RV1126_CLKGATE_CON(6), 9, GFLAGS),
576
+
GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
577
+
RV1126_CLKGATE_CON(6), 10, GFLAGS),
578
+
GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
579
+
RV1126_CLKGATE_CON(6), 11, GFLAGS),
580
+
GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
581
+
RV1126_CLKGATE_CON(6), 12, GFLAGS),
582
+
GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
583
+
RV1126_CLKGATE_CON(6), 13, GFLAGS),
584
+
585
+
GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
586
+
RV1126_CLKGATE_CON(6), 6, GFLAGS),
587
+
588
+
GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
589
+
RV1126_CLKGATE_CON(7), 11, GFLAGS),
590
+
GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
591
+
RV1126_CLKGATE_CON(7), 12, GFLAGS),
592
+
COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
593
+
RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
594
+
RV1126_CLKGATE_CON(7), 13, GFLAGS),
595
+
596
+
GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
597
+
RV1126_CLKGATE_CON(7), 8, GFLAGS),
598
+
COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
599
+
RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
600
+
RV1126_CLKGATE_CON(7), 9, GFLAGS),
601
+
/* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
602
+
SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
603
+
SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
604
+
605
+
GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
606
+
RV1126_CLKGATE_CON(24), 3, GFLAGS),
607
+
COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
608
+
RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
609
+
RV1126_CLKGATE_CON(24), 4, GFLAGS),
610
+
GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
611
+
RV1126_CLKGATE_CON(24), 5, GFLAGS),
612
+
GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
613
+
RV1126_CLKGATE_CON(24), 0, GFLAGS),
614
+
COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
615
+
RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
616
+
RV1126_CLKGATE_CON(24), 1, GFLAGS),
617
+
GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
618
+
RV1126_CLKGATE_CON(24), 2, GFLAGS),
619
+
620
+
/*
621
+
* Clock-Architecture Diagram 6
622
+
*/
623
+
/* PD_AUDIO */
624
+
COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
625
+
RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
626
+
RV1126_CLKGATE_CON(9), 0, GFLAGS),
627
+
628
+
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
629
+
RV1126_CLKGATE_CON(9), 4, GFLAGS),
630
+
COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
631
+
RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
632
+
RV1126_CLKGATE_CON(9), 5, GFLAGS),
633
+
COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div",
634
+
CLK_SET_RATE_PARENT,
635
+
RV1126_CLKSEL_CON(28), 0,
636
+
RV1126_CLKGATE_CON(9), 6, GFLAGS,
637
+
&rv1126_i2s0_tx_fracmux),
638
+
GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
639
+
RV1126_CLKGATE_CON(9), 9, GFLAGS),
640
+
COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
641
+
RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
642
+
RV1126_CLKGATE_CON(9), 7, GFLAGS),
643
+
COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div",
644
+
CLK_SET_RATE_PARENT,
645
+
RV1126_CLKSEL_CON(29), 0,
646
+
RV1126_CLKGATE_CON(9), 8, GFLAGS,
647
+
&rv1126_i2s0_rx_fracmux),
648
+
GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
649
+
RV1126_CLKGATE_CON(9), 10, GFLAGS),
650
+
COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
651
+
RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
652
+
RV1126_CLKGATE_CON(9), 13, GFLAGS),
653
+
COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
654
+
RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
655
+
RV1126_CLKGATE_CON(9), 14, GFLAGS),
656
+
657
+
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
658
+
RV1126_CLKGATE_CON(10), 0, GFLAGS),
659
+
COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
660
+
RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
661
+
RV1126_CLKGATE_CON(10), 1, GFLAGS),
662
+
COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div",
663
+
CLK_SET_RATE_PARENT,
664
+
RV1126_CLKSEL_CON(32), 0,
665
+
RV1126_CLKGATE_CON(10), 2, GFLAGS,
666
+
&rv1126_i2s1_fracmux),
667
+
GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
668
+
RV1126_CLKGATE_CON(10), 3, GFLAGS),
669
+
COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
670
+
RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
671
+
RV1126_CLKGATE_CON(10), 4, GFLAGS),
672
+
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
673
+
RV1126_CLKGATE_CON(10), 5, GFLAGS),
674
+
COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
675
+
RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
676
+
RV1126_CLKGATE_CON(10), 6, GFLAGS),
677
+
COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div",
678
+
CLK_SET_RATE_PARENT,
679
+
RV1126_CLKSEL_CON(34), 0,
680
+
RV1126_CLKGATE_CON(10), 7, GFLAGS,
681
+
&rv1126_i2s2_fracmux),
682
+
GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
683
+
RV1126_CLKGATE_CON(10), 8, GFLAGS),
684
+
COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
685
+
RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
686
+
RV1126_CLKGATE_CON(10), 9, GFLAGS),
687
+
688
+
GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
689
+
RV1126_CLKGATE_CON(10), 10, GFLAGS),
690
+
COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
691
+
RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
692
+
RV1126_CLKGATE_CON(10), 11, GFLAGS),
693
+
694
+
GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
695
+
RV1126_CLKGATE_CON(10), 12, GFLAGS),
696
+
COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
697
+
RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
698
+
RV1126_CLKGATE_CON(10), 13, GFLAGS),
699
+
COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div",
700
+
CLK_SET_RATE_PARENT,
701
+
RV1126_CLKSEL_CON(37), 0,
702
+
RV1126_CLKGATE_CON(10), 14, GFLAGS,
703
+
&rv1126_audpwm_fracmux),
704
+
GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
705
+
RV1126_CLKGATE_CON(10), 15, GFLAGS),
706
+
707
+
GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
708
+
RV1126_CLKGATE_CON(11), 0, GFLAGS),
709
+
GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
710
+
RV1126_CLKGATE_CON(11), 2, GFLAGS),
711
+
GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
712
+
RV1126_CLKGATE_CON(11), 3, GFLAGS),
713
+
COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
714
+
RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
715
+
RV1126_CLKGATE_CON(11), 1, GFLAGS),
716
+
717
+
/*
718
+
* Clock-Architecture Diagram 12
719
+
*/
720
+
/* PD_PHP */
721
+
COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
722
+
RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
723
+
RV1126_CLKGATE_CON(17), 0, GFLAGS),
724
+
COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
725
+
RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
726
+
RV1126_CLKGATE_CON(17), 1, GFLAGS),
727
+
/* PD_SDCARD */
728
+
GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
729
+
RV1126_CLKGATE_CON(17), 6, GFLAGS),
730
+
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
731
+
RV1126_CLKGATE_CON(18), 4, GFLAGS),
732
+
COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
733
+
RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
734
+
DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
735
+
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
736
+
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
737
+
738
+
/* PD_SDIO */
739
+
GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
740
+
RV1126_CLKGATE_CON(17), 8, GFLAGS),
741
+
GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
742
+
RV1126_CLKGATE_CON(18), 6, GFLAGS),
743
+
COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
744
+
RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
745
+
RV1126_CLKGATE_CON(18), 7, GFLAGS),
746
+
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
747
+
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
748
+
749
+
/* PD_NVM */
750
+
GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
751
+
RV1126_CLKGATE_CON(18), 1, GFLAGS),
752
+
GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
753
+
RV1126_CLKGATE_CON(18), 8, GFLAGS),
754
+
COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
755
+
RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
756
+
RV1126_CLKGATE_CON(18), 9, GFLAGS),
757
+
GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
758
+
RV1126_CLKGATE_CON(18), 13, GFLAGS),
759
+
COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
760
+
RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
761
+
RV1126_CLKGATE_CON(18), 14, GFLAGS),
762
+
GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
763
+
RV1126_CLKGATE_CON(18), 10, GFLAGS),
764
+
GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
765
+
RV1126_CLKGATE_CON(18), 11, GFLAGS),
766
+
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
767
+
RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
768
+
RV1126_CLKGATE_CON(18), 12, GFLAGS),
769
+
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
770
+
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
771
+
772
+
/* PD_USB */
773
+
GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
774
+
RV1126_CLKGATE_CON(19), 0, GFLAGS),
775
+
GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
776
+
RV1126_CLKGATE_CON(19), 1, GFLAGS),
777
+
GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
778
+
RV1126_CLKGATE_CON(19), 4, GFLAGS),
779
+
GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
780
+
RV1126_CLKGATE_CON(19), 5, GFLAGS),
781
+
COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
782
+
RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
783
+
RV1126_CLKGATE_CON(19), 6, GFLAGS),
784
+
GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
785
+
RV1126_CLKGATE_CON(19), 7, GFLAGS),
786
+
GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
787
+
RV1126_CLKGATE_CON(19), 8, GFLAGS),
788
+
/* PD_GMAC */
789
+
GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
790
+
RV1126_CLKGATE_CON(20), 0, GFLAGS),
791
+
COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
792
+
RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
793
+
RV1126_CLKGATE_CON(20), 1, GFLAGS),
794
+
GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
795
+
RV1126_CLKGATE_CON(20), 4, GFLAGS),
796
+
GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
797
+
RV1126_CLKGATE_CON(20), 5, GFLAGS),
798
+
799
+
COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
800
+
RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
801
+
RV1126_CLKGATE_CON(20), 6, GFLAGS),
802
+
GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
803
+
RV1126_CLKGATE_CON(20), 12, GFLAGS),
804
+
MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
805
+
RV1126_GMAC_CON, 0, 1, MFLAGS),
806
+
GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
807
+
RV1126_CLKGATE_CON(20), 13, GFLAGS),
808
+
MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
809
+
RV1126_GMAC_CON, 5, 1, MFLAGS),
810
+
MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
811
+
CLK_SET_RATE_NO_REPARENT,
812
+
RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
813
+
814
+
GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
815
+
RV1126_CLKGATE_CON(20), 7, GFLAGS),
816
+
817
+
GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
818
+
RV1126_CLKGATE_CON(20), 9, GFLAGS),
819
+
FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
820
+
FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
821
+
MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
822
+
RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
823
+
GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
824
+
RV1126_CLKGATE_CON(20), 8, GFLAGS),
825
+
FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
826
+
FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
827
+
MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
828
+
RV1126_GMAC_CON, 1, 1, MFLAGS),
829
+
MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |
830
+
CLK_SET_RATE_NO_REPARENT,
831
+
RV1126_GMAC_CON, 4, 1, MFLAGS),
832
+
833
+
GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
834
+
RV1126_CLKGATE_CON(20), 10, GFLAGS),
835
+
COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
836
+
RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
837
+
RV1126_CLKGATE_CON(20), 11, GFLAGS),
838
+
839
+
/*
840
+
* Clock-Architecture Diagram 15
841
+
*/
842
+
GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
843
+
RV1126_CLKGATE_CON(23), 8, GFLAGS),
844
+
GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
845
+
RV1126_CLKGATE_CON(23), 4, GFLAGS),
846
+
GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
847
+
RV1126_CLKGATE_CON(23), 2, GFLAGS),
848
+
GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
849
+
RV1126_CLKGATE_CON(23), 3, GFLAGS),
850
+
GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
851
+
RV1126_CLKGATE_CON(19), 13, GFLAGS),
852
+
GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
853
+
RV1126_CLKGATE_CON(19), 12, GFLAGS),
854
+
855
+
/*
856
+
* Clock-Architecture Diagram 3
857
+
*/
858
+
/* PD_CORE */
859
+
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
860
+
RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
861
+
RV1126_CLKGATE_CON(0), 2, GFLAGS),
862
+
GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
863
+
RV1126_CLKGATE_CON(0), 5, GFLAGS),
864
+
GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
865
+
RV1126_CLKGATE_CON(0), 9, GFLAGS),
866
+
GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
867
+
RV1126_CLKGATE_CON(0), 3, GFLAGS),
868
+
GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
869
+
RV1126_CLKGATE_CON(0), 4, GFLAGS),
870
+
/*
871
+
* Clock-Architecture Diagram 4
872
+
*/
873
+
/* PD_BUS */
874
+
GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
875
+
RV1126_CLKGATE_CON(2), 10, GFLAGS),
876
+
GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
877
+
RV1126_CLKGATE_CON(2), 3, GFLAGS),
878
+
GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
879
+
RV1126_CLKGATE_CON(2), 4, GFLAGS),
880
+
GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
881
+
RV1126_CLKGATE_CON(2), 5, GFLAGS),
882
+
GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
883
+
RV1126_CLKGATE_CON(2), 6, GFLAGS),
884
+
GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
885
+
RV1126_CLKGATE_CON(2), 7, GFLAGS),
886
+
GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
887
+
RV1126_CLKGATE_CON(2), 8, GFLAGS),
888
+
GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
889
+
RV1126_CLKGATE_CON(2), 9, GFLAGS),
890
+
GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
891
+
RV1126_CLKGATE_CON(6), 15, GFLAGS),
892
+
GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
893
+
RV1126_CLKGATE_CON(8), 4, GFLAGS),
894
+
GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
895
+
RV1126_CLKGATE_CON(3), 9, GFLAGS),
896
+
GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
897
+
RV1126_CLKGATE_CON(7), 14, GFLAGS),
898
+
899
+
/*
900
+
* Clock-Architecture Diagram 6
901
+
*/
902
+
/* PD_AUDIO */
903
+
GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
904
+
RV1126_CLKGATE_CON(9), 2, GFLAGS),
905
+
GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
906
+
RV1126_CLKGATE_CON(9), 3, GFLAGS),
907
+
908
+
/*
909
+
* Clock-Architecture Diagram 12
910
+
*/
911
+
/* PD_PHP */
912
+
GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
913
+
RV1126_CLKGATE_CON(17), 2, GFLAGS),
914
+
GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
915
+
RV1126_CLKGATE_CON(17), 3, GFLAGS),
916
+
GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
917
+
RV1126_CLKGATE_CON(17), 4, GFLAGS),
918
+
GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
919
+
RV1126_CLKGATE_CON(17), 5, GFLAGS),
920
+
921
+
/* PD_SDCARD */
922
+
GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
923
+
RV1126_CLKGATE_CON(17), 7, GFLAGS),
924
+
925
+
/* PD_SDIO */
926
+
GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
927
+
RV1126_CLKGATE_CON(17), 9, GFLAGS),
928
+
929
+
/* PD_NVM */
930
+
GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
931
+
RV1126_CLKGATE_CON(18), 3, GFLAGS),
932
+
933
+
/* PD_USB */
934
+
GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
935
+
RV1126_CLKGATE_CON(19), 2, GFLAGS),
936
+
GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
937
+
RV1126_CLKGATE_CON(19), 3, GFLAGS),
938
+
939
+
/* PD_GMAC */
940
+
GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
941
+
RV1126_CLKGATE_CON(20), 2, GFLAGS),
942
+
GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
943
+
RV1126_CLKGATE_CON(20), 3, GFLAGS),
944
+
945
+
/*
946
+
* Clock-Architecture Diagram 13
947
+
*/
948
+
/* PD_DDR */
949
+
COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
950
+
RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
951
+
RV1126_CLKGATE_CON(21), 0, GFLAGS),
952
+
GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
953
+
RV1126_CLKGATE_CON(21), 15, GFLAGS),
954
+
GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
955
+
RV1126_CLKGATE_CON(21), 6, GFLAGS),
956
+
COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
957
+
RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
958
+
CLK_DIVIDER_POWER_OF_TWO),
959
+
COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
960
+
RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
961
+
RV1126_CLKGATE_CON(21), 8, GFLAGS),
962
+
GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
963
+
RV1126_CLKGATE_CON(23), 1, GFLAGS),
964
+
GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
965
+
RV1126_CLKGATE_CON(21), 10, GFLAGS),
966
+
GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
967
+
RV1126_CLKGATE_CON(21), 2, GFLAGS),
968
+
GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
969
+
RV1126_CLKGATE_CON(21), 13, GFLAGS),
970
+
GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
971
+
RV1126_CLKGATE_CON(21), 4, GFLAGS),
972
+
GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
973
+
RV1126_CLKGATE_CON(21), 14, GFLAGS),
974
+
GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
975
+
RV1126_CLKGATE_CON(21), 9, GFLAGS),
976
+
GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
977
+
RV1126_CLKGATE_CON(21), 5, GFLAGS),
978
+
GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
979
+
RV1126_CLKGATE_CON(21), 3, GFLAGS),
980
+
GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
981
+
RV1126_CLKGATE_CON(20), 15, GFLAGS),
982
+
GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
983
+
RV1126_CLKGATE_CON(21), 7, GFLAGS),
984
+
985
+
/*
986
+
* Clock-Architecture Diagram 15
987
+
*/
988
+
GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
989
+
RV1126_CLKGATE_CON(23), 9, GFLAGS),
990
+
GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
991
+
RV1126_CLKGATE_CON(23), 10, GFLAGS),
992
+
GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
993
+
RV1126_CLKGATE_CON(23), 11, GFLAGS),
994
+
GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
995
+
RV1126_CLKGATE_CON(23), 12, GFLAGS),
996
+
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
997
+
RV1126_CLKGATE_CON(23), 0, GFLAGS),
998
+
};
999
+
1000
+
static const char *const rv1126_cru_critical_clocks[] __initconst = {
1001
+
"gpll",
1002
+
"cpll",
1003
+
"hpll",
1004
+
"armclk",
1005
+
"pclk_dbg",
1006
+
"pclk_pdpmu",
1007
+
"aclk_pdbus",
1008
+
"hclk_pdbus",
1009
+
"pclk_pdbus",
1010
+
"aclk_pdphp",
1011
+
"hclk_pdphp",
1012
+
"clk_ddrphy",
1013
+
"pclk_pdddr",
1014
+
"pclk_pdtop",
1015
+
"clk_usbhost_utmi_ohci",
1016
+
"aclk_pdjpeg_niu",
1017
+
"hclk_pdjpeg_niu",
1018
+
"aclk_pdvdec_niu",
1019
+
"hclk_pdvdec_niu",
1020
+
};
1021
+
1022
+
static void __init rv1126_pmu_clk_init(struct device_node *np)
1023
+
{
1024
+
struct rockchip_clk_provider *ctx;
1025
+
void __iomem *reg_base;
1026
+
1027
+
reg_base = of_iomap(np, 0);
1028
+
if (!reg_base) {
1029
+
pr_err("%s: could not map cru pmu region\n", __func__);
1030
+
return;
1031
+
}
1032
+
1033
+
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1034
+
if (IS_ERR(ctx)) {
1035
+
pr_err("%s: rockchip pmu clk init failed\n", __func__);
1036
+
return;
1037
+
}
1038
+
1039
+
rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
1040
+
ARRAY_SIZE(rv1126_pmu_pll_clks),
1041
+
RV1126_GRF_SOC_STATUS0);
1042
+
1043
+
rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
1044
+
ARRAY_SIZE(rv1126_clk_pmu_branches));
1045
+
1046
+
rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
1047
+
ROCKCHIP_SOFTRST_HIWORD_MASK);
1048
+
1049
+
rockchip_clk_of_add_provider(np, ctx);
1050
+
}
1051
+
1052
+
static void __init rv1126_clk_init(struct device_node *np)
1053
+
{
1054
+
struct rockchip_clk_provider *ctx;
1055
+
void __iomem *reg_base;
1056
+
1057
+
reg_base = of_iomap(np, 0);
1058
+
if (!reg_base) {
1059
+
pr_err("%s: could not map cru region\n", __func__);
1060
+
return;
1061
+
}
1062
+
1063
+
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1064
+
if (IS_ERR(ctx)) {
1065
+
pr_err("%s: rockchip clk init failed\n", __func__);
1066
+
iounmap(reg_base);
1067
+
return;
1068
+
}
1069
+
1070
+
rockchip_clk_register_plls(ctx, rv1126_pll_clks,
1071
+
ARRAY_SIZE(rv1126_pll_clks),
1072
+
RV1126_GRF_SOC_STATUS0);
1073
+
1074
+
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1075
+
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1076
+
&rv1126_cpuclk_data, rv1126_cpuclk_rates,
1077
+
ARRAY_SIZE(rv1126_cpuclk_rates));
1078
+
1079
+
rockchip_clk_register_branches(ctx, rv1126_clk_branches,
1080
+
ARRAY_SIZE(rv1126_clk_branches));
1081
+
1082
+
rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
1083
+
ROCKCHIP_SOFTRST_HIWORD_MASK);
1084
+
1085
+
rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
1086
+
1087
+
rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
1088
+
ARRAY_SIZE(rv1126_cru_critical_clocks));
1089
+
1090
+
rockchip_clk_of_add_provider(np, ctx);
1091
+
}
1092
+
1093
+
struct clk_rv1126_inits {
1094
+
void (*inits)(struct device_node *np);
1095
+
};
1096
+
1097
+
static const struct clk_rv1126_inits clk_rv1126_pmucru_init = {
1098
+
.inits = rv1126_pmu_clk_init,
1099
+
};
1100
+
1101
+
static const struct clk_rv1126_inits clk_rv1126_cru_init = {
1102
+
.inits = rv1126_clk_init,
1103
+
};
1104
+
1105
+
static const struct of_device_id clk_rv1126_match_table[] = {
1106
+
{
1107
+
.compatible = "rockchip,rv1126-cru",
1108
+
.data = &clk_rv1126_cru_init,
1109
+
}, {
1110
+
.compatible = "rockchip,rv1126-pmucru",
1111
+
.data = &clk_rv1126_pmucru_init,
1112
+
},
1113
+
{ }
1114
+
};
1115
+
1116
+
static int __init clk_rv1126_probe(struct platform_device *pdev)
1117
+
{
1118
+
struct device_node *np = pdev->dev.of_node;
1119
+
const struct clk_rv1126_inits *init_data;
1120
+
1121
+
init_data = (struct clk_rv1126_inits *)of_device_get_match_data(&pdev->dev);
1122
+
if (!init_data)
1123
+
return -EINVAL;
1124
+
1125
+
if (init_data->inits)
1126
+
init_data->inits(np);
1127
+
1128
+
return 0;
1129
+
}
1130
+
1131
+
static struct platform_driver clk_rv1126_driver = {
1132
+
.driver = {
1133
+
.name = "clk-rv1126",
1134
+
.of_match_table = clk_rv1126_match_table,
1135
+
.suppress_bind_attrs = true,
1136
+
},
1137
+
};
1138
+
builtin_platform_driver_probe(clk_rv1126_driver, clk_rv1126_probe);
+19
drivers/clk/rockchip/clk.h
+19
drivers/clk/rockchip/clk.h
···
79
79
#define RV1108_EMMC_CON0 0x1e8
80
80
#define RV1108_EMMC_CON1 0x1ec
81
81
82
+
#define RV1126_PMU_MODE 0x0
83
+
#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
84
+
#define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
85
+
#define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
86
+
#define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
87
+
#define RV1126_PLL_CON(x) ((x) * 0x4)
88
+
#define RV1126_MODE_CON 0x90
89
+
#define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
90
+
#define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
91
+
#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
92
+
#define RV1126_GLB_SRST_FST 0x408
93
+
#define RV1126_GLB_SRST_SND 0x40c
94
+
#define RV1126_SDMMC_CON0 0x440
95
+
#define RV1126_SDMMC_CON1 0x444
96
+
#define RV1126_SDIO_CON0 0x448
97
+
#define RV1126_SDIO_CON1 0x44c
98
+
#define RV1126_EMMC_CON0 0x450
99
+
#define RV1126_EMMC_CON1 0x454
100
+
82
101
#define RK2928_PLL_CON(x) ((x) * 0x4)
83
102
#define RK2928_MODE_CON 0x40
84
103
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)