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dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
Convert Amlogic AXG Audio Clock Controller binding to yaml.
Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240513224552.800153-1-jan.dakinevich@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Alexander Stein
and committed by
Jerome Brunet
23dc5f7e
1613e604
+201
-59
-59
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
-59
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
···
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* Amlogic AXG Audio Clock Controllers
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The Amlogic AXG audio clock controller generates and supplies clock to the
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other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
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devices.
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Required Properties:
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-
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
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"amlogic,g12a-audio-clkc" for G12A,
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"amlogic,sm1-audio-clkc" for S905X3.
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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in clock-names.
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- clock-names : must contain the following:
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* "pclk" - Main peripheral bus clock
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may contain the following:
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* "mst_in[0-7]" - 8 input plls to generate clock signals
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* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
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components.
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* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
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components.
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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- #reset-cells : should be 1 on the g12a (and following) soc family
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-
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
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used in device tree sources.
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Example:
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clkc_audio: clock-controller@0 {
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compatible = "amlogic,axg-audio-clkc";
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reg = <0x0 0x0 0x0 0xb4>;
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#clock-cells = <1>;
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-
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clocks = <&clkc CLKID_AUDIO>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL3>,
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<&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_FCLK_DIV3>,
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_GP0_PLL>;
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clock-names = "pclk",
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"mst_in0",
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"mst_in1",
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"mst_in2",
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"mst_in3",
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"mst_in4",
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"mst_in5",
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"mst_in6",
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"mst_in7";
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resets = <&reset RESET_AUDIO>;
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};
+201
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
+201
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
···
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic AXG Audio Clock Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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description:
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The Amlogic AXG audio clock controller generates and supplies clock to the
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other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
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devices.
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+
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properties:
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compatible:
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enum:
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- amlogic,axg-audio-clkc
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- amlogic,g12a-audio-clkc
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- amlogic,sm1-audio-clkc
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+
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'#clock-cells':
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const: 1
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+
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'#reset-cells':
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const: 1
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+
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reg:
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maxItems: 1
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+
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clocks:
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minItems: 1
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items:
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- description: main peripheral bus clock
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- description: input plls to generate clock signals N0
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- description: input plls to generate clock signals N1
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- description: input plls to generate clock signals N2
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- description: input plls to generate clock signals N3
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- description: input plls to generate clock signals N4
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- description: input plls to generate clock signals N5
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- description: input plls to generate clock signals N6
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- description: input plls to generate clock signals N7
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- description: slave bit clock N0 provided by external components
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- description: slave bit clock N1 provided by external components
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- description: slave bit clock N2 provided by external components
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- description: slave bit clock N3 provided by external components
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- description: slave bit clock N4 provided by external components
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- description: slave bit clock N5 provided by external components
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- description: slave bit clock N6 provided by external components
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- description: slave bit clock N7 provided by external components
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- description: slave bit clock N8 provided by external components
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- description: slave bit clock N9 provided by external components
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- description: slave sample clock N0 provided by external components
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- description: slave sample clock N1 provided by external components
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- description: slave sample clock N2 provided by external components
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- description: slave sample clock N3 provided by external components
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- description: slave sample clock N4 provided by external components
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- description: slave sample clock N5 provided by external components
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- description: slave sample clock N6 provided by external components
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- description: slave sample clock N7 provided by external components
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- description: slave sample clock N8 provided by external components
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- description: slave sample clock N9 provided by external components
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+
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clock-names:
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minItems: 1
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items:
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- const: pclk
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- const: mst_in0
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- const: mst_in1
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- const: mst_in2
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- const: mst_in3
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- const: mst_in4
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- const: mst_in5
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- const: mst_in6
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- const: mst_in7
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- const: slv_sclk0
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- const: slv_sclk1
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- const: slv_sclk2
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- const: slv_sclk3
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- const: slv_sclk4
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- const: slv_sclk5
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- const: slv_sclk6
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- const: slv_sclk7
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- const: slv_sclk8
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- const: slv_sclk9
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- const: slv_lrclk0
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- const: slv_lrclk1
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- const: slv_lrclk2
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- const: slv_lrclk3
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- const: slv_lrclk4
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- const: slv_lrclk5
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- const: slv_lrclk6
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- const: slv_lrclk7
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- const: slv_lrclk8
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- const: slv_lrclk9
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+
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resets:
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description: internal reset line
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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- resets
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+
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- amlogic,g12a-audio-clkc
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- amlogic,sm1-audio-clkc
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then:
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required:
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- '#reset-cells'
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else:
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properties:
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'#reset-cells': false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/axg-clkc.h>
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#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clkc_audio: clock-controller@0 {
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compatible = "amlogic,axg-audio-clkc";
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reg = <0x0 0x0 0x0 0xb4>;
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#clock-cells = <1>;
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clocks = <&clkc CLKID_AUDIO>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL3>,
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<&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_FCLK_DIV3>,
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_GP0_PLL>,
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<&slv_sclk0>,
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<&slv_sclk1>,
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<&slv_sclk2>,
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<&slv_sclk3>,
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<&slv_sclk4>,
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<&slv_sclk5>,
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<&slv_sclk6>,
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<&slv_sclk7>,
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<&slv_sclk8>,
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<&slv_sclk9>,
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<&slv_lrclk0>,
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<&slv_lrclk1>,
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<&slv_lrclk2>,
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<&slv_lrclk3>,
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<&slv_lrclk4>,
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<&slv_lrclk5>,
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<&slv_lrclk6>,
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<&slv_lrclk7>,
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<&slv_lrclk8>,
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<&slv_lrclk9>;
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clock-names = "pclk",
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"mst_in0",
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"mst_in1",
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"mst_in2",
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"mst_in3",
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"mst_in4",
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"mst_in5",
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"mst_in6",
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"mst_in7",
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"slv_sclk0",
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"slv_sclk1",
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"slv_sclk2",
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"slv_sclk3",
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"slv_sclk4",
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"slv_sclk5",
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"slv_sclk6",
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"slv_sclk7",
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"slv_sclk8",
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"slv_sclk9",
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"slv_lrclk0",
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"slv_lrclk1",
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"slv_lrclk2",
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"slv_lrclk3",
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"slv_lrclk4",
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"slv_lrclk5",
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"slv_lrclk6",
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"slv_lrclk7",
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"slv_lrclk8",
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"slv_lrclk9";
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resets = <&reset RESET_AUDIO>;
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};
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};