tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: Move gas macro MAPPED_KERNEL_SETUP_TLB to IP27-specific code.
It's IP27-specific and can only cause trouble in head.S.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+39
-39
+39
arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+39
arch/mips/include/asm/mach-ip27/kernel-entry-init.h
···
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dsrl \res, NSRI_NODEID_SHFT
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.endm
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/*
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* inputs are the text nasid in t1, data nasid in t2.
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*/
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.macro MAPPED_KERNEL_SETUP_TLB
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#ifdef CONFIG_MAPPED_KERNEL
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/*
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* This needs to read the nasid - assume 0 for now.
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* Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
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* 0+DVG in tlblo_1.
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*/
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dli t0, 0xffffffffc0000000
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dmtc0 t0, CP0_ENTRYHI
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li t0, 0x1c000 # Offset of text into node memory
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dsll t1, NASID_SHFT # Shift text nasid into place
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dsll t2, NASID_SHFT # Same for data nasid
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or t1, t1, t0 # Physical load address of kernel text
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or t2, t2, t0 # Physical load address of kernel data
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dsrl t1, 12 # 4K pfn
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dsrl t2, 12 # 4K pfn
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dsll t1, 6 # Get pfn into place
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dsll t2, 6 # Get pfn into place
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li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
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or t0, t0, t1
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mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
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li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
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or t0, t0, t2
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mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
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li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
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mtc0 t0, CP0_PAGEMASK
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li t0, 0 # KMAP_INX
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mtc0 t0, CP0_INDEX
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li t0, 1
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mtc0 t0, CP0_WIRED
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tlbwi
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#else
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mtc0 zero, CP0_WIRED
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#endif
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.endm
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/*
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* Intentionally empty macro, used in head.S. Override in
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* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
-39
arch/mips/kernel/head.S
-39
arch/mips/kernel/head.S
···
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#include <kernel-entry-init.h>
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/*
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* inputs are the text nasid in t1, data nasid in t2.
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*/
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.macro MAPPED_KERNEL_SETUP_TLB
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#ifdef CONFIG_MAPPED_KERNEL
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/*
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* This needs to read the nasid - assume 0 for now.
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* Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
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* 0+DVG in tlblo_1.
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*/
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dli t0, 0xffffffffc0000000
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dmtc0 t0, CP0_ENTRYHI
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li t0, 0x1c000 # Offset of text into node memory
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dsll t1, NASID_SHFT # Shift text nasid into place
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dsll t2, NASID_SHFT # Same for data nasid
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or t1, t1, t0 # Physical load address of kernel text
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or t2, t2, t0 # Physical load address of kernel data
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dsrl t1, 12 # 4K pfn
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dsrl t2, 12 # 4K pfn
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dsll t1, 6 # Get pfn into place
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dsll t2, 6 # Get pfn into place
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li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
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or t0, t0, t1
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mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
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li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
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or t0, t0, t2
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mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
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li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
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mtc0 t0, CP0_PAGEMASK
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li t0, 0 # KMAP_INX
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mtc0 t0, CP0_INDEX
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li t0, 1
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mtc0 t0, CP0_WIRED
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tlbwi
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#else
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mtc0 zero, CP0_WIRED
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#endif
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.endm
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/*
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* For the moment disable interrupts, mark the kernel mode and
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* set ST0_KX so that the CPU does not spit fire when using
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* 64-bit addresses. A full initialization of the CPU's status