tjh.dev / kernel
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drm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

authored by

Francisco Jerez and committed by
Ben Skeggs 23357e4d 2756a4f5

+1 -1
+1 -1
drivers/gpu/drm/nouveau/nouveau_hw.c
··· 305 305 bool mpll = Preg == 0x4020; 306 306 uint32_t oldPval = nvReadMC(dev, Preg); 307 307 uint32_t NMNM = pv->NM2 << 16 | pv->NM1; 308 - uint32_t Pval = (oldPval & (mpll ? ~(0x11 << 16) : ~(1 << 16))) | 308 + uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | 309 309 0xc << 28 | pv->log2P << 16; 310 310 uint32_t saved4600 = 0; 311 311 /* some cards have different maskc040s */