tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge branch 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Regression fixes for audio and UVD, several hang fixes,
some DPM fixes.

* 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: re-enable sw ACR support on pre-DCE4
drm/radeon/dpm: disable bapm on TN asics
drm/radeon: improve soft reset on CIK
drm/radeon: improve soft reset on SI
drm/radeon/dpm: off by one in si_set_mc_special_registers()
drm/radeon/dpm/btc: off by one in btc_set_mc_special_registers()
drm/radeon: forever loop on error in radeon_do_test_moves()
drm/radeon: fix hw contexts for SUMO2 asics
drm/radeon: fix typo in CP DMA register headers
drm/radeon/dpm: disable multiple UVD states
drm/radeon: use hw generated CTS/N values for audio
drm/radeon: fix N/CTS clock matching for audio
drm/radeon: use 64-bit math to calculate CTS values for audio (v2)
drm/edid: catch kmalloc failure in drm_edid_to_speaker_allocation

Dave Airlie 23026285 ecc7e6f3

+53 -25
+2
drivers/gpu/drm/drm_edid.c
··· 2925 2925 /* Speaker Allocation Data Block */ 2926 2926 if (dbl == 3) { 2927 2927 *sadb = kmalloc(dbl, GFP_KERNEL); 2928 + if (!*sadb) 2929 + return -ENOMEM; 2928 2930 memcpy(*sadb, &db[1], dbl); 2929 2931 count = dbl; 2930 2932 break;
+3 -3
drivers/gpu/drm/radeon/btc_dpm.c
··· 1930 1930 } 1931 1931 j++; 1932 1932 1933 - if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1933 + if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1934 1934 return -EINVAL; 1935 1935 1936 1936 tmp = RREG32(MC_PMG_CMD_MRS); ··· 1945 1945 } 1946 1946 j++; 1947 1947 1948 - if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1948 + if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1949 1949 return -EINVAL; 1950 1950 break; 1951 1951 case MC_SEQ_RESERVE_M >> 2: ··· 1959 1959 } 1960 1960 j++; 1961 1961 1962 - if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1962 + if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1963 1963 return -EINVAL; 1964 1964 break; 1965 1965 default:
+6
drivers/gpu/drm/radeon/cik.c
··· 77 77 static void cik_program_aspm(struct radeon_device *rdev); 78 78 static void cik_init_pg(struct radeon_device *rdev); 79 79 static void cik_init_cg(struct radeon_device *rdev); 80 + static void cik_fini_pg(struct radeon_device *rdev); 81 + static void cik_fini_cg(struct radeon_device *rdev); 80 82 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, 81 83 bool enable); 82 84 ··· 4186 4184 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 4187 4185 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 4188 4186 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 4187 + 4188 + /* disable CG/PG */ 4189 + cik_fini_pg(rdev); 4190 + cik_fini_cg(rdev); 4189 4191 4190 4192 /* stop the rlc */ 4191 4193 cik_rlc_stop(rdev);
+1 -1
drivers/gpu/drm/radeon/evergreen.c
··· 3131 3131 rdev->config.evergreen.sx_max_export_size = 256; 3132 3132 rdev->config.evergreen.sx_max_export_pos_size = 64; 3133 3133 rdev->config.evergreen.sx_max_export_smx_size = 192; 3134 - rdev->config.evergreen.max_hw_contexts = 8; 3134 + rdev->config.evergreen.max_hw_contexts = 4; 3135 3135 rdev->config.evergreen.sq_num_cf_insts = 2; 3136 3136 3137 3137 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
+1 -2
drivers/gpu/drm/radeon/evergreen_hdmi.c
··· 288 288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 289 289 290 290 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 291 - HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 292 - HDMI_ACR_SOURCE); /* select SW CTS value */ 291 + HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 293 292 294 293 evergreen_hdmi_update_ACR(encoder, mode->clock); 295 294
+2 -2
drivers/gpu/drm/radeon/evergreend.h
··· 1501 1501 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1502 1502 */ 1503 1503 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1504 - /* 0 - SRC_ADDR 1504 + /* 0 - DST_ADDR 1505 1505 * 1 - GDS 1506 1506 */ 1507 1507 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) ··· 1516 1516 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1517 1517 /* COMMAND */ 1518 1518 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1519 - # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1519 + # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1520 1520 /* 0 - none 1521 1521 * 1 - 8 in 16 1522 1522 * 2 - 8 in 32
+14 -7
drivers/gpu/drm/radeon/r600_hdmi.c
··· 57 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58 58 /* 32kHz 44.1kHz 48kHz */ 59 59 /* Clock N CTS N CTS N CTS */ 60 - { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 60 + { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 - { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 66 + { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 - { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 68 + { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 71 71 }; ··· 75 75 */ 76 76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77 77 { 78 - if (*CTS == 0) 79 - *CTS = clock * N / (128 * freq) * 1000; 78 + u64 n; 79 + u32 d; 80 + 81 + if (*CTS == 0) { 82 + n = (u64)clock * (u64)N * 1000ULL; 83 + d = 128 * freq; 84 + do_div(n, d); 85 + *CTS = n; 86 + } 80 87 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 81 88 N, *CTS, freq); 82 89 } ··· 451 444 } 452 445 453 446 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 454 - HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 455 - HDMI0_ACR_SOURCE); /* select SW CTS value */ 447 + HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ 448 + HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 456 449 457 450 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 458 451 HDMI0_NULL_SEND | /* send null packets when required */
+1 -1
drivers/gpu/drm/radeon/r600d.h
··· 1523 1523 */ 1524 1524 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1525 1525 /* COMMAND */ 1526 - # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1526 + # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1527 1527 /* 0 - none 1528 1528 * 1 - 8 in 16 1529 1529 * 2 - 8 in 32
+3
drivers/gpu/drm/radeon/radeon_pm.c
··· 945 945 if (enable) { 946 946 mutex_lock(&rdev->pm.mutex); 947 947 rdev->pm.dpm.uvd_active = true; 948 + /* disable this for now */ 949 + #if 0 948 950 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 949 951 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 950 952 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) ··· 956 954 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 957 955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 958 956 else 957 + #endif 959 958 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 960 959 rdev->pm.dpm.state = dpm_state; 961 960 mutex_unlock(&rdev->pm.mutex);
+2 -2
drivers/gpu/drm/radeon/radeon_test.c
··· 36 36 struct radeon_bo *vram_obj = NULL; 37 37 struct radeon_bo **gtt_obj = NULL; 38 38 uint64_t gtt_addr, vram_addr; 39 - unsigned i, n, size; 40 - int r, ring; 39 + unsigned n, size; 40 + int i, r, ring; 41 41 42 42 switch (flag) { 43 43 case RADEON_TEST_COPY_DMA:
+2 -1
drivers/gpu/drm/radeon/radeon_uvd.c
··· 798 798 (rdev->pm.dpm.hd != hd)) { 799 799 rdev->pm.dpm.sd = sd; 800 800 rdev->pm.dpm.hd = hd; 801 - streams_changed = true; 801 + /* disable this for now */ 802 + /*streams_changed = true;*/ 802 803 } 803 804 } 804 805
+10
drivers/gpu/drm/radeon/si.c
··· 85 85 uint32_t incr, uint32_t flags); 86 86 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev, 87 87 bool enable); 88 + static void si_fini_pg(struct radeon_device *rdev); 89 + static void si_fini_cg(struct radeon_device *rdev); 90 + static void si_rlc_stop(struct radeon_device *rdev); 88 91 89 92 static const u32 verde_rlc_save_restore_register_list[] = 90 93 { ··· 3610 3607 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 3611 3608 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3612 3609 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3610 + 3611 + /* disable PG/CG */ 3612 + si_fini_pg(rdev); 3613 + si_fini_cg(rdev); 3614 + 3615 + /* stop the rlc */ 3616 + si_rlc_stop(rdev); 3613 3617 3614 3618 /* Disable CP parsing/prefetching */ 3615 3619 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+3 -3
drivers/gpu/drm/radeon/si_dpm.c
··· 5208 5208 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5209 5209 } 5210 5210 j++; 5211 - if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5211 + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5212 5212 return -EINVAL; 5213 5213 5214 5214 if (!pi->mem_gddr5) { ··· 5218 5218 table->mc_reg_table_entry[k].mc_data[j] = 5219 5219 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5220 5220 j++; 5221 - if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5221 + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5222 5222 return -EINVAL; 5223 5223 } 5224 5224 break; ··· 5231 5231 (temp_reg & 0xffff0000) | 5232 5232 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5233 5233 j++; 5234 - if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5234 + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5235 5235 return -EINVAL; 5236 5236 break; 5237 5237 default:
+2 -2
drivers/gpu/drm/radeon/sid.h
··· 1553 1553 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1554 1554 */ 1555 1555 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1556 - /* 0 - SRC_ADDR 1556 + /* 0 - DST_ADDR 1557 1557 * 1 - GDS 1558 1558 */ 1559 1559 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) ··· 1568 1568 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1569 1569 /* COMMAND */ 1570 1570 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1571 - # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1571 + # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1572 1572 /* 0 - none 1573 1573 * 1 - 8 in 16 1574 1574 * 2 - 8 in 32
+1 -1
drivers/gpu/drm/radeon/trinity_dpm.c
··· 1868 1868 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 1869 1869 pi->at[i] = TRINITY_AT_DFLT; 1870 1870 1871 - pi->enable_bapm = true; 1871 + pi->enable_bapm = false; 1872 1872 pi->enable_nbps_policy = true; 1873 1873 pi->enable_sclk_ds = true; 1874 1874 pi->enable_gfx_power_gating = true;