tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/msm: resync generated headers

resync to latest envytools db, fixes a typo: s/mpd4/mdp4/

Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: David Brown <davidb@codeaurora.org>

Rob Clark 22ba8b6b b4b15c86

+169 -115
+37 -5
drivers/gpu/drm/msm/adreno/a2xx.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) 13 + - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) 16 - - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) 15 + - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 16 + - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17 17 18 18 Copyright (C) 2013 by the following authors: 19 19 - Rob Clark <robdclark@gmail.com> (robclark) ··· 316 316 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 317 317 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 318 318 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 319 + 320 + #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 321 + #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 322 + #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 323 + static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 324 + { 325 + return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 326 + } 327 + #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 328 + #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 329 + #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 330 + #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 331 + #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 332 + #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 333 + static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 334 + { 335 + return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 336 + } 337 + #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 338 + #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 339 + #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 340 + #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 341 + #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 342 + static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 343 + { 344 + return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 345 + } 346 + #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 347 + #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 348 + #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 349 + #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 350 + #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 319 351 320 352 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 321 353 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
+34 -12
drivers/gpu/drm/msm/adreno/a3xx.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) 13 + - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) 16 - - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) 15 + - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 16 + - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17 17 18 18 Copyright (C) 2013 by the following authors: 19 19 - Rob Clark <robdclark@gmail.com> (robclark) ··· 637 637 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 638 638 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 639 639 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 640 - #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007fc 641 - #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 2 642 - static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(uint32_t val) 640 + #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 641 + #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 642 + #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 643 + static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 643 644 { 644 - return ((val) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 645 + return ((((uint32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 645 646 } 646 647 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 647 648 ··· 746 745 } 747 746 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 748 747 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 748 + #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 749 749 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 750 750 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 751 751 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) ··· 769 767 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 770 768 } 771 769 772 - #define REG_A3XX_UNKNOWN_20C3 0x000020c3 770 + #define REG_A3XX_RB_ALPHA_REF 0x000020c3 771 + #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 772 + #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 773 + static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 774 + { 775 + return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 776 + } 777 + #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 778 + #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 779 + static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 780 + { 781 + return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 782 + } 773 783 774 784 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 775 785 ··· 1016 1002 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1017 1003 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1018 1004 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1019 - #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_ENABLE 0x00000008 1005 + #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1020 1006 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1021 1007 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1022 1008 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) ··· 1052 1038 1053 1039 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1054 1040 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1055 - #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000004 1041 + #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1042 + #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1056 1043 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1057 1044 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1058 1045 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) ··· 2089 2074 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2090 2075 2091 2076 #define REG_A3XX_TEX_SAMP_0 0x00000000 2077 + #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2092 2078 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2093 2079 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2094 2080 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) ··· 2149 2133 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2150 2134 { 2151 2135 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2136 + } 2137 + #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2138 + #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2139 + static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2140 + { 2141 + return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2152 2142 } 2153 2143 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2154 2144 #define A3XX_TEX_CONST_0_FMT__SHIFT 22
+5 -5
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) 13 + - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) 16 - - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) 15 + - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 16 + - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17 17 18 18 Copyright (C) 2013 by the following authors: 19 19 - Rob Clark <robdclark@gmail.com> (robclark)
+5 -5
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) 13 + - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) 16 - - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) 15 + - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 16 + - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17 17 18 18 Copyright (C) 2013 by the following authors: 19 19 - Rob Clark <robdclark@gmail.com> (robclark)
+3 -3
drivers/gpu/drm/msm/dsi/dsi.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36) 13 + - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
+3 -3
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36) 13 + - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
+3 -3
drivers/gpu/drm/msm/dsi/sfpb.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36) 13 + - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
+3 -3
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36) 13 + - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
+3 -3
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36) 13 + - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
+63 -63
drivers/gpu/drm/msm/mdp4/mdp4.xml.h
··· 4 4 /* Autogenerated file, DO NOT EDIT manually! 5 5 6 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 - http://0x04.net/cgit/index.cgi/rules-ng-ng 8 - git clone git://0x04.net/rules-ng-ng 7 + http://github.com/freedreno/envytools/ 8 + git clone https://github.com/freedreno/envytools.git 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 12 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36) 13 + - /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 14 14 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 15 15 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 16 16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) ··· 42 42 */ 43 43 44 44 45 - enum mpd4_bpc { 45 + enum mdp4_bpc { 46 46 BPC1 = 0, 47 47 BPC5 = 1, 48 48 BPC6 = 2, 49 49 BPC8 = 3, 50 50 }; 51 51 52 - enum mpd4_bpc_alpha { 52 + enum mdp4_bpc_alpha { 53 53 BPC1A = 0, 54 54 BPC4A = 1, 55 55 BPC6A = 2, 56 56 BPC8A = 3, 57 57 }; 58 58 59 - enum mpd4_alpha_type { 59 + enum mdp4_alpha_type { 60 60 FG_CONST = 0, 61 61 BG_CONST = 1, 62 62 FG_PIXEL = 2, 63 63 BG_PIXEL = 3, 64 64 }; 65 65 66 - enum mpd4_pipe { 66 + enum mdp4_pipe { 67 67 VG1 = 0, 68 68 VG2 = 1, 69 69 RGB1 = 2, ··· 73 73 VG4 = 6, 74 74 }; 75 75 76 - enum mpd4_mixer { 76 + enum mdp4_mixer { 77 77 MIXER0 = 0, 78 78 MIXER1 = 1, 79 79 MIXER2 = 2, 80 80 }; 81 81 82 - enum mpd4_mixer_stage_id { 82 + enum mdp4_mixer_stage_id { 83 83 STAGE_UNUSED = 0, 84 84 STAGE_BASE = 1, 85 85 STAGE0 = 2, ··· 194 194 #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0 195 195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007 196 196 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0 197 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mpd4_mixer_stage_id val) 197 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val) 198 198 { 199 199 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; 200 200 } 201 201 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008 202 202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070 203 203 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4 204 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mpd4_mixer_stage_id val) 204 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val) 205 205 { 206 206 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; 207 207 } 208 208 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080 209 209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700 210 210 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8 211 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mpd4_mixer_stage_id val) 211 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val) 212 212 { 213 213 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; 214 214 } 215 215 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800 216 216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000 217 217 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12 218 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mpd4_mixer_stage_id val) 218 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val) 219 219 { 220 220 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; 221 221 } 222 222 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000 223 223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000 224 224 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16 225 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mpd4_mixer_stage_id val) 225 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val) 226 226 { 227 227 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; 228 228 } 229 229 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000 230 230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000 231 231 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20 232 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mpd4_mixer_stage_id val) 232 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val) 233 233 { 234 234 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; 235 235 } 236 236 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000 237 237 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000 238 238 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24 239 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mpd4_mixer_stage_id val) 239 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val) 240 240 { 241 241 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; 242 242 } 243 243 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000 244 244 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000 245 245 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28 246 - static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mpd4_mixer_stage_id val) 246 + static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val) 247 247 { 248 248 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; 249 249 } ··· 254 254 #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100 255 255 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007 256 256 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0 257 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mpd4_mixer_stage_id val) 257 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val) 258 258 { 259 259 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; 260 260 } 261 261 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008 262 262 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070 263 263 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4 264 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mpd4_mixer_stage_id val) 264 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val) 265 265 { 266 266 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; 267 267 } 268 268 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080 269 269 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700 270 270 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8 271 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mpd4_mixer_stage_id val) 271 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val) 272 272 { 273 273 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; 274 274 } 275 275 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800 276 276 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000 277 277 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12 278 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mpd4_mixer_stage_id val) 278 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val) 279 279 { 280 280 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; 281 281 } 282 282 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000 283 283 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000 284 284 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16 285 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mpd4_mixer_stage_id val) 285 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val) 286 286 { 287 287 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; 288 288 } 289 289 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000 290 290 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000 291 291 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20 292 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mpd4_mixer_stage_id val) 292 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val) 293 293 { 294 294 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; 295 295 } 296 296 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000 297 297 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000 298 298 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24 299 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mpd4_mixer_stage_id val) 299 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val) 300 300 { 301 301 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; 302 302 } 303 303 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000 304 304 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000 305 305 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28 306 - static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mpd4_mixer_stage_id val) 306 + static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val) 307 307 { 308 308 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; 309 309 } ··· 369 369 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 370 370 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003 371 371 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0 372 - static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mpd4_alpha_type val) 372 + static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val) 373 373 { 374 374 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; 375 375 } ··· 377 377 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008 378 378 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030 379 379 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4 380 - static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mpd4_alpha_type val) 380 + static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val) 381 381 { 382 382 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; 383 383 } ··· 472 472 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 473 473 #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003 474 474 #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0 475 - static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mpd4_bpc val) 475 + static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val) 476 476 { 477 477 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; 478 478 } 479 479 #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c 480 480 #define MDP4_DMA_CONFIG_B_BPC__SHIFT 2 481 - static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mpd4_bpc val) 481 + static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val) 482 482 { 483 483 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; 484 484 } 485 485 #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030 486 486 #define MDP4_DMA_CONFIG_R_BPC__SHIFT 4 487 - static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mpd4_bpc val) 487 + static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val) 488 488 { 489 489 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; 490 490 } ··· 601 601 602 602 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 603 603 604 - static inline uint32_t REG_MDP4_PIPE(enum mpd4_pipe i0) { return 0x00020000 + 0x10000*i0; } 604 + static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 605 605 606 - static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mpd4_pipe i0) { return 0x00020000 + 0x10000*i0; } 606 + static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 607 607 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 608 608 #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 609 609 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) ··· 617 617 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; 618 618 } 619 619 620 - static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mpd4_pipe i0) { return 0x00020004 + 0x10000*i0; } 620 + static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } 621 621 #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000 622 622 #define MDP4_PIPE_SRC_XY_Y__SHIFT 16 623 623 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) ··· 631 631 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; 632 632 } 633 633 634 - static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mpd4_pipe i0) { return 0x00020008 + 0x10000*i0; } 634 + static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } 635 635 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000 636 636 #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16 637 637 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) ··· 645 645 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; 646 646 } 647 647 648 - static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mpd4_pipe i0) { return 0x0002000c + 0x10000*i0; } 648 + static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } 649 649 #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000 650 650 #define MDP4_PIPE_DST_XY_Y__SHIFT 16 651 651 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) ··· 659 659 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; 660 660 } 661 661 662 - static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mpd4_pipe i0) { return 0x00020010 + 0x10000*i0; } 662 + static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } 663 663 664 - static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mpd4_pipe i0) { return 0x00020014 + 0x10000*i0; } 664 + static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } 665 665 666 - static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mpd4_pipe i0) { return 0x00020018 + 0x10000*i0; } 666 + static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } 667 667 668 - static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mpd4_pipe i0) { return 0x00020040 + 0x10000*i0; } 668 + static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } 669 669 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff 670 670 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0 671 671 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) ··· 679 679 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; 680 680 } 681 681 682 - static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mpd4_pipe i0) { return 0x00020044 + 0x10000*i0; } 682 + static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } 683 683 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff 684 684 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0 685 685 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) ··· 693 693 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; 694 694 } 695 695 696 - static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mpd4_pipe i0) { return 0x00020048 + 0x10000*i0; } 696 + static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } 697 697 #define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 698 698 #define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16 699 699 static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val) ··· 707 707 return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK; 708 708 } 709 709 710 - static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mpd4_pipe i0) { return 0x00020050 + 0x10000*i0; } 710 + static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } 711 711 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 712 712 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 713 - static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mpd4_bpc val) 713 + static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val) 714 714 { 715 715 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; 716 716 } 717 717 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c 718 718 #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 719 - static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mpd4_bpc val) 719 + static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val) 720 720 { 721 721 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; 722 722 } 723 723 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 724 724 #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 725 - static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mpd4_bpc val) 725 + static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val) 726 726 { 727 727 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; 728 728 } 729 729 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 730 730 #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 731 - static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mpd4_bpc_alpha val) 731 + static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val) 732 732 { 733 733 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; 734 734 } ··· 750 750 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 751 751 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000 752 752 753 - static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mpd4_pipe i0) { return 0x00020054 + 0x10000*i0; } 753 + static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } 754 754 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff 755 755 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 756 756 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) ··· 776 776 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; 777 777 } 778 778 779 - static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mpd4_pipe i0) { return 0x00020058 + 0x10000*i0; } 779 + static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } 780 780 #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001 781 781 #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002 782 782 #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200 ··· 789 789 #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000 790 790 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000 791 791 792 - static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mpd4_pipe i0) { return 0x0002005c + 0x10000*i0; } 792 + static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } 793 793 794 - static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mpd4_pipe i0) { return 0x00020060 + 0x10000*i0; } 794 + static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } 795 795 796 - static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mpd4_pipe i0) { return 0x00021004 + 0x10000*i0; } 796 + static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } 797 797 798 - static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mpd4_pipe i0) { return 0x00021008 + 0x10000*i0; } 798 + static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } 799 799 800 - static inline uint32_t REG_MDP4_PIPE_CSC(enum mpd4_pipe i0) { return 0x00024000 + 0x10000*i0; } 800 + static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } 801 801 802 802 803 - static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 803 + static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 804 804 805 - static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 805 + static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 806 806 807 - static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 807 + static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 808 808 809 - static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 809 + static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 810 810 811 - static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 811 + static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 812 812 813 - static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 813 + static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 814 814 815 - static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 815 + static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 816 816 817 - static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 817 + static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 818 818 819 - static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 819 + static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 820 820 821 - static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 821 + static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 822 822 823 823 #define REG_MDP4_LCDC 0x000c0000 824 824
+5 -5
drivers/gpu/drm/msm/mdp4/mdp4_kms.h
··· 75 75 76 76 struct mdp4_format { 77 77 struct msm_format base; 78 - enum mpd4_bpc bpc_r, bpc_g, bpc_b; 79 - enum mpd4_bpc_alpha bpc_a; 78 + enum mdp4_bpc bpc_r, bpc_g, bpc_b; 79 + enum mdp4_bpc_alpha bpc_a; 80 80 uint8_t unpack[4]; 81 81 bool alpha_enable, unpack_tight; 82 82 uint8_t cpp, unpack_count; ··· 93 93 return msm_readl(mdp4_kms->mmio + reg); 94 94 } 95 95 96 - static inline uint32_t pipe2flush(enum mpd4_pipe pipe) 96 + static inline uint32_t pipe2flush(enum mdp4_pipe pipe) 97 97 { 98 98 switch (pipe) { 99 99 case VG1: return MDP4_OVERLAY_FLUSH_VG1; ··· 158 158 unsigned int crtc_w, unsigned int crtc_h, 159 159 uint32_t src_x, uint32_t src_y, 160 160 uint32_t src_w, uint32_t src_h); 161 - enum mpd4_pipe mdp4_plane_pipe(struct drm_plane *plane); 161 + enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane); 162 162 struct drm_plane *mdp4_plane_init(struct drm_device *dev, 163 - enum mpd4_pipe pipe_id, bool private_plane); 163 + enum mdp4_pipe pipe_id, bool private_plane); 164 164 165 165 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc); 166 166 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc);
+5 -5
drivers/gpu/drm/msm/mdp4/mdp4_plane.c
··· 22 22 struct drm_plane base; 23 23 const char *name; 24 24 25 - enum mpd4_pipe pipe; 25 + enum mdp4_pipe pipe; 26 26 27 27 uint32_t nformats; 28 28 uint32_t formats[32]; ··· 101 101 { 102 102 struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane); 103 103 struct mdp4_kms *mdp4_kms = get_kms(plane); 104 - enum mpd4_pipe pipe = mdp4_plane->pipe; 104 + enum mdp4_pipe pipe = mdp4_plane->pipe; 105 105 uint32_t iova; 106 106 107 107 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), ··· 129 129 { 130 130 struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane); 131 131 struct mdp4_kms *mdp4_kms = get_kms(plane); 132 - enum mpd4_pipe pipe = mdp4_plane->pipe; 132 + enum mdp4_pipe pipe = mdp4_plane->pipe; 133 133 const struct mdp4_format *format; 134 134 uint32_t op_mode = 0; 135 135 uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT; ··· 202 202 "VG3", "VG4", 203 203 }; 204 204 205 - enum mpd4_pipe mdp4_plane_pipe(struct drm_plane *plane) 205 + enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane) 206 206 { 207 207 struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane); 208 208 return mdp4_plane->pipe; ··· 210 210 211 211 /* initialize plane */ 212 212 struct drm_plane *mdp4_plane_init(struct drm_device *dev, 213 - enum mpd4_pipe pipe_id, bool private_plane) 213 + enum mdp4_pipe pipe_id, bool private_plane) 214 214 { 215 215 struct msm_drm_private *priv = dev->dev_private; 216 216 struct drm_plane *plane = NULL;