tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/xe/irq: Check fuse mask for media engines

Just like the other engines, check xe_hw_engine_mask_per_class() for VCS
and VECS to account for architectural availability of those registers.
With that, all the possibly available media engines can have their
interrupts enabled.

Bspec: 54030
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-20-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi 22b7117e 490fa786

+17 -3
+3
drivers/gpu/drm/xe/regs/xe_irq_regs.h
··· 65 65 #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF) 66 66 #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF) 67 67 #define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF) 68 + #define VCS4_VCS5_INTR_MASK XE_REG(0x1900b0, XE_REG_OPTION_VF) 69 + #define VCS6_VCS7_INTR_MASK XE_REG(0x1900b4, XE_REG_OPTION_VF) 68 70 #define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF) 71 + #define VECS2_VECS3_INTR_MASK XE_REG(0x1900d4, XE_REG_OPTION_VF) 69 72 #define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4) 70 73 #define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF) 71 74 #define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF)
+14 -3
drivers/gpu/drm/xe/xe_irq.c
··· 205 205 } 206 206 207 207 if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) { 208 + u32 vcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE); 209 + u32 vecs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE); 208 210 u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER); 209 211 210 212 /* Enable interrupts for each engine class */ ··· 217 215 /* Unmask interrupts for each engine instance */ 218 216 val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) | 219 217 REG_FIELD_PREP(ENGINE0_MASK, vcs_mask)); 220 - xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val); 221 - xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val); 218 + if (vcs_fuse_mask & (BIT(0) | BIT(1))) 219 + xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val); 220 + if (vcs_fuse_mask & (BIT(2) | BIT(3))) 221 + xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val); 222 + if (vcs_fuse_mask & (BIT(4) | BIT(5))) 223 + xe_mmio_write32(mmio, VCS4_VCS5_INTR_MASK, val); 224 + if (vcs_fuse_mask & (BIT(6) | BIT(7))) 225 + xe_mmio_write32(mmio, VCS6_VCS7_INTR_MASK, val); 222 226 223 227 val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) | 224 228 REG_FIELD_PREP(ENGINE0_MASK, vecs_mask)); 225 - xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val); 229 + if (vecs_fuse_mask & (BIT(0) | BIT(1))) 230 + xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val); 231 + if (vecs_fuse_mask & (BIT(2) | BIT(3))) 232 + xe_mmio_write32(mmio, VECS2_VECS3_INTR_MASK, val); 226 233 227 234 /* 228 235 * the heci2 interrupt is enabled via the same register as the