tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
[MIPS] txx9tmr clockevent/clocksource driver
Convert jmr3927_clock_event_device to more generic
txx9tmr_clock_event_device which supports one-shot mode. The
txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer
interrupt was not available.
Convert jmr3927_hpt_read to txx9_clocksource driver which does not
depends jiffies anymore. The txx9_clocksource itself can be used for
TX49, but normally TX49 uses higher precision clocksource_mips.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Atsushi Nemoto
and committed by
Ralf Baechle
229f773e
22df3f53
+273
-145
+6
arch/mips/Kconfig
+6
arch/mips/Kconfig
···
583
583
584
584
config TOSHIBA_JMR3927
585
585
bool "Toshiba JMR-TX3927 board"
586
+
select CEVT_TXX9
586
587
select DMA_NONCOHERENT
587
588
select HW_HAS_PCI
588
589
select MIPS_TX3927
···
598
597
config TOSHIBA_RBTX4927
599
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bool "Toshiba RBTX49[23]7 board"
600
599
select CEVT_R4K
600
+
select CEVT_TXX9
601
601
select DMA_NONCOHERENT
602
602
select HAS_TXX9_SERIAL
603
603
select HW_HAS_PCI
···
620
618
config TOSHIBA_RBTX4938
621
619
bool "Toshiba RBTX4938 board"
622
620
select CEVT_R4K
621
+
select CEVT_TXX9
623
622
select DMA_NONCOHERENT
624
623
select HAS_TXX9_SERIAL
625
624
select HW_HAS_PCI
···
737
734
bool
738
735
739
736
config CEVT_R4K
737
+
bool
738
+
739
+
config CEVT_TXX9
740
740
bool
741
741
742
742
config CFE
+7
-76
arch/mips/jmr3927/rbhma3100/setup.c
+7
-76
arch/mips/jmr3927/rbhma3100/setup.c
···
27
27
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
28
28
*/
29
29
30
-
#include <linux/clockchips.h>
31
30
#include <linux/init.h>
32
31
#include <linux/kernel.h>
33
32
#include <linux/kdev_t.h>
34
33
#include <linux/types.h>
35
-
#include <linux/sched.h>
36
34
#include <linux/pci.h>
37
35
#include <linux/ide.h>
38
-
#include <linux/irq.h>
39
36
#include <linux/ioport.h>
40
-
#include <linux/param.h> /* for HZ */
41
37
#include <linux/delay.h>
42
38
#include <linux/pm.h>
43
39
#include <linux/platform_device.h>
···
44
48
#endif
45
49
46
50
#include <asm/addrspace.h>
47
-
#include <asm/time.h>
51
+
#include <asm/txx9tmr.h>
48
52
#include <asm/reboot.h>
49
53
#include <asm/jmr3927/jmr3927.h>
50
54
#include <asm/mipsregs.h>
51
55
52
56
extern void puts(const char *cp);
53
-
54
-
/* Tick Timer divider */
55
-
#define JMR3927_TIMER_CCD 0 /* 1/2 */
56
-
#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
57
57
58
58
/* don't enable - see errata */
59
59
static int jmr3927_ccfg_toeon;
···
85
93
while (1);
86
94
}
87
95
88
-
static cycle_t jmr3927_hpt_read(void)
89
-
{
90
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/* We assume this function is called xtime_lock held. */
91
-
return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
92
-
}
93
-
94
-
static void jmr3927_set_mode(enum clock_event_mode mode,
95
-
struct clock_event_device *evt)
96
-
{
97
-
/* Nothing to do here */
98
-
}
99
-
100
-
struct clock_event_device jmr3927_clock_event_device = {
101
-
.name = "MIPS",
102
-
.features = CLOCK_EVT_FEAT_PERIODIC,
103
-
.shift = 32,
104
-
.rating = 300,
105
-
.cpumask = CPU_MASK_CPU0,
106
-
.irq = JMR3927_IRQ_TICK,
107
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.set_mode = jmr3927_set_mode,
108
-
};
109
-
110
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static irqreturn_t jmr3927_timer_interrupt(int irq, void *dev_id)
111
-
{
112
-
struct clock_event_device *cd = &jmr3927_clock_event_device;
113
-
114
-
jmr3927_tmrptr->tisr = 0; /* ack interrupt */
115
-
116
-
cd->event_handler(cd);
117
-
118
-
return IRQ_HANDLED;
119
-
}
120
-
121
-
static struct irqaction jmr3927_timer_irqaction = {
122
-
.handler = jmr3927_timer_interrupt,
123
-
.flags = IRQF_DISABLED | IRQF_PERCPU,
124
-
.name = "jmr3927-timer",
125
-
};
126
-
127
96
void __init plat_time_init(void)
128
97
{
129
-
struct clock_event_device *cd;
130
-
131
-
clocksource_mips.read = jmr3927_hpt_read;
132
-
mips_hpt_frequency = JMR3927_TIMER_CLK;
133
-
134
-
jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
135
-
jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
136
-
jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
137
-
jmr3927_tmrptr->tcr =
138
-
TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
139
-
140
-
cd = &jmr3927_clock_event_device;
141
-
/* Calculate the min / max delta */
142
-
cd->mult = div_sc((unsigned long) JMR3927_IMCLK, NSEC_PER_SEC, 32);
143
-
cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
144
-
cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
145
-
clockevents_register_device(cd);
146
-
147
-
setup_irq(JMR3927_IRQ_TICK, &jmr3927_timer_irqaction);
98
+
txx9_clockevent_init(TX3927_TMR_REG(0),
99
+
TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
100
+
JMR3927_IMCLK);
101
+
txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
148
102
}
149
103
150
104
#define DO_WRITE_THROUGH
···
255
317
tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
256
318
257
319
/* TMR */
258
-
/* disable all timers */
259
-
for (i = 0; i < TX3927_NR_TMR; i++) {
260
-
tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
261
-
tx3927_tmrptr(i)->tisr = 0;
262
-
tx3927_tmrptr(i)->cpra = 0xffffffff;
263
-
tx3927_tmrptr(i)->itmr = 0;
264
-
tx3927_tmrptr(i)->ccdr = 0;
265
-
tx3927_tmrptr(i)->pgmr = 0;
266
-
}
320
+
for (i = 0; i < TX3927_NR_TMR; i++)
321
+
txx9_tmr_init(TX3927_TMR_REG(i));
267
322
268
323
/* DMA */
269
324
tx3927_dmaptr->mcr = 0;
+1
arch/mips/kernel/Makefile
+1
arch/mips/kernel/Makefile
+171
arch/mips/kernel/cevt-txx9.c
+171
arch/mips/kernel/cevt-txx9.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Based on linux/arch/mips/kernel/cevt-r4k.c,
7
+
* linux/arch/mips/jmr3927/rbhma3100/setup.c
8
+
*
9
+
* Copyright 2001 MontaVista Software Inc.
10
+
* Copyright (C) 2000-2001 Toshiba Corporation
11
+
* Copyright (C) 2007 MIPS Technologies, Inc.
12
+
* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
13
+
*/
14
+
#include <linux/init.h>
15
+
#include <linux/interrupt.h>
16
+
#include <asm/time.h>
17
+
#include <asm/txx9tmr.h>
18
+
19
+
#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
20
+
#define TIMER_CCD 0 /* 1/2 */
21
+
#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
22
+
23
+
static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr;
24
+
25
+
static cycle_t txx9_cs_read(void)
26
+
{
27
+
return __raw_readl(&txx9_cs_tmrptr->trr);
28
+
}
29
+
30
+
/* Use 1 bit smaller width to use full bits in that width */
31
+
#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
32
+
33
+
static struct clocksource txx9_clocksource = {
34
+
.name = "TXx9",
35
+
.rating = 200,
36
+
.read = txx9_cs_read,
37
+
.mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
38
+
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
39
+
};
40
+
41
+
void __init txx9_clocksource_init(unsigned long baseaddr,
42
+
unsigned int imbusclk)
43
+
{
44
+
struct txx9_tmr_reg __iomem *tmrptr;
45
+
46
+
clocksource_set_clock(&txx9_clocksource, TIMER_CLK(imbusclk));
47
+
clocksource_register(&txx9_clocksource);
48
+
49
+
tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
50
+
__raw_writel(TCR_BASE, &tmrptr->tcr);
51
+
__raw_writel(0, &tmrptr->tisr);
52
+
__raw_writel(TIMER_CCD, &tmrptr->ccdr);
53
+
__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
54
+
__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
55
+
__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
56
+
txx9_cs_tmrptr = tmrptr;
57
+
}
58
+
59
+
static struct txx9_tmr_reg __iomem *txx9_tmrptr;
60
+
61
+
static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
62
+
{
63
+
/* stop and reset counter */
64
+
__raw_writel(TCR_BASE, &tmrptr->tcr);
65
+
/* clear pending interrupt */
66
+
__raw_writel(0, &tmrptr->tisr);
67
+
}
68
+
69
+
static void txx9tmr_set_mode(enum clock_event_mode mode,
70
+
struct clock_event_device *evt)
71
+
{
72
+
struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
73
+
74
+
txx9tmr_stop_and_clear(tmrptr);
75
+
switch (mode) {
76
+
case CLOCK_EVT_MODE_PERIODIC:
77
+
__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,
78
+
&tmrptr->itmr);
79
+
/* start timer */
80
+
__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>
81
+
evt->shift,
82
+
&tmrptr->cpra);
83
+
__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
84
+
break;
85
+
case CLOCK_EVT_MODE_SHUTDOWN:
86
+
case CLOCK_EVT_MODE_UNUSED:
87
+
__raw_writel(0, &tmrptr->itmr);
88
+
break;
89
+
case CLOCK_EVT_MODE_ONESHOT:
90
+
__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
91
+
break;
92
+
case CLOCK_EVT_MODE_RESUME:
93
+
__raw_writel(TIMER_CCD, &tmrptr->ccdr);
94
+
__raw_writel(0, &tmrptr->itmr);
95
+
break;
96
+
}
97
+
}
98
+
99
+
static int txx9tmr_set_next_event(unsigned long delta,
100
+
struct clock_event_device *evt)
101
+
{
102
+
struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
103
+
104
+
txx9tmr_stop_and_clear(tmrptr);
105
+
/* start timer */
106
+
__raw_writel(delta, &tmrptr->cpra);
107
+
__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
108
+
return 0;
109
+
}
110
+
111
+
static struct clock_event_device txx9tmr_clock_event_device = {
112
+
.name = "TXx9",
113
+
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
114
+
.rating = 200,
115
+
.cpumask = CPU_MASK_CPU0,
116
+
.set_mode = txx9tmr_set_mode,
117
+
.set_next_event = txx9tmr_set_next_event,
118
+
};
119
+
120
+
static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
121
+
{
122
+
struct clock_event_device *cd = &txx9tmr_clock_event_device;
123
+
struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
124
+
125
+
__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
126
+
cd->event_handler(cd);
127
+
return IRQ_HANDLED;
128
+
}
129
+
130
+
static struct irqaction txx9tmr_irq = {
131
+
.handler = txx9tmr_interrupt,
132
+
.flags = IRQF_DISABLED | IRQF_PERCPU,
133
+
.name = "txx9tmr",
134
+
};
135
+
136
+
void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
137
+
unsigned int imbusclk)
138
+
{
139
+
struct clock_event_device *cd = &txx9tmr_clock_event_device;
140
+
struct txx9_tmr_reg __iomem *tmrptr;
141
+
142
+
tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
143
+
txx9tmr_stop_and_clear(tmrptr);
144
+
__raw_writel(TIMER_CCD, &tmrptr->ccdr);
145
+
__raw_writel(0, &tmrptr->itmr);
146
+
txx9_tmrptr = tmrptr;
147
+
148
+
clockevent_set_clock(cd, TIMER_CLK(imbusclk));
149
+
cd->max_delta_ns =
150
+
clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
151
+
cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
152
+
cd->irq = irq;
153
+
clockevents_register_device(cd);
154
+
setup_irq(irq, &txx9tmr_irq);
155
+
printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
156
+
baseaddr, irq);
157
+
}
158
+
159
+
void __init txx9_tmr_init(unsigned long baseaddr)
160
+
{
161
+
struct txx9_tmr_reg __iomem *tmrptr;
162
+
163
+
tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
164
+
__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
165
+
__raw_writel(0, &tmrptr->tisr);
166
+
__raw_writel(0xffffffff, &tmrptr->cpra);
167
+
__raw_writel(0, &tmrptr->itmr);
168
+
__raw_writel(0, &tmrptr->ccdr);
169
+
__raw_writel(0, &tmrptr->pgmr);
170
+
iounmap(tmrptr);
171
+
}
+9
-8
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+9
-8
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
···
63
63
#include <asm/processor.h>
64
64
#include <asm/reboot.h>
65
65
#include <asm/time.h>
66
+
#include <asm/txx9tmr.h>
66
67
#include <linux/bootmem.h>
67
68
#include <linux/blkdev.h>
68
69
#ifdef CONFIG_TOSHIBA_FPCIB0
···
94
93
95
94
#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
96
95
#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
97
-
#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
98
96
#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
99
97
#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
100
98
#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
···
130
130
131
131
int tx4927_using_backplane = 0;
132
132
133
-
extern void gt64120_time_init(void);
134
133
extern void toshiba_rbtx4927_irq_setup(void);
135
134
136
135
char *prom_getcmdline(void);
···
720
721
721
722
void __init toshiba_rbtx4927_setup(void)
722
723
{
724
+
int i;
723
725
u32 cp0_config;
724
726
char *argptr;
725
727
···
763
763
_machine_restart = toshiba_rbtx4927_restart;
764
764
_machine_halt = toshiba_rbtx4927_halt;
765
765
pm_power_off = toshiba_rbtx4927_power_off;
766
+
767
+
for (i = 0; i < TX4927_NR_TMR; i++)
768
+
txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
766
769
767
770
#ifdef CONFIG_PCI
768
771
···
895
892
#ifdef CONFIG_SERIAL_TXX9
896
893
{
897
894
extern int early_serial_txx9_setup(struct uart_port *port);
898
-
int i;
899
895
struct uart_port req;
900
896
for(i = 0; i < 2; i++) {
901
897
memset(&req, 0, sizeof(req));
···
939
937
void __init
940
938
toshiba_rbtx4927_time_init(void)
941
939
{
942
-
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
943
-
944
940
mips_hpt_frequency = tx4927_cpu_clock / 2;
945
-
946
-
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
947
-
941
+
if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
942
+
txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
943
+
TXX9_IRQ_BASE + 17,
944
+
50000000);
948
945
}
949
946
950
947
static int __init toshiba_rbtx4927_rtc_init(void)
+7
-12
arch/mips/tx4938/toshiba_rbtx4938/setup.c
+7
-12
arch/mips/tx4938/toshiba_rbtx4938/setup.c
···
26
26
#include <asm/reboot.h>
27
27
#include <asm/irq.h>
28
28
#include <asm/time.h>
29
+
#include <asm/txx9tmr.h>
29
30
#include <asm/uaccess.h>
30
31
#include <asm/io.h>
31
32
#include <asm/bootinfo.h>
···
774
773
}
775
774
776
775
/* TMR */
777
-
/* disable all timers */
778
-
for (i = 0; i < TX4938_NR_TMR; i++) {
779
-
tx4938_tmrptr(i)->tcr = 0x00000020;
780
-
tx4938_tmrptr(i)->tisr = 0;
781
-
tx4938_tmrptr(i)->cpra = 0xffffffff;
782
-
tx4938_tmrptr(i)->itmr = 0;
783
-
tx4938_tmrptr(i)->ccdr = 0;
784
-
tx4938_tmrptr(i)->pgmr = 0;
785
-
}
776
+
for (i = 0; i < TX4938_NR_TMR; i++)
777
+
txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
786
778
787
779
/* enable DMA */
788
780
TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
···
846
852
847
853
#endif /* CONFIG_PCI */
848
854
849
-
/* We use onchip r4k counter or TMR timer as our system wide timer
850
-
* interrupt running at 100HZ. */
851
-
852
855
void __init plat_time_init(void)
853
856
{
854
857
mips_hpt_frequency = txx9_cpu_clock / 2;
858
+
if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
859
+
txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
860
+
TXX9_IRQ_BASE + TX4938_IR_TMR(0),
861
+
txx9_gbus_clock / 2);
855
862
}
856
863
857
864
void __init toshiba_rbtx4938_setup(void)
+1
-8
include/asm-mips/jmr3927/jmr3927.h
+1
-8
include/asm-mips/jmr3927/jmr3927.h
···
132
132
#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133
133
#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134
134
#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135
-
#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0)
136
-
#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
137
-
#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
135
+
#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
138
136
#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
139
137
#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
140
138
#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
···
146
148
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
147
149
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
148
150
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
149
-
/* Clock Tick (10ms) */
150
-
#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
151
151
152
152
/* Clocks */
153
153
#define JMR3927_CORECLK 132710400 /* 132.7MHz */
154
154
#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
155
155
#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
156
-
157
-
#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
158
-
159
156
160
157
/*
161
158
* TX3927 Pin Configuration:
+1
-3
include/asm-mips/jmr3927/tx3927.h
+1
-3
include/asm-mips/jmr3927/tx3927.h
-37
include/asm-mips/jmr3927/txx927.h
-37
include/asm-mips/jmr3927/txx927.h
···
10
10
#ifndef __ASM_TXX927_H
11
11
#define __ASM_TXX927_H
12
12
13
-
struct txx927_tmr_reg {
14
-
volatile unsigned long tcr;
15
-
volatile unsigned long tisr;
16
-
volatile unsigned long cpra;
17
-
volatile unsigned long cprb;
18
-
volatile unsigned long itmr;
19
-
volatile unsigned long unused0[3];
20
-
volatile unsigned long ccdr;
21
-
volatile unsigned long unused1[3];
22
-
volatile unsigned long pgmr;
23
-
volatile unsigned long unused2[3];
24
-
volatile unsigned long wtmr;
25
-
volatile unsigned long unused3[43];
26
-
volatile unsigned long trr;
27
-
};
28
-
29
13
struct txx927_sio_reg {
30
14
volatile unsigned long lcr;
31
15
volatile unsigned long dicr;
···
33
49
volatile unsigned long maskcpu;
34
50
volatile unsigned long maskext;
35
51
};
36
-
37
-
/*
38
-
* TMR
39
-
*/
40
-
/* TMTCR : Timer Control */
41
-
#define TXx927_TMTCR_TCE 0x00000080
42
-
#define TXx927_TMTCR_CCDE 0x00000040
43
-
#define TXx927_TMTCR_CRE 0x00000020
44
-
#define TXx927_TMTCR_ECES 0x00000008
45
-
#define TXx927_TMTCR_CCS 0x00000004
46
-
#define TXx927_TMTCR_TMODE_MASK 0x00000003
47
-
#define TXx927_TMTCR_TMODE_ITVL 0x00000000
48
-
49
-
/* TMTISR : Timer Int. Status */
50
-
#define TXx927_TMTISR_TPIBS 0x00000004
51
-
#define TXx927_TMTISR_TPIAS 0x00000002
52
-
#define TXx927_TMTISR_TIIS 0x00000001
53
-
54
-
/* TMTITMR : Interval Timer Mode */
55
-
#define TXx927_TMTITMR_TIIE 0x00008000
56
-
#define TXx927_TMTITMR_TZCE 0x00000001
57
52
58
53
/*
59
54
* SIO
+3
include/asm-mips/tx4927/tx4927_pci.h
+3
include/asm-mips/tx4927/tx4927_pci.h
···
9
9
#define __ASM_TX4927_TX4927_PCI_H
10
10
11
11
#define TX4927_CCFG_TOE 0x00004000
12
+
#define TX4927_CCFG_TINTDIS 0x01000000
12
13
13
14
#define TX4927_PCIMEM 0x08000000
14
15
#define TX4927_PCIMEM_SIZE 0x08000000
···
21
20
#define TX4927_PCIC_REG 0xff1fd000
22
21
#define TX4927_CCFG_REG 0xff1fe000
23
22
#define TX4927_IRC_REG 0xff1ff600
23
+
#define TX4927_NR_TMR 3
24
+
#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
24
25
#define TX4927_CE3 0x17f00000 /* 1M */
25
26
#define TX4927_PCIRESET_ADDR 0xbc00f006
26
27
#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
-1
include/asm-mips/tx4938/tx4938.h
-1
include/asm-mips/tx4938/tx4938.h
···
641
641
#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
642
642
#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
643
643
#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
644
-
#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
645
644
#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
646
645
#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
647
646
#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
+67
include/asm-mips/txx9tmr.h
+67
include/asm-mips/txx9tmr.h
···
1
+
/*
2
+
* include/asm-mips/txx9tmr.h
3
+
* TX39/TX49 timer controller definitions.
4
+
*
5
+
* This file is subject to the terms and conditions of the GNU General Public
6
+
* License. See the file "COPYING" in the main directory of this archive
7
+
* for more details.
8
+
*/
9
+
#ifndef __ASM_TXX9TMR_H
10
+
#define __ASM_TXX9TMR_H
11
+
12
+
#include <linux/types.h>
13
+
14
+
struct txx9_tmr_reg {
15
+
u32 tcr;
16
+
u32 tisr;
17
+
u32 cpra;
18
+
u32 cprb;
19
+
u32 itmr;
20
+
u32 unused0[3];
21
+
u32 ccdr;
22
+
u32 unused1[3];
23
+
u32 pgmr;
24
+
u32 unused2[3];
25
+
u32 wtmr;
26
+
u32 unused3[43];
27
+
u32 trr;
28
+
};
29
+
30
+
/* TMTCR : Timer Control */
31
+
#define TXx9_TMTCR_TCE 0x00000080
32
+
#define TXx9_TMTCR_CCDE 0x00000040
33
+
#define TXx9_TMTCR_CRE 0x00000020
34
+
#define TXx9_TMTCR_ECES 0x00000008
35
+
#define TXx9_TMTCR_CCS 0x00000004
36
+
#define TXx9_TMTCR_TMODE_MASK 0x00000003
37
+
#define TXx9_TMTCR_TMODE_ITVL 0x00000000
38
+
#define TXx9_TMTCR_TMODE_PGEN 0x00000001
39
+
#define TXx9_TMTCR_TMODE_WDOG 0x00000002
40
+
41
+
/* TMTISR : Timer Int. Status */
42
+
#define TXx9_TMTISR_TPIBS 0x00000004
43
+
#define TXx9_TMTISR_TPIAS 0x00000002
44
+
#define TXx9_TMTISR_TIIS 0x00000001
45
+
46
+
/* TMITMR : Interval Timer Mode */
47
+
#define TXx9_TMITMR_TIIE 0x00008000
48
+
#define TXx9_TMITMR_TZCE 0x00000001
49
+
50
+
/* TMWTMR : Watchdog Timer Mode */
51
+
#define TXx9_TMWTMR_TWIE 0x00008000
52
+
#define TXx9_TMWTMR_WDIS 0x00000080
53
+
#define TXx9_TMWTMR_TWC 0x00000001
54
+
55
+
void txx9_clocksource_init(unsigned long baseaddr,
56
+
unsigned int imbusclk);
57
+
void txx9_clockevent_init(unsigned long baseaddr, int irq,
58
+
unsigned int imbusclk);
59
+
void txx9_tmr_init(unsigned long baseaddr);
60
+
61
+
#ifdef CONFIG_CPU_TX39XX
62
+
#define TXX9_TIMER_BITS 24
63
+
#else
64
+
#define TXX9_TIMER_BITS 32
65
+
#endif
66
+
67
+
#endif /* __ASM_TXX9TMR_H */