Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu/dce8: simplify hpd code

Use an address offset like other dce code.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

+54 -190
+8
drivers/gpu/drm/amd/amdgpu/cikd.h
··· 43 43 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 44 44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 45 45 46 + /* hpd instance offsets */ 47 + #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 48 + #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 49 + #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 50 + #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 51 + #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 52 + #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 53 + 46 54 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 47 55 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 48 56
+46 -190
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 56 56 CRTC5_REGISTER_OFFSET 57 57 }; 58 58 59 + static const u32 hpd_offsets[] = 60 + { 61 + HPD0_REGISTER_OFFSET, 62 + HPD1_REGISTER_OFFSET, 63 + HPD2_REGISTER_OFFSET, 64 + HPD3_REGISTER_OFFSET, 65 + HPD4_REGISTER_OFFSET, 66 + HPD5_REGISTER_OFFSET 67 + }; 68 + 59 69 static const uint32_t dig_offsets[] = { 60 70 CRTC0_REGISTER_OFFSET, 61 71 CRTC1_REGISTER_OFFSET, ··· 113 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 105 } }; 116 - 117 - static const uint32_t hpd_int_control_offsets[6] = { 118 - mmDC_HPD1_INT_CONTROL, 119 - mmDC_HPD2_INT_CONTROL, 120 - mmDC_HPD3_INT_CONTROL, 121 - mmDC_HPD4_INT_CONTROL, 122 - mmDC_HPD5_INT_CONTROL, 123 - mmDC_HPD6_INT_CONTROL, 124 - }; 125 106 126 107 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, 127 108 u32 block_offset, u32 reg) ··· 279 278 { 280 279 bool connected = false; 281 280 282 - switch (hpd) { 283 - case AMDGPU_HPD_1: 284 - if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 285 - connected = true; 286 - break; 287 - case AMDGPU_HPD_2: 288 - if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK) 289 - connected = true; 290 - break; 291 - case AMDGPU_HPD_3: 292 - if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK) 293 - connected = true; 294 - break; 295 - case AMDGPU_HPD_4: 296 - if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK) 297 - connected = true; 298 - break; 299 - case AMDGPU_HPD_5: 300 - if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK) 301 - connected = true; 302 - break; 303 - case AMDGPU_HPD_6: 304 - if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK) 305 - connected = true; 306 - break; 307 - default: 308 - break; 309 - } 281 + if (hpd >= adev->mode_info.num_hpd) 282 + return connected; 283 + 284 + if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & 285 + DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 286 + connected = true; 310 287 311 288 return connected; 312 289 } ··· 303 324 u32 tmp; 304 325 bool connected = dce_v8_0_hpd_sense(adev, hpd); 305 326 306 - switch (hpd) { 307 - case AMDGPU_HPD_1: 308 - tmp = RREG32(mmDC_HPD1_INT_CONTROL); 309 - if (connected) 310 - tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 311 - else 312 - tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 313 - WREG32(mmDC_HPD1_INT_CONTROL, tmp); 314 - break; 315 - case AMDGPU_HPD_2: 316 - tmp = RREG32(mmDC_HPD2_INT_CONTROL); 317 - if (connected) 318 - tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 319 - else 320 - tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 321 - WREG32(mmDC_HPD2_INT_CONTROL, tmp); 322 - break; 323 - case AMDGPU_HPD_3: 324 - tmp = RREG32(mmDC_HPD3_INT_CONTROL); 325 - if (connected) 326 - tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 327 - else 328 - tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 329 - WREG32(mmDC_HPD3_INT_CONTROL, tmp); 330 - break; 331 - case AMDGPU_HPD_4: 332 - tmp = RREG32(mmDC_HPD4_INT_CONTROL); 333 - if (connected) 334 - tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 335 - else 336 - tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 337 - WREG32(mmDC_HPD4_INT_CONTROL, tmp); 338 - break; 339 - case AMDGPU_HPD_5: 340 - tmp = RREG32(mmDC_HPD5_INT_CONTROL); 341 - if (connected) 342 - tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 343 - else 344 - tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 345 - WREG32(mmDC_HPD5_INT_CONTROL, tmp); 346 - break; 347 - case AMDGPU_HPD_6: 348 - tmp = RREG32(mmDC_HPD6_INT_CONTROL); 349 - if (connected) 350 - tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 351 - else 352 - tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 353 - WREG32(mmDC_HPD6_INT_CONTROL, tmp); 354 - break; 355 - default: 356 - break; 357 - } 327 + if (hpd >= adev->mode_info.num_hpd) 328 + return; 329 + 330 + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 331 + if (connected) 332 + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 333 + else 334 + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 335 + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 358 336 } 359 337 360 338 /** ··· 333 397 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 334 398 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 335 399 336 - switch (amdgpu_connector->hpd.hpd) { 337 - case AMDGPU_HPD_1: 338 - WREG32(mmDC_HPD1_CONTROL, tmp); 339 - break; 340 - case AMDGPU_HPD_2: 341 - WREG32(mmDC_HPD2_CONTROL, tmp); 342 - break; 343 - case AMDGPU_HPD_3: 344 - WREG32(mmDC_HPD3_CONTROL, tmp); 345 - break; 346 - case AMDGPU_HPD_4: 347 - WREG32(mmDC_HPD4_CONTROL, tmp); 348 - break; 349 - case AMDGPU_HPD_5: 350 - WREG32(mmDC_HPD5_CONTROL, tmp); 351 - break; 352 - case AMDGPU_HPD_6: 353 - WREG32(mmDC_HPD6_CONTROL, tmp); 354 - break; 355 - default: 356 - break; 357 - } 400 + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 401 + continue; 402 + 403 + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 358 404 359 405 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 360 406 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { ··· 345 427 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 346 428 * also avoid interrupt storms during dpms. 347 429 */ 348 - u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 349 - 350 - switch (amdgpu_connector->hpd.hpd) { 351 - case AMDGPU_HPD_1: 352 - dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; 353 - break; 354 - case AMDGPU_HPD_2: 355 - dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; 356 - break; 357 - case AMDGPU_HPD_3: 358 - dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; 359 - break; 360 - case AMDGPU_HPD_4: 361 - dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; 362 - break; 363 - case AMDGPU_HPD_5: 364 - dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; 365 - break; 366 - case AMDGPU_HPD_6: 367 - dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; 368 - break; 369 - default: 370 - continue; 371 - } 372 - 373 - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 374 - dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 375 - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 430 + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 431 + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 432 + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 376 433 continue; 377 434 } 378 435 ··· 372 479 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 373 480 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 374 481 375 - switch (amdgpu_connector->hpd.hpd) { 376 - case AMDGPU_HPD_1: 377 - WREG32(mmDC_HPD1_CONTROL, 0); 378 - break; 379 - case AMDGPU_HPD_2: 380 - WREG32(mmDC_HPD2_CONTROL, 0); 381 - break; 382 - case AMDGPU_HPD_3: 383 - WREG32(mmDC_HPD3_CONTROL, 0); 384 - break; 385 - case AMDGPU_HPD_4: 386 - WREG32(mmDC_HPD4_CONTROL, 0); 387 - break; 388 - case AMDGPU_HPD_5: 389 - WREG32(mmDC_HPD5_CONTROL, 0); 390 - break; 391 - case AMDGPU_HPD_6: 392 - WREG32(mmDC_HPD6_CONTROL, 0); 393 - break; 394 - default: 395 - break; 396 - } 482 + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 483 + continue; 484 + 485 + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 486 + 397 487 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 398 488 } 399 489 } ··· 3080 3204 unsigned type, 3081 3205 enum amdgpu_interrupt_state state) 3082 3206 { 3083 - u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 3207 + u32 dc_hpd_int_cntl; 3084 3208 3085 - switch (type) { 3086 - case AMDGPU_HPD_1: 3087 - dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; 3088 - break; 3089 - case AMDGPU_HPD_2: 3090 - dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; 3091 - break; 3092 - case AMDGPU_HPD_3: 3093 - dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; 3094 - break; 3095 - case AMDGPU_HPD_4: 3096 - dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; 3097 - break; 3098 - case AMDGPU_HPD_5: 3099 - dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; 3100 - break; 3101 - case AMDGPU_HPD_6: 3102 - dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; 3103 - break; 3104 - default: 3209 + if (type >= adev->mode_info.num_hpd) { 3105 3210 DRM_DEBUG("invalid hdp %d\n", type); 3106 3211 return 0; 3107 3212 } 3108 3213 3109 3214 switch (state) { 3110 3215 case AMDGPU_IRQ_STATE_DISABLE: 3111 - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3216 + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3112 3217 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3113 - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3218 + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3114 3219 break; 3115 3220 case AMDGPU_IRQ_STATE_ENABLE: 3116 - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3221 + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3117 3222 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3118 - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3223 + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3119 3224 break; 3120 3225 default: 3121 3226 break; ··· 3269 3412 struct amdgpu_irq_src *source, 3270 3413 struct amdgpu_iv_entry *entry) 3271 3414 { 3272 - uint32_t disp_int, mask, int_control, tmp; 3415 + uint32_t disp_int, mask, tmp; 3273 3416 unsigned hpd; 3274 3417 3275 3418 if (entry->src_data >= adev->mode_info.num_hpd) { ··· 3280 3423 hpd = entry->src_data; 3281 3424 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3282 3425 mask = interrupt_status_offsets[hpd].hpd; 3283 - int_control = hpd_int_control_offsets[hpd]; 3284 3426 3285 3427 if (disp_int & mask) { 3286 - tmp = RREG32(int_control); 3428 + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 3287 3429 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3288 - WREG32(int_control, tmp); 3430 + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 3289 3431 schedule_work(&adev->hotplug_work); 3290 3432 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3291 3433 }