Merge tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

+12

Documentation/devicetree/bindings/arm/rockchip.yaml

··· 97 97 - const: chipspark,rayeager-px2 98 98 - const: rockchip,rk3066a 99 99 100 + - description: Cool Pi Compute Module 5(CM5) EVB 101 + items: 102 + - enum: 103 + - coolpi,pi-cm5-evb 104 + - const: coolpi,pi-cm5 105 + - const: rockchip,rk3588 106 + 107 + - description: Cool Pi 4 Model B 108 + items: 109 + - const: coolpi,pi-4b 110 + - const: rockchip,rk3588s 111 + 100 112 - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards 101 113 items: 102 114 - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board

+2

Documentation/devicetree/bindings/soc/rockchip/grf.yaml

··· 28 28 - rockchip,rk3588-sys-grf 29 29 - rockchip,rk3588-pcie3-phy-grf 30 30 - rockchip,rk3588-pcie3-pipe-grf 31 + - rockchip,rk3588-vo-grf 32 + - rockchip,rk3588-vop-grf 31 33 - rockchip,rv1108-usbgrf 32 34 - const: syscon 33 35 - items:

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 294 294 description: CompuLab Ltd. 295 295 "^congatec,.*": 296 296 description: congatec GmbH 297 + "^coolpi,.*": 298 + description: cool-pi.com 297 299 "^coreriver,.*": 298 300 description: CORERIVER Semiconductor Co.,Ltd. 299 301 "^corpro,.*":

+2

arch/arm64/boot/dts/rockchip/Makefile

··· 101 101 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb 102 102 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb 103 103 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb 104 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb 104 105 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb 105 106 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb 106 107 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ··· 111 110 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb 112 111 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb 113 112 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb 113 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb 114 114 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb 115 115 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb 116 116 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb

+62 -58

arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts

··· 143 143 status = "okay"; 144 144 }; 145 145 146 + &gpio0 { 147 + gpio-line-names = 148 + /* GPIO0_A0 - A7 */ 149 + "", "", "", "", "", "", "", "", 150 + /* GPIO0_B0 - B7 */ 151 + "", "", "", "header1-pin3 [GPIO0_B3]", 152 + "header1-pin5 [GPIO0_B4]", "", "", 153 + "header1-pin11 [GPIO0_B7]", 154 + /* GPIO0_C0 - C7 */ 155 + "header1-pin13 [GPIO0_C0]", 156 + "header1-pin15 [GPIO0_C1]", "", "", "", 157 + "", "", "", 158 + /* GPIO0_D0 - D7 */ 159 + "", "", "", "", "", "", "", ""; 160 + }; 161 + 162 + &gpio1 { 163 + gpio-line-names = 164 + /* GPIO1_A0 - A7 */ 165 + "", "", "", "", "", "", "", "", 166 + /* GPIO1_B0 - B7 */ 167 + "", "", "", "", "", "", "", "", 168 + /* GPIO1_C0 - C7 */ 169 + "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", 170 + "header1-pin19 [GPIO1_C7]", 171 + /* GPIO1_D0 - D7 */ 172 + "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", 173 + "", "", "", "", "", ""; 174 + }; 175 + 176 + &gpio2 { 177 + gpio-line-names = 178 + /* GPIO2_A0 - A7 */ 179 + "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", 180 + "", "", 181 + "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", 182 + "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", 183 + /* GPIO2_B0 - B7 */ 184 + "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", 185 + "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", 186 + "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", 187 + "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", 188 + /* GPIO2_C0 - C7 */ 189 + "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", 190 + /* GPIO2_D0 - D7 */ 191 + "", "", "", "", "", "", "", ""; 192 + }; 193 + 194 + &gpio3 { 195 + gpio-line-names = 196 + /* GPIO3_A0 - A7 */ 197 + "", "", "", "", "", "", "", "", 198 + /* GPIO3_B0 - B7 */ 199 + "", "", "header2-pin42 [GPIO3_B2]", 200 + "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", 201 + "header2-pin39 [GPIO3_B5]", "", "", 202 + /* GPIO3_C0 - C7 */ 203 + "", "", "", "", "", "", "", "", 204 + /* GPIO3_D0 - D7 */ 205 + "", "", "", "", "", "", "", ""; 206 + }; 207 + 146 208 &i2c1 { 147 209 status = "okay"; 148 210 }; ··· 311 249 312 250 &wdt { 313 251 status = "okay"; 314 - }; 315 - 316 - &gpio0 { 317 - gpio-line-names = 318 - /* GPIO0_A0 - A7 */ 319 - "", "", "", "", "", "", "", "", 320 - /* GPIO0_B0 - B7 */ 321 - "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]", 322 - "", "", "header1-pin11 [GPIO0_B7]", 323 - /* GPIO0_C0 - C7 */ 324 - "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "", 325 - "", "", "", 326 - /* GPIO0_D0 - D8 */ 327 - "", "", "", "", "", "", "", ""; 328 - }; 329 - 330 - &gpio1 { 331 - gpio-line-names = 332 - /* GPIO1_A0 - A7 */ 333 - "", "", "", "", "", "", "", "", 334 - /* GPIO1_B0 - B7 */ 335 - "", "", "", "", "", "", "", "", 336 - /* GPIO1_C0 - C7 */ 337 - "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", 338 - "header1-pin19 [GPIO1_C7]", 339 - /* GPIO1_D0 - D8 */ 340 - "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "", 341 - "", "", ""; 342 - }; 343 - 344 - &gpio2 { 345 - gpio-line-names = 346 - /* GPIO2_A0 - A7 */ 347 - "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "", 348 - "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", 349 - "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", 350 - /* GPIO2_B0 - B7 */ 351 - "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", 352 - "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", 353 - "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", 354 - "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", 355 - /* GPIO2_C0 - C7 */ 356 - "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", 357 - /* GPIO2_D0 - D8 */ 358 - "", "", "", "", "", "", "", ""; 359 - }; 360 - 361 - &gpio3 { 362 - gpio-line-names = 363 - /* GPIO3_A0 - A7 */ 364 - "", "", "", "", "", "", "", "", 365 - /* GPIO3_B0 - B7 */ 366 - "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]", 367 - "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "", 368 - /* GPIO3_C0 - C7 */ 369 - "", "", "", "", "", "", "", "", 370 - /* GPIO3_D0 - D8 */ 371 - "", "", "", "", "", "", "", ""; 372 252 };

+3 -1

arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

··· 26 26 compatible = "ethernet-phy-ieee802.3-c22"; 27 27 reg = <0>; 28 28 29 + motorcomm,auto-sleep-disabled; 29 30 motorcomm,clk-out-frequency-hz = <125000000>; 30 31 motorcomm,keep-pll-enabled; 31 - motorcomm,auto-sleep-disabled; 32 + motorcomm,rx-clk-drv-microamp = <5020>; 33 + motorcomm,rx-data-drv-microamp = <5020>; 32 34 33 35 pinctrl-0 = <&eth_phy_reset_pin>; 34 36 pinctrl-names = "default";

+53

arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts

··· 182 182 status = "okay"; 183 183 }; 184 184 185 + &gpio0 { 186 + gpio-line-names = 187 + /* GPIO0_A0 - A7 */ 188 + "", "", "", "", "", "", "", "", 189 + /* GPIO0_B0 - B7 */ 190 + "", "", "", "", "", "", "", "", 191 + /* GPIO0_C0 - C7 */ 192 + "", "", "", "", "", "", "", "", 193 + /* GPIO0_D0 - D7 */ 194 + "", "", "", "pin-15 [GPIO0_D3]", "", "", "", ""; 195 + }; 196 + 197 + &gpio1 { 198 + gpio-line-names = 199 + /* GPIO1_A0 - A7 */ 200 + "", "", "", "", "", "", "", "", 201 + /* GPIO1_B0 - B7 */ 202 + "", "", "", "", "", "", "", "", 203 + /* GPIO1_C0 - C7 */ 204 + "", "", "", "", "", "", "", "", 205 + /* GPIO1_D0 - D7 */ 206 + "", "", "", "", "pin-07 [GPIO1_D4]", "", "", ""; 207 + }; 208 + 209 + &gpio2 { 210 + gpio-line-names = 211 + /* GPIO2_A0 - A7 */ 212 + "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]", 213 + "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]", 214 + "pin-33 [GPIO2_A6]", "", 215 + /* GPIO2_B0 - B7 */ 216 + "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]", 217 + /* GPIO2_C0 - C7 */ 218 + "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]", 219 + "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]", 220 + "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]", 221 + /* GPIO2_D0 - D7 */ 222 + "", "", "", "", "", "", "", ""; 223 + }; 224 + 225 + &gpio3 { 226 + gpio-line-names = 227 + /* GPIO3_A0 - A7 */ 228 + "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]", 229 + "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "", 230 + /* GPIO3_B0 - B7 */ 231 + "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "", 232 + /* GPIO3_C0 - C7 */ 233 + "", "", "", "", "", "", "", "", 234 + /* GPIO3_D0 - D7 */ 235 + "", "", "", "", "", "", "", ""; 236 + }; 237 + 185 238 &i2c1 { 186 239 status = "okay"; 187 240

+36 -6

arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts

··· 5 5 6 6 /dts-v1/; 7 7 #include "rk3399-puma.dtsi" 8 + #include <dt-bindings/input/input.h> 8 9 9 10 / { 10 11 model = "Theobroma Systems RK3399-Q7 SoM"; ··· 17 16 18 17 chosen { 19 18 stdout-path = "serial0:115200n8"; 19 + }; 20 + 21 + gpio-keys { 22 + compatible = "gpio-keys"; 23 + pinctrl-0 = <&haikou_keys_pin>; 24 + pinctrl-names = "default"; 25 + 26 + button-batlow-n { 27 + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; 28 + label = "BATLOW#"; 29 + linux,code = <KEY_BATTERY>; 30 + }; 31 + 32 + button-slp-btn-n { 33 + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; 34 + label = "SLP_BTN#"; 35 + linux,code = <KEY_SLEEP>; 36 + }; 37 + 38 + button-wake-n { 39 + gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; 40 + label = "WAKE#"; 41 + linux,code = <KEY_WAKEUP>; 42 + wakeup-source; 43 + }; 44 + 45 + switch-lid-btn-n { 46 + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 47 + label = "LID_BTN#"; 48 + linux,code = <SW_LID>; 49 + linux,input-type = <EV_SW>; 50 + }; 20 51 }; 21 52 22 53 leds { ··· 198 165 }; 199 166 200 167 &pinctrl { 201 - pinctrl-names = "default"; 202 - pinctrl-0 = <&haikou_pin_hog>; 203 - 204 - hog { 205 - haikou_pin_hog: haikou-pin-hog { 168 + buttons { 169 + haikou_keys_pin: haikou-keys-pin { 206 170 rockchip,pins = 207 171 /* LID_BTN */ 208 172 <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, ··· 207 177 <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, 208 178 /* SLP_BTN# */ 209 179 <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, 210 - /* BIOS_DISABLE# */ 180 + /* WAKE# */ 211 181 <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 212 182 }; 213 183 };

+14

arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi

··· 120 120 drive-impedance-ohm = <33>; 121 121 }; 122 122 123 + &gpio0 { 124 + /* 125 + * The BIOS_DISABLE hog is a feedback pin for the actual status of the 126 + * signal. This usually represents the state of a switch on the baseboard. 127 + * The pin has a 10k pull-up resistor connected, so no pull-up setting is needed. 128 + */ 129 + bios-disable-hog { 130 + gpios = <RK_PB0 GPIO_ACTIVE_HIGH>; 131 + gpio-hog; 132 + input; 133 + line-name = "bios_disable"; 134 + }; 135 + }; 136 + 123 137 &gmac { 124 138 assigned-clocks = <&cru SCLK_RMII_SRC>; 125 139 assigned-clock-parents = <&clkin_gmac>;

+1 -1

arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts

··· 455 455 &pinctrl { 456 456 leds { 457 457 sys_led_pin: sys-status-led-pin { 458 - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 458 + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 459 459 }; 460 460 }; 461 461

+214

arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 + * 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/leds/common.h> 10 + #include "rk3588-coolpi-cm5.dtsi" 11 + 12 + / { 13 + model = "RK3588 CoolPi CM5 EVB"; 14 + compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588"; 15 + 16 + backlight: backlight { 17 + compatible = "pwm-backlight"; 18 + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; 19 + pinctrl-names = "default"; 20 + pinctrl-0 = <&bl_en>; 21 + power-supply = <&vcc12v_dcin>; 22 + pwms = <&pwm2 0 25000 0>; 23 + }; 24 + 25 + leds: leds { 26 + compatible = "gpio-leds"; 27 + 28 + green_led: led-0 { 29 + color = <LED_COLOR_ID_GREEN>; 30 + function = LED_FUNCTION_STATUS; 31 + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; 32 + linux,default-trigger = "heartbeat"; 33 + }; 34 + }; 35 + 36 + vcc12v_dcin: vcc12v-dcin-regulator { 37 + compatible = "regulator-fixed"; 38 + regulator-name = "vcc12v_dcin"; 39 + regulator-always-on; 40 + regulator-boot-on; 41 + regulator-min-microvolt = <12000000>; 42 + regulator-max-microvolt = <12000000>; 43 + }; 44 + 45 + vcc5v0_sys: vcc5v0-sys-regulator { 46 + compatible = "regulator-fixed"; 47 + regulator-name = "vcc5v0_sys"; 48 + regulator-always-on; 49 + regulator-boot-on; 50 + regulator-min-microvolt = <5000000>; 51 + regulator-max-microvolt = <5000000>; 52 + vin-supply = <&vcc12v_dcin>; 53 + }; 54 + 55 + vcc3v3_sys: vcc3v3-sys-regulator { 56 + compatible = "regulator-fixed"; 57 + regulator-name = "vcc3v3_sys"; 58 + regulator-always-on; 59 + regulator-boot-on; 60 + regulator-min-microvolt = <3300000>; 61 + regulator-max-microvolt = <3300000>; 62 + vin-supply = <&vcc12v_dcin>; 63 + }; 64 + 65 + vcc3v3_lcd: vcc3v3-lcd-regulator { 66 + compatible = "regulator-fixed"; 67 + regulator-name = "vcc3v3_lcd"; 68 + enable-active-high; 69 + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 70 + pinctrl-names = "default"; 71 + pinctrl-0 = <&lcdpwr_en>; 72 + vin-supply = <&vcc3v3_sys>; 73 + }; 74 + 75 + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { 76 + compatible = "regulator-fixed"; 77 + regulator-name = "vcc5v0_host"; 78 + regulator-boot-on; 79 + regulator-always-on; 80 + enable-active-high; 81 + regulator-min-microvolt = <5000000>; 82 + regulator-max-microvolt = <5000000>; 83 + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; 84 + pinctrl-names = "default"; 85 + pinctrl-0 = <&usb_host_pwren>; 86 + vin-supply = <&vcc5v0_sys>; 87 + }; 88 + 89 + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { 90 + compatible = "regulator-fixed"; 91 + regulator-name = "vcc5v0_otg"; 92 + regulator-boot-on; 93 + regulator-always-on; 94 + enable-active-high; 95 + regulator-min-microvolt = <5000000>; 96 + regulator-max-microvolt = <5000000>; 97 + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 98 + pinctrl-names = "default"; 99 + pinctrl-0 = <&usb_otg_pwren>; 100 + vin-supply = <&vcc5v0_sys>; 101 + }; 102 + }; 103 + 104 + /* M.2 E-Key */ 105 + &pcie2x1l1 { 106 + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 107 + vpcie3v3-supply = <&vcc3v3_sys>; 108 + pinctrl-names = "default"; 109 + pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; 110 + status = "okay"; 111 + }; 112 + 113 + &pcie30phy { 114 + status = "okay"; 115 + }; 116 + 117 + &pcie3x2 { 118 + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; 119 + vpcie3v3-supply = <&vcc3v3_sys>; 120 + status = "okay"; 121 + }; 122 + 123 + /* M.2 M-Key ssd */ 124 + &pcie3x4 { 125 + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 126 + vpcie3v3-supply = <&vcc3v3_sys>; 127 + status = "okay"; 128 + }; 129 + 130 + &pinctrl { 131 + lcd { 132 + lcdpwr_en: lcdpwr-en { 133 + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; 134 + }; 135 + 136 + bl_en: bl-en { 137 + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 138 + }; 139 + }; 140 + 141 + usb { 142 + usb_host_pwren: usb-host-pwren { 143 + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 144 + }; 145 + 146 + usb_otg_pwren: usb-otg-pwren { 147 + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 148 + }; 149 + }; 150 + 151 + wifi { 152 + bt_pwron: bt-pwron { 153 + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; 154 + }; 155 + 156 + pcie_clkreq: pcie-clkreq { 157 + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 158 + }; 159 + 160 + pcie_rst: pcie-rst { 161 + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 162 + }; 163 + 164 + wifi_pwron: wifi-pwron { 165 + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 166 + }; 167 + 168 + pcie_wake: pcie-wake { 169 + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 170 + }; 171 + }; 172 + }; 173 + 174 + &pwm2 { 175 + status = "okay"; 176 + }; 177 + 178 + &sata1 { 179 + status = "okay"; 180 + }; 181 + 182 + &u2phy2 { 183 + status = "okay"; 184 + }; 185 + 186 + &u2phy3 { 187 + status = "okay"; 188 + }; 189 + 190 + &u2phy2_host { 191 + phy-supply = <&vcc5v0_usb30_host>; 192 + status = "okay"; 193 + }; 194 + 195 + &u2phy3_host { 196 + phy-supply = <&vcc5v0_usb30_host>; 197 + status = "okay"; 198 + }; 199 + 200 + &usb_host0_ehci { 201 + status = "okay"; 202 + }; 203 + 204 + &usb_host0_ohci { 205 + status = "okay"; 206 + }; 207 + 208 + &usb_host1_ehci { 209 + status = "okay"; 210 + }; 211 + 212 + &usb_host1_ohci { 213 + status = "okay"; 214 + };

+650

arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 + * 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/pwm/pwm.h> 11 + #include <dt-bindings/pinctrl/rockchip.h> 12 + #include "rk3588.dtsi" 13 + 14 + / { 15 + compatible = "coolpi,pi-cm5", "rockchip,rk3588"; 16 + 17 + aliases { 18 + mmc0 = &sdhci; 19 + mmc1 = &sdio; 20 + mmc2 = &sdmmc; 21 + serial2 = &uart2; 22 + }; 23 + 24 + analog-sound { 25 + compatible = "audio-graph-card"; 26 + dais = <&i2s0_8ch_p0>; 27 + label = "rk3588-es8316"; 28 + routing = "MIC2", "Mic Jack", 29 + "Headphones", "HPOL", 30 + "Headphones", "HPOR"; 31 + widgets = "Microphone", "Mic Jack", 32 + "Headphone", "Headphones"; 33 + }; 34 + 35 + chosen { 36 + stdout-path = "serial2:1500000n8"; 37 + }; 38 + 39 + avdd0v85_pcie20: avdd0v85-pcie20-regulator { 40 + compatible = "regulator-fixed"; 41 + regulator-name = "avdd0v85_pcie20"; 42 + regulator-boot-on; 43 + regulator-always-on; 44 + regulator-min-microvolt = <850000>; 45 + regulator-max-microvolt = <850000>; 46 + vin-supply = <&vdd_0v85_s0>; 47 + }; 48 + 49 + avdd1v8_pcie20: avdd1v8-pcie20-regulator { 50 + compatible = "regulator-fixed"; 51 + regulator-name = "avdd1v8_pcie20"; 52 + regulator-boot-on; 53 + regulator-always-on; 54 + regulator-min-microvolt = <1800000>; 55 + regulator-max-microvolt = <1800000>; 56 + vin-supply = <&avcc_1v8_s0>; 57 + }; 58 + 59 + avdd0v75_pcie30: avdd0v75-pcie30-regulator { 60 + compatible = "regulator-fixed"; 61 + regulator-name = "avdd0v75_pcie30"; 62 + regulator-boot-on; 63 + regulator-always-on; 64 + regulator-min-microvolt = <750000>; 65 + regulator-max-microvolt = <750000>; 66 + vin-supply = <&avdd_0v75_s0>; 67 + }; 68 + 69 + pcie30_avdd1v8: avdd1v8-pcie30-regulator { 70 + compatible = "regulator-fixed"; 71 + regulator-name = "pcie30_avdd1v8"; 72 + regulator-boot-on; 73 + regulator-always-on; 74 + regulator-min-microvolt = <1800000>; 75 + regulator-max-microvolt = <1800000>; 76 + vin-supply = <&avcc_1v8_s0>; 77 + }; 78 + }; 79 + 80 + &combphy0_ps { 81 + status = "okay"; 82 + }; 83 + 84 + &combphy1_ps { 85 + status = "okay"; 86 + }; 87 + 88 + &combphy2_psu { 89 + status = "okay"; 90 + }; 91 + 92 + &cpu_b0 { 93 + cpu-supply = <&vdd_cpu_big0_s0>; 94 + }; 95 + 96 + &cpu_b1 { 97 + cpu-supply = <&vdd_cpu_big0_s0>; 98 + }; 99 + 100 + &cpu_b2 { 101 + cpu-supply = <&vdd_cpu_big1_s0>; 102 + }; 103 + 104 + &cpu_b3 { 105 + cpu-supply = <&vdd_cpu_big1_s0>; 106 + }; 107 + 108 + &cpu_l0 { 109 + cpu-supply = <&vdd_cpu_lit_s0>; 110 + }; 111 + 112 + &cpu_l1 { 113 + cpu-supply = <&vdd_cpu_lit_s0>; 114 + }; 115 + 116 + &cpu_l2 { 117 + cpu-supply = <&vdd_cpu_lit_s0>; 118 + }; 119 + 120 + &cpu_l3 { 121 + cpu-supply = <&vdd_cpu_lit_s0>; 122 + }; 123 + 124 + &gmac0 { 125 + clock_in_out = "output"; 126 + phy-handle = <&rgmii_phy>; 127 + phy-mode = "rgmii-rxid"; 128 + pinctrl-0 = <&gmac0_miim 129 + &gmac0_tx_bus2 130 + &gmac0_rx_bus2 131 + &gmac0_rgmii_clk 132 + &gmac0_rgmii_bus>; 133 + pinctrl-names = "default"; 134 + rx_delay = <0x00>; 135 + tx_delay = <0x43>; 136 + status = "okay"; 137 + }; 138 + 139 + &i2c0 { 140 + pinctrl-0 = <&i2c0m2_xfer>; 141 + status = "okay"; 142 + 143 + vdd_cpu_big0_s0: regulator@42 { 144 + compatible = "rockchip,rk8602"; 145 + reg = <0x42>; 146 + fcs,suspend-voltage-selector = <1>; 147 + regulator-name = "vdd_cpu_big0_s0"; 148 + regulator-always-on; 149 + regulator-boot-on; 150 + regulator-min-microvolt = <550000>; 151 + regulator-max-microvolt = <1050000>; 152 + regulator-ramp-delay = <2300>; 153 + vin-supply = <&vcc5v0_sys>; 154 + 155 + regulator-state-mem { 156 + regulator-off-in-suspend; 157 + }; 158 + }; 159 + 160 + vdd_cpu_big1_s0: regulator@43 { 161 + compatible = "rockchip,rk8603", "rockchip,rk8602"; 162 + reg = <0x43>; 163 + fcs,suspend-voltage-selector = <1>; 164 + regulator-name = "vdd_cpu_big1_s0"; 165 + regulator-always-on; 166 + regulator-boot-on; 167 + regulator-min-microvolt = <550000>; 168 + regulator-max-microvolt = <1050000>; 169 + regulator-ramp-delay = <2300>; 170 + vin-supply = <&vcc5v0_sys>; 171 + 172 + regulator-state-mem { 173 + regulator-off-in-suspend; 174 + }; 175 + }; 176 + }; 177 + 178 + &i2c2 { 179 + status = "okay"; 180 + 181 + vdd_npu_s0: regulator@42 { 182 + compatible = "rockchip,rk8602"; 183 + reg = <0x42>; 184 + fcs,suspend-voltage-selector = <1>; 185 + regulator-name = "vdd_npu_s0"; 186 + regulator-always-on; 187 + regulator-boot-on; 188 + regulator-min-microvolt = <550000>; 189 + regulator-max-microvolt = <950000>; 190 + regulator-ramp-delay = <2300>; 191 + vin-supply = <&vcc5v0_sys>; 192 + 193 + regulator-state-mem { 194 + regulator-off-in-suspend; 195 + }; 196 + }; 197 + }; 198 + 199 + &i2c6 { 200 + status = "okay"; 201 + 202 + hym8563: rtc@51 { 203 + compatible = "haoyu,hym8563"; 204 + reg = <0x51>; 205 + interrupt-parent = <&gpio0>; 206 + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 207 + #clock-cells = <0>; 208 + clock-output-names = "hym8563"; 209 + pinctrl-names = "default"; 210 + pinctrl-0 = <&hym8563_int>; 211 + wakeup-source; 212 + }; 213 + }; 214 + 215 + &i2c7 { 216 + pinctrl-0 = <&i2c7m0_xfer>; 217 + status = "okay"; 218 + 219 + es8316: audio-codec@11 { 220 + compatible = "everest,es8316"; 221 + reg = <0x11>; 222 + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; 223 + assigned-clock-rates = <12288000>; 224 + clocks = <&cru I2S0_8CH_MCLKOUT>; 225 + clock-names = "mclk"; 226 + #sound-dai-cells = <0>; 227 + 228 + port { 229 + es8316_p0_0: endpoint { 230 + remote-endpoint = <&i2s0_8ch_p0_0>; 231 + }; 232 + }; 233 + }; 234 + }; 235 + 236 + &i2s0_8ch { 237 + pinctrl-0 = <&i2s0_lrck 238 + &i2s0_mclk 239 + &i2s0_sclk 240 + &i2s0_sdi0 241 + &i2s0_sdo0>; 242 + status = "okay"; 243 + 244 + i2s0_8ch_p0: port { 245 + i2s0_8ch_p0_0: endpoint { 246 + dai-format = "i2s"; 247 + mclk-fs = <256>; 248 + remote-endpoint = <&es8316_p0_0>; 249 + }; 250 + }; 251 + }; 252 + 253 + &mdio0 { 254 + rgmii_phy: ethernet-phy@1 { 255 + /* YT8531C/H */ 256 + compatible = "ethernet-phy-ieee802.3-c22"; 257 + reg = <0x1>; 258 + pinctrl-names = "default"; 259 + pinctrl-0 = <&yt8531_rst>; 260 + reset-assert-us = <20000>; 261 + reset-deassert-us = <100000>; 262 + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 263 + }; 264 + }; 265 + 266 + /* ethernet */ 267 + &pcie2x1l2 { 268 + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; 269 + vpcie3v3-supply = <&vcc3v3_sys>; 270 + pinctrl-names = "default"; 271 + pinctrl-0 = <&yt6801_isolate>; 272 + status = "okay"; 273 + }; 274 + 275 + &pinctrl { 276 + hym8563 { 277 + hym8563_int: hym8563-int { 278 + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 279 + }; 280 + }; 281 + 282 + yt6801 { 283 + yt6801_isolate: yt6801-isolate { 284 + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 285 + }; 286 + }; 287 + 288 + yt8531 { 289 + yt8531_rst: yt8531-rst { 290 + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 291 + }; 292 + }; 293 + }; 294 + 295 + &saradc { 296 + vref-supply = <&vcc_1v8_s0>; 297 + status = "okay"; 298 + }; 299 + 300 + &sdhci { 301 + bus-width = <8>; 302 + max-frequency = <200000000>; 303 + mmc-hs400-1_8v; 304 + mmc-hs400-enhanced-strobe; 305 + no-sdio; 306 + no-sd; 307 + non-removable; 308 + status = "okay"; 309 + }; 310 + 311 + &sdmmc { 312 + bus-width = <4>; 313 + cap-mmc-highspeed; 314 + cap-sd-highspeed; 315 + disable-wp; 316 + max-frequency = <150000000>; 317 + no-sdio; 318 + no-mmc; 319 + sd-uhs-sdr104; 320 + vqmmc-supply = <&vccio_sd_s0>; 321 + status = "okay"; 322 + }; 323 + 324 + &spi2 { 325 + assigned-clocks = <&cru CLK_SPI2>; 326 + assigned-clock-rates = <200000000>; 327 + num-cs = <1>; 328 + pinctrl-names = "default"; 329 + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 330 + status = "okay"; 331 + 332 + pmic@0 { 333 + compatible = "rockchip,rk806"; 334 + reg = <0x0>; 335 + interrupt-parent = <&gpio0>; 336 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 337 + gpio-controller; 338 + #gpio-cells = <2>; 339 + pinctrl-names = "default"; 340 + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 341 + <&rk806_dvs2_null>, <&rk806_dvs3_null>; 342 + spi-max-frequency = <1000000>; 343 + vcc1-supply = <&vcc5v0_sys>; 344 + vcc2-supply = <&vcc5v0_sys>; 345 + vcc3-supply = <&vcc5v0_sys>; 346 + vcc4-supply = <&vcc5v0_sys>; 347 + vcc5-supply = <&vcc5v0_sys>; 348 + vcc6-supply = <&vcc5v0_sys>; 349 + vcc7-supply = <&vcc5v0_sys>; 350 + vcc8-supply = <&vcc5v0_sys>; 351 + vcc9-supply = <&vcc5v0_sys>; 352 + vcc10-supply = <&vcc5v0_sys>; 353 + vcc11-supply = <&vcc_2v0_pldo_s3>; 354 + vcc12-supply = <&vcc5v0_sys>; 355 + vcc13-supply = <&vcc_2v0_pldo_s3>; 356 + vcc14-supply = <&vcc_2v0_pldo_s3>; 357 + vcca-supply = <&vcc5v0_sys>; 358 + 359 + rk806_dvs1_null: dvs1-null-pins { 360 + pins = "gpio_pwrctrl2"; 361 + function = "pin_fun0"; 362 + }; 363 + 364 + rk806_dvs2_null: dvs2-null-pins { 365 + pins = "gpio_pwrctrl2"; 366 + function = "pin_fun0"; 367 + }; 368 + 369 + rk806_dvs3_null: dvs3-null-pins { 370 + pins = "gpio_pwrctrl3"; 371 + function = "pin_fun0"; 372 + }; 373 + 374 + regulators { 375 + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { 376 + regulator-boot-on; 377 + regulator-min-microvolt = <550000>; 378 + regulator-max-microvolt = <950000>; 379 + regulator-ramp-delay = <12500>; 380 + regulator-name = "vdd_gpu_s0"; 381 + regulator-enable-ramp-delay = <400>; 382 + 383 + regulator-state-mem { 384 + regulator-off-in-suspend; 385 + }; 386 + }; 387 + 388 + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { 389 + regulator-always-on; 390 + regulator-boot-on; 391 + regulator-min-microvolt = <550000>; 392 + regulator-max-microvolt = <950000>; 393 + regulator-ramp-delay = <12500>; 394 + regulator-name = "vdd_cpu_lit_s0"; 395 + 396 + regulator-state-mem { 397 + regulator-off-in-suspend; 398 + }; 399 + }; 400 + 401 + vdd_log_s0: dcdc-reg3 { 402 + regulator-always-on; 403 + regulator-boot-on; 404 + regulator-min-microvolt = <675000>; 405 + regulator-max-microvolt = <750000>; 406 + regulator-ramp-delay = <12500>; 407 + regulator-name = "vdd_log_s0"; 408 + 409 + regulator-state-mem { 410 + regulator-off-in-suspend; 411 + regulator-suspend-microvolt = <750000>; 412 + }; 413 + }; 414 + 415 + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { 416 + regulator-always-on; 417 + regulator-boot-on; 418 + regulator-min-microvolt = <550000>; 419 + regulator-max-microvolt = <950000>; 420 + regulator-ramp-delay = <12500>; 421 + regulator-name = "vdd_vdenc_s0"; 422 + 423 + regulator-state-mem { 424 + regulator-off-in-suspend; 425 + }; 426 + }; 427 + 428 + vdd_ddr_s0: dcdc-reg5 { 429 + regulator-always-on; 430 + regulator-boot-on; 431 + regulator-min-microvolt = <675000>; 432 + regulator-max-microvolt = <900000>; 433 + regulator-ramp-delay = <12500>; 434 + regulator-name = "vdd_ddr_s0"; 435 + 436 + regulator-state-mem { 437 + regulator-off-in-suspend; 438 + regulator-suspend-microvolt = <850000>; 439 + }; 440 + }; 441 + 442 + vdd2_ddr_s3: dcdc-reg6 { 443 + regulator-always-on; 444 + regulator-boot-on; 445 + regulator-name = "vdd2_ddr_s3"; 446 + 447 + regulator-state-mem { 448 + regulator-on-in-suspend; 449 + }; 450 + }; 451 + 452 + vcc_2v0_pldo_s3: dcdc-reg7 { 453 + regulator-always-on; 454 + regulator-boot-on; 455 + regulator-min-microvolt = <2000000>; 456 + regulator-max-microvolt = <2000000>; 457 + regulator-ramp-delay = <12500>; 458 + regulator-name = "vdd_2v0_pldo_s3"; 459 + 460 + regulator-state-mem { 461 + regulator-on-in-suspend; 462 + regulator-suspend-microvolt = <2000000>; 463 + }; 464 + }; 465 + 466 + vcc_3v3_s3: dcdc-reg8 { 467 + regulator-always-on; 468 + regulator-boot-on; 469 + regulator-min-microvolt = <3300000>; 470 + regulator-max-microvolt = <3300000>; 471 + regulator-name = "vcc_3v3_s3"; 472 + 473 + regulator-state-mem { 474 + regulator-on-in-suspend; 475 + regulator-suspend-microvolt = <3300000>; 476 + }; 477 + }; 478 + 479 + vddq_ddr_s0: dcdc-reg9 { 480 + regulator-always-on; 481 + regulator-boot-on; 482 + regulator-name = "vddq_ddr_s0"; 483 + 484 + regulator-state-mem { 485 + regulator-off-in-suspend; 486 + }; 487 + }; 488 + 489 + vcc_1v8_s3: dcdc-reg10 { 490 + regulator-always-on; 491 + regulator-boot-on; 492 + regulator-min-microvolt = <1800000>; 493 + regulator-max-microvolt = <1800000>; 494 + regulator-name = "vcc_1v8_s3"; 495 + 496 + regulator-state-mem { 497 + regulator-on-in-suspend; 498 + regulator-suspend-microvolt = <1800000>; 499 + }; 500 + }; 501 + 502 + avcc_1v8_s0: pldo-reg1 { 503 + regulator-always-on; 504 + regulator-boot-on; 505 + regulator-min-microvolt = <1800000>; 506 + regulator-max-microvolt = <1800000>; 507 + regulator-name = "avcc_1v8_s0"; 508 + 509 + regulator-state-mem { 510 + regulator-off-in-suspend; 511 + }; 512 + }; 513 + 514 + vcc_1v8_s0: pldo-reg2 { 515 + regulator-always-on; 516 + regulator-boot-on; 517 + regulator-min-microvolt = <1800000>; 518 + regulator-max-microvolt = <1800000>; 519 + regulator-name = "vcc_1v8_s0"; 520 + 521 + regulator-state-mem { 522 + regulator-off-in-suspend; 523 + regulator-suspend-microvolt = <1800000>; 524 + }; 525 + }; 526 + 527 + avdd_1v2_s0: pldo-reg3 { 528 + regulator-always-on; 529 + regulator-boot-on; 530 + regulator-min-microvolt = <1200000>; 531 + regulator-max-microvolt = <1200000>; 532 + regulator-name = "avdd_1v2_s0"; 533 + 534 + regulator-state-mem { 535 + regulator-off-in-suspend; 536 + }; 537 + }; 538 + 539 + vcc_3v3_s0: pldo-reg4 { 540 + regulator-always-on; 541 + regulator-boot-on; 542 + regulator-min-microvolt = <3300000>; 543 + regulator-max-microvolt = <3300000>; 544 + regulator-ramp-delay = <12500>; 545 + regulator-name = "vcc_3v3_s0"; 546 + 547 + regulator-state-mem { 548 + regulator-off-in-suspend; 549 + }; 550 + }; 551 + 552 + vccio_sd_s0: pldo-reg5 { 553 + regulator-always-on; 554 + regulator-boot-on; 555 + regulator-min-microvolt = <1800000>; 556 + regulator-max-microvolt = <3300000>; 557 + regulator-ramp-delay = <12500>; 558 + regulator-name = "vccio_sd_s0"; 559 + 560 + regulator-state-mem { 561 + regulator-off-in-suspend; 562 + }; 563 + }; 564 + 565 + pldo6_s3: pldo-reg6 { 566 + regulator-always-on; 567 + regulator-boot-on; 568 + regulator-min-microvolt = <1800000>; 569 + regulator-max-microvolt = <1800000>; 570 + regulator-name = "pldo6_s3"; 571 + 572 + regulator-state-mem { 573 + regulator-on-in-suspend; 574 + regulator-suspend-microvolt = <1800000>; 575 + }; 576 + }; 577 + 578 + vdd_0v75_s3: nldo-reg1 { 579 + regulator-always-on; 580 + regulator-boot-on; 581 + regulator-min-microvolt = <750000>; 582 + regulator-max-microvolt = <750000>; 583 + regulator-name = "vdd_0v75_s3"; 584 + 585 + regulator-state-mem { 586 + regulator-on-in-suspend; 587 + regulator-suspend-microvolt = <750000>; 588 + }; 589 + }; 590 + 591 + vdd_ddr_pll_s0: nldo-reg2 { 592 + regulator-always-on; 593 + regulator-boot-on; 594 + regulator-min-microvolt = <850000>; 595 + regulator-max-microvolt = <850000>; 596 + regulator-name = "vdd_ddr_pll_s0"; 597 + 598 + regulator-state-mem { 599 + regulator-off-in-suspend; 600 + regulator-suspend-microvolt = <850000>; 601 + }; 602 + }; 603 + 604 + avdd_0v75_s0: nldo-reg3 { 605 + regulator-always-on; 606 + regulator-boot-on; 607 + regulator-min-microvolt = <750000>; 608 + regulator-max-microvolt = <750000>; 609 + regulator-name = "avdd_0v75_s0"; 610 + 611 + regulator-state-mem { 612 + regulator-off-in-suspend; 613 + }; 614 + }; 615 + 616 + vdd_0v85_s0: nldo-reg4 { 617 + regulator-always-on; 618 + regulator-boot-on; 619 + regulator-min-microvolt = <850000>; 620 + regulator-max-microvolt = <850000>; 621 + regulator-name = "vdd_0v85_s0"; 622 + 623 + regulator-state-mem { 624 + regulator-off-in-suspend; 625 + }; 626 + }; 627 + 628 + vdd_0v75_s0: nldo-reg5 { 629 + regulator-always-on; 630 + regulator-boot-on; 631 + regulator-min-microvolt = <750000>; 632 + regulator-max-microvolt = <750000>; 633 + regulator-name = "vdd_0v75_s0"; 634 + 635 + regulator-state-mem { 636 + regulator-off-in-suspend; 637 + }; 638 + }; 639 + }; 640 + }; 641 + }; 642 + 643 + &tsadc { 644 + status = "okay"; 645 + }; 646 + 647 + &uart2 { 648 + pinctrl-0 = <&uart2m0_xfer>; 649 + status = "okay"; 650 + };

+5 -4

arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts

··· 536 536 }; 537 537 538 538 &sdmmc { 539 - max-frequency = <200000000>; 540 - no-sdio; 541 - no-mmc; 542 539 bus-width = <4>; 543 540 cap-mmc-highspeed; 544 541 cap-sd-highspeed; 545 542 disable-wp; 543 + no-mmc; 544 + no-sdio; 546 545 sd-uhs-sdr104; 547 546 vmmc-supply = <&vcc_3v3_s3>; 548 547 vqmmc-supply = <&vccio_sd_s0>; ··· 568 569 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 569 570 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 570 571 572 + system-power-controller; 573 + 571 574 vcc1-supply = <&vcc4v0_sys>; 572 575 vcc2-supply = <&vcc4v0_sys>; 573 576 vcc3-supply = <&vcc4v0_sys>; ··· 590 589 #gpio-cells = <2>; 591 590 592 591 rk806_dvs1_null: dvs1-null-pins { 593 - pins = "gpio_pwrctrl2"; 592 + pins = "gpio_pwrctrl1"; 594 593 function = "pin_fun0"; 595 594 }; 596 595

+3 -1

arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts

··· 426 426 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 427 427 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 428 428 429 + system-power-controller; 430 + 429 431 vcc1-supply = <&vcc5v0_sys>; 430 432 vcc2-supply = <&vcc5v0_sys>; 431 433 vcc3-supply = <&vcc5v0_sys>; ··· 448 446 #gpio-cells = <2>; 449 447 450 448 rk806_dvs1_null: dvs1-null-pins { 451 - pins = "gpio_pwrctrl2"; 449 + pins = "gpio_pwrctrl1"; 452 450 function = "pin_fun0"; 453 451 }; 454 452

+812

arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 + * 5 + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction 6 + * 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include <dt-bindings/gpio/gpio.h> 12 + #include <dt-bindings/leds/common.h> 13 + #include <dt-bindings/pinctrl/rockchip.h> 14 + #include "rk3588s.dtsi" 15 + 16 + / { 17 + model = "RK3588S CoolPi 4 Model B"; 18 + compatible = "coolpi,pi-4b", "rockchip,rk3588s"; 19 + 20 + aliases { 21 + mmc0 = &sdhci; 22 + mmc1 = &sdio; 23 + mmc2 = &sdmmc; 24 + }; 25 + 26 + analog-sound { 27 + compatible = "audio-graph-card"; 28 + dais = <&i2s0_8ch_p0>; 29 + label = "rk3588-es8316"; 30 + routing = "MIC2", "Mic Jack", 31 + "Headphones", "HPOL", 32 + "Headphones", "HPOR"; 33 + widgets = "Microphone", "Mic Jack", 34 + "Headphone", "Headphones"; 35 + }; 36 + 37 + chosen { 38 + stdout-path = "serial2:1500000n8"; 39 + }; 40 + 41 + leds: leds { 42 + compatible = "gpio-leds"; 43 + pinctrl-names = "default"; 44 + pinctrl-0 = <&gpio_leds>; 45 + 46 + led0: led-green { 47 + color = <LED_COLOR_ID_GREEN>; 48 + function = LED_FUNCTION_STATUS; 49 + gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; 50 + linux,default-trigger = "heartbeat"; 51 + }; 52 + 53 + led1: led-red { 54 + color = <LED_COLOR_ID_RED>; 55 + default-state = "off"; 56 + function = LED_FUNCTION_WLAN; 57 + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 58 + linux,default-trigger = "phy0tx"; 59 + }; 60 + }; 61 + 62 + sdio_pwrseq: sdio-pwrseq { 63 + compatible = "mmc-pwrseq-simple"; 64 + clocks = <&hym8563>; 65 + clock-names = "ext_clock"; 66 + pinctrl-names = "default"; 67 + pinctrl-0 = <&wifi_enable_h>; 68 + /* 69 + * On the module itself this is one of these (depending 70 + * on the actual card populated): 71 + * - SDIO_RESET_L_WL_REG_ON 72 + * - PDN (power down when low) 73 + */ 74 + post-power-on-delay-ms = <200>; 75 + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; 76 + }; 77 + 78 + vcc12v_dcin: vcc12v-dcin-regulator { 79 + compatible = "regulator-fixed"; 80 + regulator-name = "vcc12v_dcin"; 81 + regulator-always-on; 82 + regulator-boot-on; 83 + regulator-min-microvolt = <12000000>; 84 + regulator-max-microvolt = <12000000>; 85 + }; 86 + 87 + vcc5v0_sys: vcc5v0-sys-regulator { 88 + compatible = "regulator-fixed"; 89 + regulator-name = "vcc5v0_sys"; 90 + regulator-always-on; 91 + regulator-boot-on; 92 + regulator-min-microvolt = <5000000>; 93 + regulator-max-microvolt = <5000000>; 94 + vin-supply = <&vcc12v_dcin>; 95 + }; 96 + 97 + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { 98 + compatible = "regulator-fixed"; 99 + regulator-name = "vcc5v0_usbdcin"; 100 + regulator-always-on; 101 + regulator-boot-on; 102 + regulator-min-microvolt = <5000000>; 103 + regulator-max-microvolt = <5000000>; 104 + vin-supply = <&vcc12v_dcin>; 105 + }; 106 + 107 + vcc5v0_usb: vcc5v0-usb-regulator { 108 + compatible = "regulator-fixed"; 109 + regulator-name = "vcc5v0_usb"; 110 + regulator-always-on; 111 + regulator-boot-on; 112 + regulator-min-microvolt = <5000000>; 113 + regulator-max-microvolt = <5000000>; 114 + vin-supply = <&vcc5v0_usbdcin>; 115 + }; 116 + 117 + avdd0v85_pcie20: avdd0v85-pcie20-regulator { 118 + compatible = "regulator-fixed"; 119 + regulator-name = "avdd0v85_pcie20"; 120 + regulator-boot-on; 121 + regulator-always-on; 122 + regulator-min-microvolt = <850000>; 123 + regulator-max-microvolt = <850000>; 124 + vin-supply = <&vdd_0v85_s0>; 125 + }; 126 + 127 + avdd1v8_pcie20: avdd1v8-pcie20-regulator { 128 + compatible = "regulator-fixed"; 129 + regulator-name = "avdd1v8_pcie20"; 130 + regulator-boot-on; 131 + regulator-always-on; 132 + regulator-min-microvolt = <1800000>; 133 + regulator-max-microvolt = <1800000>; 134 + vin-supply = <&avcc_1v8_s0>; 135 + }; 136 + 137 + vcc3v3_mipi: vcc3v3-mipi-regulator { 138 + compatible = "regulator-fixed"; 139 + enable-active-high; 140 + gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; 141 + regulator-name = "vcc3v3_mipi"; 142 + regulator-boot-on; 143 + regulator-always-on; 144 + vin-supply = <&vcc_3v3_s3>; 145 + }; 146 + 147 + vcc5v0_host: vcc5v0-host-regulator { 148 + compatible = "regulator-fixed"; 149 + enable-active-high; 150 + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 151 + pinctrl-names = "default"; 152 + pinctrl-0 = <&vcc5v0_host_en>; 153 + regulator-name = "vcc5v0_host"; 154 + regulator-boot-on; 155 + regulator-always-on; 156 + regulator-min-microvolt = <5000000>; 157 + regulator-max-microvolt = <5000000>; 158 + vin-supply = <&vcc5v0_sys>; 159 + }; 160 + 161 + vcc5v0_otg: vcc5v0-otg-regulator { 162 + compatible = "regulator-fixed"; 163 + enable-active-high; 164 + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 165 + pinctrl-names = "default"; 166 + pinctrl-0 = <&vcc5v0_u3host_en>; 167 + regulator-name = "vcc5v0_otg"; 168 + regulator-boot-on; 169 + regulator-always-on; 170 + regulator-min-microvolt = <5000000>; 171 + regulator-max-microvolt = <5000000>; 172 + vin-supply = <&vcc5v0_sys>; 173 + }; 174 + 175 + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { 176 + compatible = "regulator-fixed"; 177 + regulator-name = "vcc_1v1_nldo_s3"; 178 + regulator-always-on; 179 + regulator-boot-on; 180 + regulator-min-microvolt = <1100000>; 181 + regulator-max-microvolt = <1100000>; 182 + vin-supply = <&vcc5v0_sys>; 183 + }; 184 + }; 185 + 186 + &combphy0_ps { 187 + status = "okay"; 188 + }; 189 + 190 + &combphy2_psu { 191 + status = "okay"; 192 + }; 193 + 194 + &cpu_l0 { 195 + cpu-supply = <&vdd_cpu_lit_s0>; 196 + }; 197 + 198 + &cpu_b0 { 199 + cpu-supply = <&vdd_cpu_big0_s0>; 200 + }; 201 + 202 + &cpu_b2 { 203 + cpu-supply = <&vdd_cpu_big1_s0>; 204 + }; 205 + 206 + &i2c0 { 207 + pinctrl-0 = <&i2c0m2_xfer>; 208 + status = "okay"; 209 + 210 + vdd_cpu_big0_s0: regulator@42 { 211 + compatible = "rockchip,rk8602"; 212 + reg = <0x42>; 213 + fcs,suspend-voltage-selector = <1>; 214 + regulator-name = "vdd_cpu_big0_s0"; 215 + regulator-always-on; 216 + regulator-boot-on; 217 + regulator-min-microvolt = <550000>; 218 + regulator-max-microvolt = <1050000>; 219 + regulator-ramp-delay = <2300>; 220 + vin-supply = <&vcc5v0_sys>; 221 + 222 + regulator-state-mem { 223 + regulator-off-in-suspend; 224 + }; 225 + }; 226 + 227 + vdd_cpu_big1_s0: regulator@43 { 228 + compatible = "rockchip,rk8603", "rockchip,rk8602"; 229 + reg = <0x43>; 230 + fcs,suspend-voltage-selector = <1>; 231 + regulator-name = "vdd_cpu_big1_s0"; 232 + regulator-always-on; 233 + regulator-boot-on; 234 + regulator-min-microvolt = <550000>; 235 + regulator-max-microvolt = <1050000>; 236 + regulator-ramp-delay = <2300>; 237 + vin-supply = <&vcc5v0_sys>; 238 + 239 + regulator-state-mem { 240 + regulator-off-in-suspend; 241 + }; 242 + }; 243 + }; 244 + 245 + &i2c2 { 246 + status = "okay"; 247 + 248 + vdd_npu_s0: regulator@42 { 249 + compatible = "rockchip,rk8602"; 250 + reg = <0x42>; 251 + fcs,suspend-voltage-selector = <1>; 252 + regulator-name = "vdd_npu_s0"; 253 + regulator-always-on; 254 + regulator-boot-on; 255 + regulator-min-microvolt = <550000>; 256 + regulator-max-microvolt = <950000>; 257 + regulator-ramp-delay = <2300>; 258 + vin-supply = <&vcc5v0_sys>; 259 + 260 + regulator-state-mem { 261 + regulator-off-in-suspend; 262 + }; 263 + }; 264 + }; 265 + 266 + &i2c6 { 267 + pinctrl-0 = <&i2c6m3_xfer>; 268 + status = "okay"; 269 + 270 + hym8563: rtc@51 { 271 + compatible = "haoyu,hym8563"; 272 + reg = <0x51>; 273 + interrupt-parent = <&gpio0>; 274 + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 275 + #clock-cells = <0>; 276 + clock-output-names = "hym8563"; 277 + pinctrl-names = "default"; 278 + pinctrl-0 = <&hym8563_int>; 279 + }; 280 + }; 281 + 282 + &i2c7 { 283 + pinctrl-0 = <&i2c7m0_xfer>; 284 + status = "okay"; 285 + 286 + es8316: audio-codec@11 { 287 + compatible = "everest,es8316"; 288 + reg = <0x11>; 289 + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; 290 + assigned-clock-rates = <12288000>; 291 + clocks = <&cru I2S0_8CH_MCLKOUT>; 292 + clock-names = "mclk"; 293 + #sound-dai-cells = <0>; 294 + 295 + port { 296 + es8316_p0_0: endpoint { 297 + remote-endpoint = <&i2s0_8ch_p0_0>; 298 + }; 299 + }; 300 + }; 301 + }; 302 + 303 + &i2s0_8ch { 304 + pinctrl-0 = <&i2s0_lrck 305 + &i2s0_mclk 306 + &i2s0_sclk 307 + &i2s0_sdi0 308 + &i2s0_sdo0>; 309 + status = "okay"; 310 + 311 + i2s0_8ch_p0: port { 312 + i2s0_8ch_p0_0: endpoint { 313 + dai-format = "i2s"; 314 + mclk-fs = <256>; 315 + remote-endpoint = <&es8316_p0_0>; 316 + }; 317 + }; 318 + }; 319 + 320 + &pcie2x1l2 { 321 + pinctrl-names = "default"; 322 + pinctrl-0 = <&rtl8111_isolate>; 323 + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; 324 + status = "okay"; 325 + }; 326 + 327 + &pinctrl { 328 + hym8563 { 329 + hym8563_int: hym8563-int { 330 + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 331 + }; 332 + }; 333 + 334 + led { 335 + gpio_leds: gpio-leds { 336 + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, 337 + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; 338 + }; 339 + }; 340 + 341 + rtl8111 { 342 + rtl8111_isolate: rtl8111-isolate { 343 + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 344 + }; 345 + }; 346 + 347 + sdio-pwrseq { 348 + wifi_enable_h: wifi-enable-h { 349 + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 350 + }; 351 + }; 352 + 353 + usb { 354 + vcc5v0_host_en: vcc5v0-host-en { 355 + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, 356 + <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 357 + }; 358 + 359 + vcc5v0_u3host_en: vcc5v0-u3host-en { 360 + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 361 + }; 362 + }; 363 + 364 + wireless-bluetooth { 365 + bt_reset_gpio: bt-reset-pin { 366 + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 367 + }; 368 + 369 + bt_wake_gpio: bt-wake-pin { 370 + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 371 + }; 372 + 373 + bt_wake_host_irq: bt-wake-host-irq { 374 + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; 375 + }; 376 + }; 377 + 378 + wireless-wlan { 379 + wifi_host_wake_irq: wifi-host-wake-irq { 380 + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 381 + }; 382 + 383 + wifi_poweren_pin: wifi-poweren-pin { 384 + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 385 + }; 386 + }; 387 + }; 388 + 389 + &pwm2 { 390 + pinctrl-0 = <&pwm2m1_pins>; 391 + status = "okay"; 392 + }; 393 + 394 + &pwm13 { 395 + pinctrl-names = "active"; 396 + pinctrl-0 = <&pwm13m2_pins>; 397 + status = "okay"; 398 + }; 399 + 400 + &saradc { 401 + vref-supply = <&vcc_1v8_s0>; 402 + status = "okay"; 403 + }; 404 + 405 + &sdhci { 406 + bus-width = <8>; 407 + max-frequency = <200000000>; 408 + mmc-hs400-1_8v; 409 + mmc-hs400-enhanced-strobe; 410 + no-sdio; 411 + no-sd; 412 + non-removable; 413 + status = "okay"; 414 + }; 415 + 416 + &sdio { 417 + bus-width = <4>; 418 + cap-sd-highspeed; 419 + cap-sdio-irq; 420 + disable-wp; 421 + keep-power-in-suspend; 422 + max-frequency = <150000000>; 423 + mmc-pwrseq = <&sdio_pwrseq>; 424 + no-sd; 425 + no-mmc; 426 + non-removable; 427 + pinctrl-names = "default"; 428 + pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>; 429 + status = "okay"; 430 + }; 431 + 432 + &sdmmc { 433 + bus-width = <4>; 434 + cap-mmc-highspeed; 435 + cap-sd-highspeed; 436 + disable-wp; 437 + max-frequency = <150000000>; 438 + no-sdio; 439 + no-mmc; 440 + sd-uhs-sdr104; 441 + vmmc-supply = <&vcc_3v3_s3>; 442 + vqmmc-supply = <&vccio_sd_s0>; 443 + status = "okay"; 444 + }; 445 + 446 + &spi2 { 447 + assigned-clocks = <&cru CLK_SPI2>; 448 + assigned-clock-rates = <200000000>; 449 + num-cs = <1>; 450 + pinctrl-names = "default"; 451 + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 452 + status = "okay"; 453 + 454 + pmic@0 { 455 + compatible = "rockchip,rk806"; 456 + reg = <0x0>; 457 + interrupt-parent = <&gpio0>; 458 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 459 + gpio-controller; 460 + #gpio-cells = <2>; 461 + pinctrl-names = "default"; 462 + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 463 + <&rk806_dvs2_null>, <&rk806_dvs3_null>; 464 + spi-max-frequency = <1000000>; 465 + vcc1-supply = <&vcc5v0_sys>; 466 + vcc2-supply = <&vcc5v0_sys>; 467 + vcc3-supply = <&vcc5v0_sys>; 468 + vcc4-supply = <&vcc5v0_sys>; 469 + vcc5-supply = <&vcc5v0_sys>; 470 + vcc6-supply = <&vcc5v0_sys>; 471 + vcc7-supply = <&vcc5v0_sys>; 472 + vcc8-supply = <&vcc5v0_sys>; 473 + vcc9-supply = <&vcc5v0_sys>; 474 + vcc10-supply = <&vcc5v0_sys>; 475 + vcc11-supply = <&vcc_2v0_pldo_s3>; 476 + vcc12-supply = <&vcc5v0_sys>; 477 + vcc13-supply = <&vcc_1v1_nldo_s3>; 478 + vcc14-supply = <&vcc_1v1_nldo_s3>; 479 + vcca-supply = <&vcc5v0_sys>; 480 + 481 + rk806_dvs1_null: dvs1-null-pins { 482 + pins = "gpio_pwrctrl2"; 483 + function = "pin_fun0"; 484 + }; 485 + 486 + rk806_dvs2_null: dvs2-null-pins { 487 + pins = "gpio_pwrctrl2"; 488 + function = "pin_fun0"; 489 + }; 490 + 491 + rk806_dvs3_null: dvs3-null-pins { 492 + pins = "gpio_pwrctrl3"; 493 + function = "pin_fun0"; 494 + }; 495 + 496 + regulators { 497 + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { 498 + regulator-name = "vdd_gpu_s0"; 499 + regulator-boot-on; 500 + regulator-min-microvolt = <550000>; 501 + regulator-max-microvolt = <950000>; 502 + regulator-ramp-delay = <12500>; 503 + regulator-enable-ramp-delay = <400>; 504 + 505 + regulator-state-mem { 506 + regulator-off-in-suspend; 507 + }; 508 + }; 509 + 510 + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { 511 + regulator-name = "vdd_cpu_lit_s0"; 512 + regulator-always-on; 513 + regulator-boot-on; 514 + regulator-min-microvolt = <550000>; 515 + regulator-max-microvolt = <950000>; 516 + regulator-ramp-delay = <12500>; 517 + 518 + regulator-state-mem { 519 + regulator-off-in-suspend; 520 + }; 521 + }; 522 + 523 + vdd_log_s0: dcdc-reg3 { 524 + regulator-name = "vdd_log_s0"; 525 + regulator-always-on; 526 + regulator-boot-on; 527 + regulator-min-microvolt = <675000>; 528 + regulator-max-microvolt = <750000>; 529 + regulator-ramp-delay = <12500>; 530 + 531 + regulator-state-mem { 532 + regulator-off-in-suspend; 533 + regulator-suspend-microvolt = <750000>; 534 + }; 535 + }; 536 + 537 + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { 538 + regulator-name = "vdd_vdenc_s0"; 539 + regulator-always-on; 540 + regulator-boot-on; 541 + regulator-min-microvolt = <550000>; 542 + regulator-max-microvolt = <950000>; 543 + regulator-ramp-delay = <12500>; 544 + 545 + regulator-state-mem { 546 + regulator-off-in-suspend; 547 + }; 548 + }; 549 + 550 + vdd_ddr_s0: dcdc-reg5 { 551 + regulator-name = "vdd_ddr_s0"; 552 + regulator-always-on; 553 + regulator-boot-on; 554 + regulator-min-microvolt = <675000>; 555 + regulator-max-microvolt = <900000>; 556 + regulator-ramp-delay = <12500>; 557 + 558 + regulator-state-mem { 559 + regulator-off-in-suspend; 560 + regulator-suspend-microvolt = <850000>; 561 + }; 562 + }; 563 + 564 + vdd2_ddr_s3: dcdc-reg6 { 565 + regulator-name = "vdd2_ddr_s3"; 566 + regulator-always-on; 567 + regulator-boot-on; 568 + 569 + regulator-state-mem { 570 + regulator-on-in-suspend; 571 + }; 572 + }; 573 + 574 + vcc_2v0_pldo_s3: dcdc-reg7 { 575 + regulator-name = "vdd_2v0_pldo_s3"; 576 + regulator-always-on; 577 + regulator-boot-on; 578 + regulator-min-microvolt = <2000000>; 579 + regulator-max-microvolt = <2000000>; 580 + regulator-ramp-delay = <12500>; 581 + 582 + regulator-state-mem { 583 + regulator-on-in-suspend; 584 + regulator-suspend-microvolt = <2000000>; 585 + }; 586 + }; 587 + 588 + vcc_3v3_s3: dcdc-reg8 { 589 + regulator-name = "vcc_3v3_s3"; 590 + regulator-always-on; 591 + regulator-boot-on; 592 + regulator-min-microvolt = <3300000>; 593 + regulator-max-microvolt = <3300000>; 594 + 595 + regulator-state-mem { 596 + regulator-on-in-suspend; 597 + regulator-suspend-microvolt = <3300000>; 598 + }; 599 + }; 600 + 601 + vddq_ddr_s0: dcdc-reg9 { 602 + regulator-name = "vddq_ddr_s0"; 603 + regulator-always-on; 604 + regulator-boot-on; 605 + 606 + regulator-state-mem { 607 + regulator-off-in-suspend; 608 + }; 609 + }; 610 + 611 + vcc_1v8_s3: dcdc-reg10 { 612 + regulator-name = "vcc_1v8_s3"; 613 + regulator-always-on; 614 + regulator-boot-on; 615 + regulator-min-microvolt = <1800000>; 616 + regulator-max-microvolt = <1800000>; 617 + 618 + regulator-state-mem { 619 + regulator-on-in-suspend; 620 + regulator-suspend-microvolt = <1800000>; 621 + }; 622 + }; 623 + 624 + avcc_1v8_s0: pldo-reg1 { 625 + regulator-name = "avcc_1v8_s0"; 626 + regulator-always-on; 627 + regulator-boot-on; 628 + regulator-min-microvolt = <1800000>; 629 + regulator-max-microvolt = <1800000>; 630 + 631 + regulator-state-mem { 632 + regulator-off-in-suspend; 633 + }; 634 + }; 635 + 636 + vcc_1v8_s0: pldo-reg2 { 637 + regulator-name = "vcc_1v8_s0"; 638 + regulator-always-on; 639 + regulator-boot-on; 640 + regulator-min-microvolt = <1800000>; 641 + regulator-max-microvolt = <1800000>; 642 + 643 + regulator-state-mem { 644 + regulator-off-in-suspend; 645 + regulator-suspend-microvolt = <1800000>; 646 + }; 647 + }; 648 + 649 + avdd_1v2_s0: pldo-reg3 { 650 + regulator-name = "avdd_1v2_s0"; 651 + regulator-always-on; 652 + regulator-boot-on; 653 + regulator-min-microvolt = <1200000>; 654 + regulator-max-microvolt = <1200000>; 655 + 656 + regulator-state-mem { 657 + regulator-off-in-suspend; 658 + }; 659 + }; 660 + 661 + vcc_3v3_s0: pldo-reg4 { 662 + regulator-name = "vcc_3v3_s0"; 663 + regulator-always-on; 664 + regulator-boot-on; 665 + regulator-min-microvolt = <3300000>; 666 + regulator-max-microvolt = <3300000>; 667 + regulator-ramp-delay = <12500>; 668 + 669 + regulator-state-mem { 670 + regulator-off-in-suspend; 671 + }; 672 + }; 673 + 674 + vccio_sd_s0: pldo-reg5 { 675 + regulator-name = "vccio_sd_s0"; 676 + regulator-always-on; 677 + regulator-boot-on; 678 + regulator-min-microvolt = <1800000>; 679 + regulator-max-microvolt = <3300000>; 680 + regulator-ramp-delay = <12500>; 681 + 682 + regulator-state-mem { 683 + regulator-off-in-suspend; 684 + }; 685 + }; 686 + 687 + pldo6_s3: pldo-reg6 { 688 + regulator-name = "pldo6_s3"; 689 + regulator-always-on; 690 + regulator-boot-on; 691 + regulator-min-microvolt = <1800000>; 692 + regulator-max-microvolt = <1800000>; 693 + 694 + regulator-state-mem { 695 + regulator-on-in-suspend; 696 + regulator-suspend-microvolt = <1800000>; 697 + }; 698 + }; 699 + 700 + vdd_0v75_s3: nldo-reg1 { 701 + regulator-name = "vdd_0v75_s3"; 702 + regulator-always-on; 703 + regulator-boot-on; 704 + regulator-min-microvolt = <750000>; 705 + regulator-max-microvolt = <750000>; 706 + 707 + regulator-state-mem { 708 + regulator-on-in-suspend; 709 + regulator-suspend-microvolt = <750000>; 710 + }; 711 + }; 712 + 713 + vdd_ddr_pll_s0: nldo-reg2 { 714 + regulator-name = "vdd_ddr_pll_s0"; 715 + regulator-always-on; 716 + regulator-boot-on; 717 + regulator-min-microvolt = <850000>; 718 + regulator-max-microvolt = <850000>; 719 + 720 + regulator-state-mem { 721 + regulator-off-in-suspend; 722 + regulator-suspend-microvolt = <850000>; 723 + }; 724 + }; 725 + 726 + avdd_0v75_s0: nldo-reg3 { 727 + regulator-name = "avdd_0v75_s0"; 728 + regulator-always-on; 729 + regulator-boot-on; 730 + regulator-min-microvolt = <750000>; 731 + regulator-max-microvolt = <750000>; 732 + 733 + regulator-state-mem { 734 + regulator-off-in-suspend; 735 + }; 736 + }; 737 + 738 + vdd_0v85_s0: nldo-reg4 { 739 + regulator-name = "vdd_0v85_s0"; 740 + regulator-always-on; 741 + regulator-boot-on; 742 + regulator-min-microvolt = <850000>; 743 + regulator-max-microvolt = <850000>; 744 + 745 + regulator-state-mem { 746 + regulator-off-in-suspend; 747 + }; 748 + }; 749 + 750 + vdd_0v75_s0: nldo-reg5 { 751 + regulator-name = "vdd_0v75_s0"; 752 + regulator-always-on; 753 + regulator-boot-on; 754 + regulator-min-microvolt = <750000>; 755 + regulator-max-microvolt = <750000>; 756 + 757 + regulator-state-mem { 758 + regulator-off-in-suspend; 759 + }; 760 + }; 761 + }; 762 + }; 763 + }; 764 + 765 + &tsadc { 766 + status = "okay"; 767 + }; 768 + 769 + &u2phy2 { 770 + status = "okay"; 771 + }; 772 + 773 + &u2phy3 { 774 + status = "okay"; 775 + }; 776 + 777 + &u2phy2_host { 778 + phy-supply = <&vcc5v0_host>; 779 + status = "okay"; 780 + }; 781 + 782 + &u2phy3_host { 783 + status = "okay"; 784 + }; 785 + 786 + &uart2 { 787 + pinctrl-0 = <&uart2m0_xfer>; 788 + status = "okay"; 789 + }; 790 + 791 + /* bt */ 792 + &uart9 { 793 + status = "okay"; 794 + pinctrl-names = "default"; 795 + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; 796 + }; 797 + 798 + &usb_host0_ehci { 799 + status = "okay"; 800 + }; 801 + 802 + &usb_host0_ohci { 803 + status = "okay"; 804 + }; 805 + 806 + &usb_host1_ehci { 807 + status = "okay"; 808 + }; 809 + 810 + &usb_host1_ohci { 811 + status = "okay"; 812 + };

+1

arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts

··· 314 314 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 315 315 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 316 316 spi-max-frequency = <1000000>; 317 + system-power-controller; 317 318 318 319 vcc1-supply = <&vcc5v0_sys>; 319 320 vcc2-supply = <&vcc5v0_sys>;

+84

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

··· 394 394 #clock-cells = <0>; 395 395 }; 396 396 397 + display_subsystem: display-subsystem { 398 + compatible = "rockchip,display-subsystem"; 399 + ports = <&vop_out>; 400 + }; 401 + 397 402 timer { 398 403 compatible = "arm,armv8-timer"; 399 404 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, ··· 509 504 sys_grf: syscon@fd58c000 { 510 505 compatible = "rockchip,rk3588-sys-grf", "syscon"; 511 506 reg = <0x0 0xfd58c000 0x0 0x1000>; 507 + }; 508 + 509 + vop_grf: syscon@fd5a4000 { 510 + compatible = "rockchip,rk3588-vop-grf", "syscon"; 511 + reg = <0x0 0xfd5a4000 0x0 0x2000>; 512 + }; 513 + 514 + vo1_grf: syscon@fd5a8000 { 515 + compatible = "rockchip,rk3588-vo-grf", "syscon"; 516 + reg = <0x0 0xfd5a8000 0x0 0x100>; 512 517 }; 513 518 514 519 php_grf: syscon@fd5b0000 { ··· 637 622 pinctrl-names = "default"; 638 623 #address-cells = <1>; 639 624 #size-cells = <0>; 625 + status = "disabled"; 626 + }; 627 + 628 + vop: vop@fdd90000 { 629 + compatible = "rockchip,rk3588-vop"; 630 + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 631 + reg-names = "vop", "gamma-lut"; 632 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 633 + clocks = <&cru ACLK_VOP>, 634 + <&cru HCLK_VOP>, 635 + <&cru DCLK_VOP0>, 636 + <&cru DCLK_VOP1>, 637 + <&cru DCLK_VOP2>, 638 + <&cru DCLK_VOP3>, 639 + <&cru PCLK_VOP_ROOT>; 640 + clock-names = "aclk", 641 + "hclk", 642 + "dclk_vp0", 643 + "dclk_vp1", 644 + "dclk_vp2", 645 + "dclk_vp3", 646 + "pclk_vop"; 647 + iommus = <&vop_mmu>; 648 + power-domains = <&power RK3588_PD_VOP>; 649 + rockchip,grf = <&sys_grf>; 650 + rockchip,vop-grf = <&vop_grf>; 651 + rockchip,vo1-grf = <&vo1_grf>; 652 + rockchip,pmu = <&pmu>; 653 + status = "disabled"; 654 + 655 + vop_out: ports { 656 + #address-cells = <1>; 657 + #size-cells = <0>; 658 + 659 + vp0: port@0 { 660 + #address-cells = <1>; 661 + #size-cells = <0>; 662 + reg = <0>; 663 + }; 664 + 665 + vp1: port@1 { 666 + #address-cells = <1>; 667 + #size-cells = <0>; 668 + reg = <1>; 669 + }; 670 + 671 + vp2: port@2 { 672 + #address-cells = <1>; 673 + #size-cells = <0>; 674 + reg = <2>; 675 + }; 676 + 677 + vp3: port@3 { 678 + #address-cells = <1>; 679 + #size-cells = <0>; 680 + reg = <3>; 681 + }; 682 + }; 683 + }; 684 + 685 + vop_mmu: iommu@fdd97e00 { 686 + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 687 + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 688 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 689 + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 690 + clock-names = "aclk", "iface"; 691 + #iommu-cells = <0>; 692 + power-domains = <&power RK3588_PD_VOP>; 640 693 status = "disabled"; 641 694 }; 642 695 ··· 1031 948 reg = <RK3588_PD_USB>; 1032 949 clocks = <&cru PCLK_PHP_ROOT>, 1033 950 <&cru ACLK_USB_ROOT>, 951 + <&cru ACLK_USB>, 1034 952 <&cru HCLK_USB_ROOT>, 1035 953 <&cru HCLK_HOST0>, 1036 954 <&cru HCLK_HOST_ARB0>,