tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dsi: Add support for 28nm PHY on 8960
DSI PHY on MSM8960 and APQ8064 is a 28nm PHY that's different from the
supported 28nm LP PHY found in newer chips.
Add support for the new PHY.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
authored by
Archit Taneja
and committed by
Rob Clark
225380b3
e6c4c78c
+210
+8
drivers/gpu/drm/msm/Kconfig
+8
drivers/gpu/drm/msm/Kconfig
···
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default y
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help
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Choose this option if the 20nm DSI PHY is used on the platform.
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config DRM_MSM_DSI_28NM_8960_PHY
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bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
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depends on DRM_MSM_DSI
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default y
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help
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Choose this option if the 28nm DSI PHY 8960 variant is used on the
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platform.
+1
drivers/gpu/drm/msm/Makefile
+1
drivers/gpu/drm/msm/Makefile
+1
drivers/gpu/drm/msm/dsi/dsi.h
+1
drivers/gpu/drm/msm/dsi/dsi.h
+4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
···
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_pre;
+195
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+195
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
···
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/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "dsi_phy.h"
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#include "dsi.xml.h"
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static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy,
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struct msm_dsi_dphy_timing *timing)
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{
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void __iomem *base = phy->base;
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0,
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DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1,
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DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2,
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DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4,
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DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5,
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DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6,
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DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7,
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DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8,
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DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9,
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DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
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DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10,
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DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11,
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DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
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}
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static void dsi_28nm_phy_regulator_init(struct msm_dsi_phy *phy)
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{
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void __iomem *base = phy->reg_base;
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 1);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 1);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4,
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0x100);
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}
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static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy)
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{
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void __iomem *base = phy->reg_base;
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 0xa);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 0x4);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0x0);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, 0x20);
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}
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static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy)
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{
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void __iomem *base = phy->reg_base;
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u32 status;
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int i = 5000;
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG,
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0x3);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2, 0x0);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1, 0x5a);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3, 0x10);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4, 0x1);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0, 0x1);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x1);
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usleep_range(5000, 6000);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x0);
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do {
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status = dsi_phy_read(base +
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REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS);
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if (!(status & DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY))
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break;
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udelay(1);
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} while (--i > 0);
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}
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static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy)
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{
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void __iomem *base = phy->base;
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int i;
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for (i = 0; i < 4; i++) {
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i), 0x80);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i), 0x45);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i), 0x00);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i),
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0x00);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i),
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0x01);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i),
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0x66);
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}
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0, 0x40);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1, 0x67);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2, 0x0);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH, 0x0);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0, 0x1);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88);
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}
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static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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const unsigned long bit_rate, const unsigned long esc_rate)
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{
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struct msm_dsi_dphy_timing *timing = &phy->timing;
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void __iomem *base = phy->base;
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DBG("");
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if (msm_dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
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dev_err(&phy->pdev->dev,
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"%s: D-PHY timing calculation failed\n", __func__);
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return -EINVAL;
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}
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dsi_28nm_phy_regulator_init(phy);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LDO_CTRL, 0x04);
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/* strength control */
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_0, 0xff);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_1, 0x00);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_2, 0x06);
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/* phy ctrl */
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x5f);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_1, 0x00);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_2, 0x00);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_3, 0x10);
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dsi_28nm_phy_regulator_ctrl(phy);
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dsi_28nm_phy_calibration(phy);
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dsi_28nm_phy_lane_config(phy);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0f);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1, 0x03);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0, 0x03);
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dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0);
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dsi_28nm_dphy_set_timing(phy, timing);
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return 0;
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}
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static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
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{
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dsi_phy_write(phy->base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x0);
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/*
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* Wait for the registers writes to complete in order to
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* ensure that the phy is completely disabled
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*/
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wmb();
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}
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const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
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.type = MSM_DSI_PHY_28NM_8960,
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.src_pll_truthtable = { {true, true}, {false, true} },
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.reg_cfg = {
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.num = 1,
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.regs = {
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{"vddio", 1800000, 1800000, 100000, 100},
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},
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},
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.ops = {
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.enable = dsi_28nm_phy_enable,
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.disable = dsi_28nm_phy_disable,
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},
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};