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Merge tag 'imx-fixes-5.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.15, round 2:

- A couple of fixes from Haibo Chen to update SPI NOR TX bus width for
i.MX6 and i.MX8 boards. This becomes necessary because spi-nor driver
starts using the setting in DT.
- Mark buck2 always-on for i.MX8MM Kontron-n801x-som board to avoid the
core supply being turned off unexpectedly.
- Fix eSDHC2 device tree settings for LS1028A SoC.
- Disable GIC CPU interface before calling stby-poweroff sequence to fix
power-off failure on i.MX6.
- Fix M2_RST# GPIO pinmux on i.MX8M venice-gw7902 boards.

* tag 'imx-fixes-5.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8m*-venice-gw7902: fix M2_RST# gpio
ARM: imx6: disable the GIC CPU interface before calling stby-poweroff sequence
arm64: dts: ls1028a: fix eSDHC2 node
arm64: dts: imx8mm-kontron-n801x-som: do not allow to switch off buck2
arm64: dts: imx8: change the spi-nor tx
ARM: dts: imx: change the spi-nor tx

Link: https://lore.kernel.org/r/20211006125734.GA10197@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 22505963 34186b48

+17 -12
+2 -2
arch/arm/boot/dts/imx6sx-sdb.dts
··· 114 114 compatible = "micron,n25q256a", "jedec,spi-nor"; 115 115 spi-max-frequency = <29000000>; 116 116 spi-rx-bus-width = <4>; 117 - spi-tx-bus-width = <4>; 117 + spi-tx-bus-width = <1>; 118 118 reg = <0>; 119 119 }; 120 120 ··· 124 124 compatible = "micron,n25q256a", "jedec,spi-nor"; 125 125 spi-max-frequency = <29000000>; 126 126 spi-rx-bus-width = <4>; 127 - spi-tx-bus-width = <4>; 127 + spi-tx-bus-width = <1>; 128 128 reg = <2>; 129 129 }; 130 130 };
+1 -1
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
··· 292 292 compatible = "micron,n25q256a", "jedec,spi-nor"; 293 293 spi-max-frequency = <29000000>; 294 294 spi-rx-bus-width = <4>; 295 - spi-tx-bus-width = <4>; 295 + spi-tx-bus-width = <1>; 296 296 reg = <0>; 297 297 }; 298 298 };
+2
arch/arm/mach-imx/pm-imx6.c
··· 10 10 #include <linux/io.h> 11 11 #include <linux/irq.h> 12 12 #include <linux/genalloc.h> 13 + #include <linux/irqchip/arm-gic.h> 13 14 #include <linux/mfd/syscon.h> 14 15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 15 16 #include <linux/of.h> ··· 620 619 621 620 static void imx6_pm_stby_poweroff(void) 622 621 { 622 + gic_cpu_if_down(0); 623 623 imx6_set_lpm(STOP_POWER_OFF); 624 624 imx6q_suspend_finish(0); 625 625
+2 -2
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
··· 405 405 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 406 406 clock-frequency = <0>; /* fixed up by bootloader */ 407 407 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 408 - voltage-ranges = <1800 1800 3300 3300>; 408 + voltage-ranges = <1800 1800>; 409 409 sdhci,auto-cmd12; 410 - broken-cd; 410 + non-removable; 411 411 little-endian; 412 412 bus-width = <4>; 413 413 status = "disabled";
+1 -1
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
··· 91 91 #size-cells = <1>; 92 92 compatible = "jedec,spi-nor"; 93 93 spi-max-frequency = <80000000>; 94 - spi-tx-bus-width = <4>; 94 + spi-tx-bus-width = <1>; 95 95 spi-rx-bus-width = <4>; 96 96 }; 97 97 };
+1 -1
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
··· 48 48 #size-cells = <1>; 49 49 compatible = "jedec,spi-nor"; 50 50 spi-max-frequency = <80000000>; 51 - spi-tx-bus-width = <4>; 51 + spi-tx-bus-width = <1>; 52 52 spi-rx-bus-width = <4>; 53 53 }; 54 54 };
+1
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
··· 102 102 regulator-min-microvolt = <850000>; 103 103 regulator-max-microvolt = <950000>; 104 104 regulator-boot-on; 105 + regulator-always-on; 105 106 regulator-ramp-delay = <3125>; 106 107 nxp,dvs-run-voltage = <950000>; 107 108 nxp,dvs-standby-voltage = <850000>;
+1 -1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
··· 647 647 pinctrl_hog: hoggrp { 648 648 fsl,pins = < 649 649 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 650 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* M2_RST# */ 650 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ 651 651 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 652 652 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 653 653 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
+1 -1
arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
··· 101 101 #size-cells = <1>; 102 102 compatible = "jedec,spi-nor"; 103 103 spi-max-frequency = <80000000>; 104 - spi-tx-bus-width = <4>; 104 + spi-tx-bus-width = <1>; 105 105 spi-rx-bus-width = <4>; 106 106 }; 107 107 };
+1 -1
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
··· 633 633 pinctrl_hog: hoggrp { 634 634 fsl,pins = < 635 635 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 636 - MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* M2_RST# */ 636 + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ 637 637 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 638 638 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 639 639 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
+1 -1
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
··· 74 74 compatible = "jedec,spi-nor"; 75 75 reg = <0>; 76 76 spi-max-frequency = <80000000>; 77 - spi-tx-bus-width = <4>; 77 + spi-tx-bus-width = <1>; 78 78 spi-rx-bus-width = <4>; 79 79 }; 80 80 };
+2
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
··· 337 337 #size-cells = <1>; 338 338 compatible = "micron,n25q256a", "jedec,spi-nor"; 339 339 spi-max-frequency = <29000000>; 340 + spi-tx-bus-width = <1>; 341 + spi-rx-bus-width = <4>; 340 342 }; 341 343 }; 342 344
+1 -1
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
··· 281 281 #address-cells = <1>; 282 282 #size-cells = <1>; 283 283 reg = <0>; 284 - spi-tx-bus-width = <4>; 284 + spi-tx-bus-width = <1>; 285 285 spi-rx-bus-width = <4>; 286 286 m25p,fast-read; 287 287 spi-max-frequency = <50000000>;