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phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
Add some missing V6 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-1-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Abel Vesa
and committed by
Vinod Koul
2226ec07
7f6f9e0d
+6
+5
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+5
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
···
22
22
#define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34
23
23
#define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38
24
24
#define QSERDES_V6_COM_HSCLK_SEL_1 0x3c
25
+
#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1 0x40
26
+
#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1 0x44
25
27
#define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48
26
28
#define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c
27
29
#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
···
50
48
#define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac
51
49
#define QSERDES_V6_COM_BG_TIMER 0xbc
52
50
#define QSERDES_V6_COM_SSC_EN_CENTER 0xc0
51
+
#define QSERDES_V6_COM_SSC_ADJ_PER1 0xc4
53
52
#define QSERDES_V6_COM_SSC_PER1 0xcc
54
53
#define QSERDES_V6_COM_SSC_PER2 0xd0
55
54
#define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8
···
59
56
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
60
57
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
61
58
#define QSERDES_V6_COM_PLL_IVCO 0xf4
59
+
#define QSERDES_V6_COM_PLL_IVCO_MODE1 0xf8
62
60
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
63
61
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
64
62
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
···
67
63
#define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c
68
64
#define QSERDES_V6_COM_VCO_TUNE_MAP 0x140
69
65
#define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148
66
+
#define QSERDES_V6_COM_VCO_TUNE_MAXVAL2 0x158
70
67
#define QSERDES_V6_COM_CLK_SELECT 0x164
71
68
#define QSERDES_V6_COM_CORE_CLK_EN 0x170
72
69
#define QSERDES_V6_COM_CMN_CONFIG_1 0x174
+1
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+1
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
···
23
23
#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
24
24
#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
25
25
#define QSERDES_V6_TX_LANE_MODE_1 0x84
26
+
#define QSERDES_V6_TX_LANE_MODE_2 0x88
26
27
#define QSERDES_V6_TX_LANE_MODE_3 0x8c
27
28
#define QSERDES_V6_TX_LANE_MODE_4 0x90
28
29
#define QSERDES_V6_TX_LANE_MODE_5 0x94