tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC updates from Arnd Bergmann:
"The SoC updates this time are mainly removing obsolete code from the
OMAP2 platform, another step in the eternal cleanup of that platform.

There are two new SoCs getting added: STMicroelectronics stm32mp13 and
Microchip lan966. Both fit into existing platforms and require minimal
changes here.

A couple of MAINTAINER file updates relate to those changes, and
update some file paths"

* tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits)
MAINTAINERS: Update BCM7XXX entry with additional patterns
MAINTAINERS: add pinctrl-apple-gpio to ARM/APPLE MACHINE
MAINTAINERS: Add pasemi i2c to ARM/APPLE MACHINE
ARM: SPEAr: Update MAINTAINERS entries
ARM: OMAP2+: Drop unused CM defines for am3
ARM: OMAP2+: Drop unused CM and SCRM defines for omap4
ARM: OMAP2+: Drop unused CM and SCRM defines for omap5
ARM: OMAP2+: Drop unused CM defines for dra7
ARM: OMAP2+: Drop unused PRM defines for am3
ARM: OMAP2+: Drop unused PRM defines for am4
ARM: OMAP2+: Drop unused PRM defines for omap4
ARM: OMAP2+: Drop unused PRM defines for omap5
ARM: OMAP2+: Drop unused PRM defines for dra7
ARM: OMAP2+: Fix comment typo
ARM: OMAP2+: Fix typo in some comments
ARM: at91: add basic support for new SoC family lan966
dt-bindings: arm: at91: Document lan966 pcb8291 and pcb8290 boards
ARM: at91: Documentation: add lan966 family
ARM: at91: Documentation: add sama7g5 family
MAINTAINERS: add an entry for NXP S32G boards
...

Linus Torvalds 2219b0ce 43e1b129

+135 -4318
+1
Documentation/arm/index.rst
··· 55 55 stm32/stm32h750-overview 56 56 stm32/stm32f769-overview 57 57 stm32/stm32f429-overview 58 + stm32/stm32mp13-overview 58 59 stm32/stm32mp157-overview 59 60 60 61 sunxi
+20
Documentation/arm/microchip.rst
··· 137 137 138 138 http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001476B.pdf 139 139 140 + * ARM Cortex-A7 based SoCs 141 + - sama7g5 family 142 + 143 + - sama7g51 144 + - sama7g52 145 + - sama7g53 146 + - sama7g54 (device superset) 147 + 148 + * Datasheet 149 + 150 + Coming soon 151 + 152 + - lan966 family 153 + - lan9662 154 + - lan9668 155 + 156 + * Datasheet 157 + 158 + Coming soon 159 + 140 160 * ARM Cortex-M7 MCUs 141 161 - sams70 family 142 162
+37
Documentation/arm/stm32/stm32mp13-overview.rst
··· 1 + =================== 2 + STM32MP13 Overview 3 + =================== 4 + 5 + Introduction 6 + ------------ 7 + 8 + The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications. 9 + They feature: 10 + 11 + - One Cortex-A7 application core 12 + - Standard memories interface support 13 + - Standard connectivity, widely inherited from the STM32 MCU family 14 + - Comprehensive security support 15 + 16 + More details: 17 + 18 + - Cortex-A7 core running up to @900MHz 19 + - FMC controller to connect SDRAM, NOR and NAND memories 20 + - QSPI 21 + - SD/MMC/SDIO support 22 + - 2*Ethernet controller 23 + - CAN 24 + - ADC/DAC 25 + - USB EHCI/OHCI controllers 26 + - USB OTG 27 + - I2C, SPI, CAN busses support 28 + - Several general purpose timers 29 + - Serial Audio interface 30 + - LCD controller 31 + - DCMIPP 32 + - SPDIFRX 33 + - DFSDM 34 + 35 + :Authors: 36 + 37 + - Alexandre Torgue <alexandre.torgue@foss.st.com>
+12
Documentation/devicetree/bindings/arm/atmel-at91.yaml
··· 150 150 - const: microchip,sama7g5 151 151 - const: microchip,sama7 152 152 153 + - description: Microchip LAN9662 PCB8291 Evaluation Board. 154 + items: 155 + - const: microchip,lan9662-pcb8291 156 + - const: microchip,lan9662 157 + - const: microchip,lan966 158 + 159 + - description: Microchip LAN9668 PCB8290 Evaluation Board. 160 + items: 161 + - const: microchip,lan9668-pcb8290 162 + - const: microchip,lan9668 163 + - const: microchip,lan966 164 + 153 165 - items: 154 166 - enum: 155 167 - atmel,sams70j19
+18 -15
MAINTAINERS
··· 1721 1721 C: irc://irc.oftc.net/asahi-dev 1722 1722 T: git https://github.com/AsahiLinux/linux.git 1723 1723 F: Documentation/devicetree/bindings/arm/apple.yaml 1724 + F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml 1724 1725 F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml 1725 1726 F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml 1726 1727 F: Documentation/devicetree/bindings/pci/apple,pcie.yaml 1727 1728 F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml 1728 1729 F: arch/arm64/boot/dts/apple/ 1730 + F: drivers/i2c/busses/i2c-pasemi-core.c 1731 + F: drivers/i2c/busses/i2c-pasemi-platform.c 1729 1732 F: drivers/irqchip/irq-apple-aic.c 1730 1733 F: drivers/mailbox/apple-mailbox.c 1734 + F: drivers/pinctrl/pinctrl-apple-gpio.c 1731 1735 F: include/dt-bindings/interrupt-controller/apple-aic.h 1732 1736 F: include/dt-bindings/pinctrl/apple.h 1733 1737 F: include/linux/apple-mailbox.h ··· 2318 2314 F: arch/arm/boot/dts/nuvoton-wpcm450* 2319 2315 F: arch/arm/mach-npcm/wpcm450.c 2320 2316 F: drivers/*/*wpcm* 2317 + 2318 + ARM/NXP S32G ARCHITECTURE 2319 + M: Chester Lin <clin@suse.com> 2320 + R: Andreas Färber <afaerber@suse.de> 2321 + R: Matthias Brugger <mbrugger@suse.com> 2322 + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 2323 + S: Maintained 2324 + F: arch/arm64/boot/dts/freescale/s32g*.dts* 2321 2325 2322 2326 ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT 2323 2327 L: openmoko-kernel@lists.openmoko.org (subscribers-only) ··· 3645 3633 F: drivers/bus/brcmstb_gisb.c 3646 3634 F: drivers/pci/controller/pcie-brcmstb.c 3647 3635 N: brcmstb 3636 + N: bcm7038 3637 + N: bcm7120 3648 3638 3649 3639 BROADCOM BDC DRIVER 3650 3640 M: Al Cooper <alcooperx@gmail.com> ··· 15001 14987 S: Maintained 15002 14988 F: drivers/pinctrl/pinctrl-single.c 15003 14989 15004 - PIN CONTROLLER - ST SPEAR 15005 - M: Viresh Kumar <vireshk@kernel.org> 15006 - L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 15007 - S: Maintained 15008 - W: http://www.st.com/spear 15009 - F: drivers/pinctrl/spear/ 15010 - 15011 14990 PKTCDVD DRIVER 15012 14991 M: linux-block@vger.kernel.org 15013 14992 S: Orphan ··· 17778 17771 B: https://github.com/linux-speakup/speakup/issues 17779 17772 F: drivers/accessibility/speakup/ 17780 17773 17781 - SPEAR CLOCK FRAMEWORK SUPPORT 17782 - M: Viresh Kumar <vireshk@kernel.org> 17783 - L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 17784 - S: Maintained 17785 - W: http://www.st.com/spear 17786 - F: drivers/clk/spear/ 17787 - 17788 - SPEAR PLATFORM SUPPORT 17774 + SPEAR PLATFORM/CLOCK/PINCTRL SUPPORT 17789 17775 M: Viresh Kumar <vireshk@kernel.org> 17790 17776 M: Shiraz Hashim <shiraz.linux.kernel@gmail.com> 17777 + M: soc@kernel.org 17791 17778 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 17792 17779 S: Maintained 17793 17780 W: http://www.st.com/spear 17794 17781 F: arch/arm/boot/dts/spear* 17795 17782 F: arch/arm/mach-spear/ 17783 + F: drivers/clk/spear/ 17784 + F: drivers/pinctrl/spear/ 17796 17785 17797 17786 SPI NOR SUBSYSTEM 17798 17787 M: Tudor Ambarus <tudor.ambarus@microchip.com>
+9
arch/arm/mach-at91/Kconfig
··· 67 67 help 68 68 Select this if you are using one of Microchip's SAMA7G5 family SoC. 69 69 70 + config SOC_LAN966 71 + bool "ARMv7 based Microchip LAN966 SoC family" 72 + depends on ARCH_MULTI_V7 73 + select DW_APB_TIMER_OF 74 + select ARM_GIC 75 + select MEMORY 76 + help 77 + This enables support for ARMv7 based Microchip LAN966 SoC family. 78 + 70 79 config SOC_AT91RM9200 71 80 bool "AT91RM9200" 72 81 depends on ARCH_MULTI_V4T
-101
arch/arm/mach-omap2/cm-regbits-44xx.h
··· 20 20 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 21 21 22 22 #define OMAP4430_ABE_STATDEP_SHIFT 3 23 - #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 24 - #define OMAP4430_CLKSEL_SHIFT 24 25 - #define OMAP4430_CLKSEL_WIDTH 0x1 26 - #define OMAP4430_CLKSEL_MASK (1 << 24) 27 - #define OMAP4430_CLKSEL_0_0_SHIFT 0 28 - #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 29 - #define OMAP4430_CLKSEL_0_1_SHIFT 0 30 - #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 31 - #define OMAP4430_CLKSEL_24_25_SHIFT 24 32 - #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 33 - #define OMAP4430_CLKSEL_60M_SHIFT 24 34 - #define OMAP4430_CLKSEL_60M_WIDTH 0x1 35 - #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 36 - #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 37 - #define OMAP4430_CLKSEL_CORE_SHIFT 0 38 - #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 39 - #define OMAP4430_CLKSEL_DIV_SHIFT 24 40 - #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 41 - #define OMAP4430_CLKSEL_FCLK_SHIFT 24 42 - #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 43 - #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 44 - #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 45 - #define OMAP4430_CLKSEL_L3_SHIFT 4 46 - #define OMAP4430_CLKSEL_L3_WIDTH 0x1 47 - #define OMAP4430_CLKSEL_L4_SHIFT 8 48 - #define OMAP4430_CLKSEL_L4_WIDTH 0x1 49 - #define OMAP4430_CLKSEL_OPP_SHIFT 0 50 - #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 51 - #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 52 - #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 53 - #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) 54 - #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) 55 - #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) 56 - #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 57 - #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 58 - #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 59 - #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 60 - #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 61 23 #define OMAP4430_CLKTRCTRL_SHIFT 0 62 24 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 63 - #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 64 - #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 65 - #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 66 - #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 67 - #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 68 - #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 69 - #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 70 - #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 71 - #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 72 - #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 73 - #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 74 - #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 75 - #define OMAP4430_DPLL_EN_MASK (0x7 << 0) 76 - #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 77 - #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 78 - #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 79 - #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 80 - #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 81 25 #define OMAP4430_DSS_STATDEP_SHIFT 8 82 26 #define OMAP4430_DUCATI_STATDEP_SHIFT 0 83 27 #define OMAP4430_GFX_STATDEP_SHIFT 10 84 - #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 85 - #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 86 - #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 87 - #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 88 28 #define OMAP4430_IDLEST_SHIFT 16 89 29 #define OMAP4430_IDLEST_MASK (0x3 << 16) 90 30 #define OMAP4430_IVAHD_STATDEP_SHIFT 2 ··· 38 98 #define OMAP4430_MEMIF_STATDEP_SHIFT 4 39 99 #define OMAP4430_MODULEMODE_SHIFT 0 40 100 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) 41 - #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 42 - #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 43 - #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 44 - #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 45 - #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 46 - #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 47 - #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 48 - #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 49 - #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 50 - #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 51 - #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 52 - #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 53 - #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 54 - #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 55 - #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 56 - #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 57 - #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 58 - #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 59 - #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 60 - #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 61 - #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 62 - #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 63 - #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 64 - #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 65 - #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 66 - #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 67 - #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 68 - #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 69 - #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 70 - #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 71 - #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 72 - #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 73 - #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 74 - #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 75 - #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 76 - #define OMAP4430_SCALE_FCLK_SHIFT 0 77 - #define OMAP4430_SCALE_FCLK_WIDTH 0x1 78 - #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 79 - #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) 80 - #define OMAP4430_SYS_CLKSEL_SHIFT 0 81 - #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 82 101 #define OMAP4430_TESLA_STATDEP_SHIFT 1 83 102 #endif
-174
arch/arm/mach-omap2/cm1_44xx.h
··· 34 34 #define OMAP4430_CM1_MPU_INST 0x0300 35 35 #define OMAP4430_CM1_TESLA_INST 0x0400 36 36 #define OMAP4430_CM1_ABE_INST 0x0500 37 - #define OMAP4430_CM1_RESTORE_INST 0x0e00 38 - #define OMAP4430_CM1_INSTR_INST 0x0f00 39 37 40 38 /* CM1 clockdomain register offsets (from instance start) */ 41 39 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 42 40 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 43 41 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 44 - 45 - /* CM1 */ 46 - 47 - /* CM1.OCP_SOCKET_CM1 register offsets */ 48 - #define OMAP4_REVISION_CM1_OFFSET 0x0000 49 - #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) 50 - #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 51 - #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) 52 - 53 - /* CM1.CKGEN_CM1 register offsets */ 54 - #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 55 - #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) 56 - #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 57 - #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) 58 - #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 59 - #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) 60 - #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 61 - #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) 62 - #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 63 - #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) 64 - #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 65 - #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) 66 - #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 67 - #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) 68 - #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 69 - #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) 70 - #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 71 - #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) 72 - #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 73 - #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) 74 - #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 75 - #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) 76 - #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 77 - #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) 78 - #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 79 - #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 80 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 81 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 82 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 83 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 84 - #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 85 - #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 86 - #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 87 - #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) 88 - #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 89 - #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) 90 - #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 91 - #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) 92 - #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 93 - #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) 94 - #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 95 - #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 96 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 97 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 98 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 99 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 100 - #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 101 - #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 102 - #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 103 - #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) 104 - #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 105 - #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) 106 - #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 107 - #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) 108 - #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 109 - #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) 110 - #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 111 - #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) 112 - #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 113 - #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 114 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 115 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 116 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 117 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 118 - #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 119 - #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 120 - #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 121 - #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) 122 - #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 123 - #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) 124 - #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 125 - #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) 126 - #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 127 - #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) 128 - #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 129 - #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) 130 - #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 131 - #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 132 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 133 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 134 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 135 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 136 - #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 137 - #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 138 - #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 139 - #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) 140 - #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 141 - #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) 142 - #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 143 - #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) 144 - #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 145 - #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) 146 - #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 147 - #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) 148 - #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 149 - #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) 150 - #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 151 - #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 152 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 153 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 154 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 155 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 156 - #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 157 - #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 158 - #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 159 - #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) 160 - #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 161 - #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) 162 - #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 163 - #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) 164 - 165 - /* CM1.MPU_CM1 register offsets */ 166 - #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 167 - #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) 168 - #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 169 - #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) 170 - #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 171 - #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) 172 - #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 173 - #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) 174 - 175 - /* CM1.TESLA_CM1 register offsets */ 176 - #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 177 - #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) 178 - #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 179 - #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) 180 - #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 181 - #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) 182 - #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 183 - #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) 184 - 185 - /* CM1.ABE_CM1 register offsets */ 186 - #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 187 - #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) 188 - #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 189 - #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) 190 - #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 191 - #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) 192 - #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 193 - #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) 194 - #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 195 - #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) 196 - #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 197 - #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) 198 - #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 199 - #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) 200 - #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 201 - #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) 202 - #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 203 - #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) 204 - #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 205 - #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) 206 - #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 207 - #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) 208 - #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 209 - #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) 210 - #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 211 - #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) 212 - #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 213 - #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) 214 - #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 215 - #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 216 42 217 43 #endif
-168
arch/arm/mach-omap2/cm1_54xx.h
··· 30 30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300 31 31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400 32 32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500 33 - #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00 34 - #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00 35 33 36 34 /* CM_CORE_AON clockdomain register offsets (from instance start) */ 37 35 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 38 36 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000 39 37 #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000 40 - 41 - /* CM_CORE_AON */ 42 - 43 - /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ 44 - #define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000 45 - #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 46 - #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) 47 - #define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080 48 - #define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084 49 - #define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090 50 - #define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094 51 - #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098 52 - #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c 53 - #define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0 54 - #define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4 55 - #define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8 56 - #define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac 57 - #define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0 58 - #define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4 59 - #define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8 60 - #define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc 61 - #define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0 62 - #define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4 63 - #define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8 64 - #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc 65 - #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0 66 - #define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4 67 - #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8 68 - #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc 69 - #define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0 70 - #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4 71 - #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8 72 - #define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec 73 - #define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0 74 - 75 - /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ 76 - #define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000 77 - #define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000) 78 - #define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008 79 - #define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008) 80 - #define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010 81 - #define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 82 - #define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020) 83 - #define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 84 - #define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024) 85 - #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 86 - #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028) 87 - #define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 88 - #define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c) 89 - #define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 90 - #define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030) 91 - #define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 92 - #define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034) 93 - #define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 94 - #define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038) 95 - #define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c 96 - #define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c) 97 - #define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 98 - #define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040) 99 - #define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 100 - #define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044) 101 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 102 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 103 - #define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 104 - #define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050) 105 - #define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 106 - #define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054) 107 - #define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 108 - #define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058) 109 - #define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c 110 - #define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c) 111 - #define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 112 - #define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060) 113 - #define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 114 - #define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064) 115 - #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 116 - #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068) 117 - #define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 118 - #define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c) 119 - #define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 120 - #define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070) 121 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 122 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 123 - #define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 124 - #define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c) 125 - #define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 126 - #define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0) 127 - #define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 128 - #define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4) 129 - #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 130 - #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8) 131 - #define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 132 - #define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac) 133 - #define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8 134 - #define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8) 135 - #define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc 136 - #define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc) 137 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 138 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 139 - #define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 140 - #define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc) 141 - #define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 142 - #define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0) 143 - #define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 144 - #define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4) 145 - #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 146 - #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8) 147 - #define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 148 - #define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec) 149 - #define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 150 - #define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0) 151 - #define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 152 - #define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4) 153 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 154 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 155 - #define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 156 - #define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 157 - #define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 158 - #define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180 159 - 160 - /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ 161 - #define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 162 - #define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004 163 - #define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 164 - #define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 165 - #define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020) 166 - #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 167 - #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028) 168 - 169 - /* CM_CORE_AON.DSP_CM_CORE_AON register offsets */ 170 - #define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000 171 - #define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004 172 - #define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008 173 - #define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020 174 - #define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020) 175 - 176 - /* CM_CORE_AON.ABE_CM_CORE_AON register offsets */ 177 - #define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000 178 - #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020 179 - #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020) 180 - #define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028 181 - #define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028) 182 - #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030 183 - #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030) 184 - #define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038 185 - #define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038) 186 - #define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040 187 - #define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040) 188 - #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 189 - #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048) 190 - #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 191 - #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050) 192 - #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 193 - #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058) 194 - #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060 195 - #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060) 196 - #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 197 - #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068) 198 - #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 199 - #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070) 200 - #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 201 - #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078) 202 - #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 203 - #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080) 204 - #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088 205 - #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088) 206 38 207 39 #endif
-263
arch/arm/mach-omap2/cm1_7xx.h
··· 38 38 #define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700 39 39 #define DRA7XX_CM_CORE_AON_RTC_INST 0x0740 40 40 #define DRA7XX_CM_CORE_AON_VPE_INST 0x0760 41 - #define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00 42 - #define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00 43 41 44 42 /* CM_CORE_AON clockdomain register offsets (from instance start) */ 45 43 #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 ··· 51 53 #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000 52 54 #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000 53 55 #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000 54 - 55 - /* CM_CORE_AON */ 56 - 57 - /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ 58 - #define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000 59 - #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 60 - #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) 61 - #define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec 62 - #define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0 63 - #define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4 64 - #define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8 65 - #define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc 66 - 67 - /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ 68 - #define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000 69 - #define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000) 70 - #define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008 71 - #define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008) 72 - #define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010 73 - #define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 74 - #define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020) 75 - #define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 76 - #define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024) 77 - #define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 78 - #define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028) 79 - #define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 80 - #define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c) 81 - #define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 82 - #define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030) 83 - #define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 84 - #define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034) 85 - #define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 86 - #define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038) 87 - #define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c 88 - #define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c) 89 - #define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 90 - #define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040) 91 - #define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 92 - #define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044) 93 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 94 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 95 - #define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 96 - #define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050) 97 - #define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 98 - #define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054) 99 - #define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 100 - #define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058) 101 - #define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c 102 - #define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c) 103 - #define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 104 - #define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060) 105 - #define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 106 - #define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064) 107 - #define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 108 - #define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068) 109 - #define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 110 - #define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c) 111 - #define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 112 - #define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070) 113 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 114 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 115 - #define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 116 - #define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c) 117 - #define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 118 - #define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0) 119 - #define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 120 - #define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4) 121 - #define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 122 - #define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8) 123 - #define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 124 - #define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac) 125 - #define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0 126 - #define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0) 127 - #define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4 128 - #define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4) 129 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 130 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 131 - #define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 132 - #define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc) 133 - #define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 134 - #define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0) 135 - #define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 136 - #define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4) 137 - #define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 138 - #define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8) 139 - #define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 140 - #define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec) 141 - #define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 142 - #define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0) 143 - #define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 144 - #define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4) 145 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 146 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 147 - #define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110 148 - #define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110) 149 - #define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114 150 - #define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114) 151 - #define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118 152 - #define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118) 153 - #define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c 154 - #define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c) 155 - #define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120 156 - #define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120) 157 - #define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124 158 - #define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124) 159 - #define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128 160 - #define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128) 161 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c 162 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130 163 - #define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134 164 - #define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134) 165 - #define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138 166 - #define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138) 167 - #define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c 168 - #define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c) 169 - #define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140 170 - #define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140) 171 - #define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144 172 - #define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144) 173 - #define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148 174 - #define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148) 175 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c 176 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150 177 - #define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154 178 - #define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154) 179 - #define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 180 - #define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 181 - #define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 182 - #define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180 183 - #define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184 184 - #define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184) 185 - #define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188 186 - #define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188) 187 - #define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c 188 - #define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c) 189 - #define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190 190 - #define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190) 191 - #define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194 192 - #define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194) 193 - #define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198 194 - #define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198) 195 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c 196 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0 197 - #define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4 198 - #define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4) 199 - #define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8 200 - #define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8) 201 - #define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac 202 - #define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac) 203 - #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0 204 - #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0) 205 - #define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4 206 - #define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4) 207 - #define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8 208 - #define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8) 209 - #define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc 210 - #define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc) 211 - #define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0 212 - #define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0) 213 - #define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4 214 - #define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4) 215 - #define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8 216 - #define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8) 217 - #define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc 218 - #define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc) 219 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0 220 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4 221 - #define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8 222 - #define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8) 223 - #define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc 224 - #define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc) 225 - #define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0 226 - #define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0) 227 - #define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4 228 - #define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4) 229 - #define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8 230 - #define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8) 231 - #define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec 232 - #define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec) 233 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0 234 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4 235 - 236 - /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ 237 - #define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 238 - #define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004 239 - #define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 240 - #define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 241 - #define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020) 242 - #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 243 - #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028) 244 - 245 - /* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */ 246 - #define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000 247 - #define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004 248 - #define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008 249 - #define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020 250 - #define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020) 251 - 252 - /* CM_CORE_AON.IPU_CM_CORE_AON register offsets */ 253 - #define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000 254 - #define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004 255 - #define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008 256 - #define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020 257 - #define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020) 258 - #define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040 259 - #define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050 260 - #define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050) 261 - #define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058 262 - #define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058) 263 - #define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060 264 - #define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060) 265 - #define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068 266 - #define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068) 267 - #define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070 268 - #define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070) 269 - #define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078 270 - #define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078) 271 - #define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080 272 - #define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080) 273 - 274 - /* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */ 275 - #define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000 276 - #define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004 277 - #define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008 278 - #define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020 279 - #define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020) 280 - 281 - /* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */ 282 - #define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000 283 - #define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004 284 - #define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020 285 - #define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020) 286 - 287 - /* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */ 288 - #define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000 289 - #define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004 290 - #define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020 291 - #define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020) 292 - 293 - /* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */ 294 - #define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000 295 - #define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004 296 - #define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020 297 - #define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020) 298 - 299 - /* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */ 300 - #define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000 301 - #define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004 302 - #define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020 303 - #define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020) 304 - 305 - /* CM_CORE_AON.RTC_CM_CORE_AON register offsets */ 306 - #define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000 307 - #define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004 308 - #define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004) 309 - 310 - /* CM_CORE_AON.VPE_CM_CORE_AON register offsets */ 311 - #define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000 312 - #define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004 313 - #define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004) 314 - #define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008 315 56 316 57 #endif
-386
arch/arm/mach-omap2/cm2_44xx.h
··· 40 40 #define OMAP4430_CM2_L3INIT_INST 0x1300 41 41 #define OMAP4430_CM2_L4PER_INST 0x1400 42 42 #define OMAP4430_CM2_CEFUSE_INST 0x1600 43 - #define OMAP4430_CM2_RESTORE_INST 0x1e00 44 - #define OMAP4430_CM2_INSTR_INST 0x1f00 45 43 46 44 /* CM2 clockdomain register offsets (from instance start) */ 47 45 #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 ··· 59 61 #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 60 62 #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 61 63 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 62 - 63 - /* CM2 */ 64 - 65 - /* CM2.OCP_SOCKET_CM2 register offsets */ 66 - #define OMAP4_REVISION_CM2_OFFSET 0x0000 67 - #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) 68 - #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 69 - #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) 70 - 71 - /* CM2.CKGEN_CM2 register offsets */ 72 - #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 73 - #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) 74 - #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 75 - #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) 76 - #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 77 - #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) 78 - #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 79 - #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) 80 - #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 81 - #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) 82 - #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 83 - #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) 84 - #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c 85 - #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) 86 - #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 87 - #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) 88 - #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 89 - #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) 90 - #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c 91 - #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) 92 - #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 93 - #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) 94 - #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 95 - #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) 96 - #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 97 - #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) 98 - #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 99 - #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) 100 - #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 101 - #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) 102 - #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 103 - #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) 104 - #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 105 - #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) 106 - #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 107 - #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) 108 - #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 109 - #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) 110 - #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c 111 - #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) 112 - #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 113 - #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) 114 - #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 115 - #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 116 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 117 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 118 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 119 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 120 - #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 121 - #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 122 - #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 123 - #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) 124 - #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 125 - #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) 126 - #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 127 - #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) 128 - #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 129 - #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 130 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 131 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 132 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 133 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 134 - #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 135 - #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 136 - #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 137 - #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) 138 - #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 139 - #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) 140 - #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 141 - #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) 142 - #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc 143 - #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) 144 - #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 145 - #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 146 - #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 147 - #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 148 - #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 149 - #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 150 - 151 - /* CM2.ALWAYS_ON_CM2 register offsets */ 152 - #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 153 - #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) 154 - #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 155 - #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) 156 - #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 157 - #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) 158 - #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 159 - #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) 160 - #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 161 - #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) 162 - #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 163 - #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) 164 - 165 - /* CM2.CORE_CM2 register offsets */ 166 - #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 167 - #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) 168 - #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 169 - #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) 170 - #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 171 - #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) 172 - #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 173 - #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) 174 - #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 175 - #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) 176 - #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 177 - #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) 178 - #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 179 - #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) 180 - #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 181 - #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) 182 - #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 183 - #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) 184 - #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 185 - #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) 186 - #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 187 - #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) 188 - #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 189 - #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) 190 - #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 191 - #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) 192 - #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 193 - #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) 194 - #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 195 - #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) 196 - #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 197 - #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) 198 - #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 199 - #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) 200 - #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 201 - #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) 202 - #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 203 - #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) 204 - #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 205 - #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) 206 - #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 207 - #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) 208 - #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 209 - #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) 210 - #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 211 - #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) 212 - #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 213 - #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) 214 - #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 215 - #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) 216 - #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 217 - #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) 218 - #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 219 - #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) 220 - #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 221 - #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 222 - #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 223 - #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 224 - #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 225 - #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 226 - #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 227 - #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 228 - #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 229 - #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) 230 - #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 231 - #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) 232 - #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 233 - #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) 234 - #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 235 - #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) 236 - #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 237 - #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) 238 - #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 239 - #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) 240 - #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 241 - #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) 242 - #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 243 - #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) 244 - #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 245 - #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) 246 - #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 247 - #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) 248 - 249 - /* CM2.IVAHD_CM2 register offsets */ 250 - #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 251 - #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) 252 - #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 253 - #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) 254 - #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 255 - #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) 256 - #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 257 - #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) 258 - #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 259 - #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) 260 - 261 - /* CM2.CAM_CM2 register offsets */ 262 - #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 263 - #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) 264 - #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 265 - #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) 266 - #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 267 - #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) 268 - #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 269 - #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) 270 - #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 271 - #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) 272 - 273 - /* CM2.DSS_CM2 register offsets */ 274 - #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 275 - #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) 276 - #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 277 - #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) 278 - #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 279 - #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) 280 - #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 281 - #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) 282 - #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 283 - #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) 284 - 285 - /* CM2.GFX_CM2 register offsets */ 286 - #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 287 - #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) 288 - #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 289 - #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) 290 - #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 291 - #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) 292 - #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 293 - #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) 294 - 295 - /* CM2.L3INIT_CM2 register offsets */ 296 - #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 297 - #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) 298 - #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 299 - #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) 300 - #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 301 - #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) 302 - #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 303 - #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) 304 - #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 305 - #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) 306 - #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 307 - #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) 308 - #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 309 - #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) 310 - #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 311 - #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) 312 - #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 313 - #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) 314 - #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 315 - #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) 316 - #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 317 - #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) 318 - #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 319 - #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) 320 - #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 321 - #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) 322 - #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 323 - #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) 324 - #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 325 - #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) 326 - #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 327 - #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) 328 - #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 329 - #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) 330 - #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 331 - #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) 332 - #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 333 - #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) 334 - #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 335 - #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) 336 - 337 - /* CM2.L4PER_CM2 register offsets */ 338 - #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 339 - #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) 340 - #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 341 - #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) 342 - #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 343 - #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) 344 - #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 345 - #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) 346 - #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 347 - #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) 348 - #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 349 - #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) 350 - #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 351 - #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) 352 - #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 353 - #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) 354 - #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 355 - #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) 356 - #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 357 - #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) 358 - #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 359 - #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) 360 - #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 361 - #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) 362 - #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 363 - #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) 364 - #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 365 - #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) 366 - #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 367 - #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) 368 - #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 369 - #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) 370 - #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 371 - #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) 372 - #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 373 - #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) 374 - #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 375 - #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) 376 - #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 377 - #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) 378 - #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 379 - #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) 380 - #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 381 - #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) 382 - #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 383 - #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) 384 - #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 385 - #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) 386 - #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 387 - #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) 388 - #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 389 - #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) 390 - #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 391 - #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) 392 - #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 393 - #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) 394 - #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 395 - #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) 396 - #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 397 - #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) 398 - #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 399 - #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) 400 - #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 401 - #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) 402 - #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 403 - #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) 404 - #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 405 - #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) 406 - #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 407 - #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) 408 - #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 409 - #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) 410 - #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 411 - #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) 412 - #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 413 - #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) 414 - #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 415 - #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) 416 - #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 417 - #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) 418 - #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 419 - #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) 420 - #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 421 - #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) 422 - #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 423 - #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) 424 - #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 425 - #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) 426 - #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 427 - #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) 428 - #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 429 - #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) 430 - #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 431 - #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) 432 - #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 433 - #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) 434 - #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 435 - #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) 436 - #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 437 - #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) 438 - #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 439 - #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) 440 - 441 - /* CM2.CEFUSE_CM2 register offsets */ 442 - #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 443 - #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) 444 - #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 445 - #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 446 64 447 65 #endif
-325
arch/arm/mach-omap2/cm2_54xx.h
··· 35 35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500 36 36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 37 37 #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 38 - #define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 39 - #define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 40 38 41 39 /* CM_CORE clockdomain register offsets (from instance start) */ 42 40 #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 ··· 55 57 #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 56 58 #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 57 59 #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 58 - 59 - /* CM_CORE */ 60 - 61 - /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ 62 - #define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 63 - #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 64 - #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) 65 - #define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 66 - #define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 67 - 68 - /* CM_CORE.CKGEN_CM_CORE register offsets */ 69 - #define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 70 - #define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) 71 - #define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 72 - #define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) 73 - #define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 74 - #define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) 75 - #define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 76 - #define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) 77 - #define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 78 - #define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) 79 - #define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 80 - #define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) 81 - #define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 82 - #define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) 83 - #define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 84 - #define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) 85 - #define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c 86 - #define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) 87 - #define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 88 - #define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) 89 - #define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 90 - #define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) 91 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 92 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 93 - #define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 94 - #define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) 95 - #define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 96 - #define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) 97 - #define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 98 - #define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) 99 - #define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 100 - #define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) 101 - #define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 102 - #define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) 103 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 104 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 105 - #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 106 - #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) 107 - #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 108 - #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) 109 - #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 110 - #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) 111 - #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 112 - #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) 113 - #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc 114 - #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) 115 - #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 116 - #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) 117 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 118 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec 119 - #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 120 - #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) 121 - #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 122 - #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) 123 - #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 124 - #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) 125 - #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 126 - #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) 127 - #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c 128 - #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) 129 - #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 130 - #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) 131 - #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 132 - #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c 133 - #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 134 - #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) 135 - 136 - /* CM_CORE.COREAON_CM_CORE register offsets */ 137 - #define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 138 - #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 139 - #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) 140 - #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 141 - #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) 142 - #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 143 - #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) 144 - #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 145 - #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) 146 - #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 147 - #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) 148 - 149 - /* CM_CORE.CORE_CM_CORE register offsets */ 150 - #define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 151 - #define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 152 - #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 153 - #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) 154 - #define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 155 - #define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 156 - #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 157 - #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) 158 - #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 159 - #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) 160 - #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 161 - #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) 162 - #define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 163 - #define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 164 - #define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 165 - #define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 166 - #define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) 167 - #define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 168 - #define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 169 - #define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 170 - #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 171 - #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) 172 - #define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 173 - #define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 174 - #define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) 175 - #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 176 - #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) 177 - #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 178 - #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) 179 - #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 180 - #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) 181 - #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 182 - #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) 183 - #define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 184 - #define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 185 - #define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 186 - #define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 187 - #define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) 188 - #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 189 - #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) 190 - #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 191 - #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) 192 - #define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 193 - #define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 194 - #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 195 - #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) 196 - #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 197 - #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) 198 - #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 199 - #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) 200 - #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 201 - #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) 202 - #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 203 - #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) 204 - #define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 205 - #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 206 - #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) 207 - #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 208 - #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) 209 - #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 210 - #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) 211 - #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 212 - #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) 213 - #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 214 - #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) 215 - #define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 216 - #define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 217 - #define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 218 - #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 219 - #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) 220 - #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 221 - #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) 222 - #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 223 - #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) 224 - #define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 225 - #define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 226 - #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 227 - #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) 228 - #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 229 - #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) 230 - #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 231 - #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) 232 - #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 233 - #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) 234 - #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 235 - #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) 236 - #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 237 - #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) 238 - #define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 239 - #define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) 240 - #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 241 - #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) 242 - #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 243 - #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) 244 - #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 245 - #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) 246 - #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 247 - #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) 248 - #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 249 - #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) 250 - #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 251 - #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) 252 - #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 253 - #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) 254 - #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 255 - #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) 256 - #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 257 - #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) 258 - #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 259 - #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) 260 - #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 261 - #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) 262 - #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 263 - #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) 264 - #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 265 - #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) 266 - #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 267 - #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) 268 - #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 269 - #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) 270 - #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 271 - #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) 272 - #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 273 - #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) 274 - #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 275 - #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) 276 - #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 277 - #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) 278 - #define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 279 - #define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) 280 - #define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 281 - #define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) 282 - #define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 283 - #define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) 284 - #define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 285 - #define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) 286 - #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 287 - #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) 288 - #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 289 - #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) 290 - #define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 291 - #define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) 292 - #define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 293 - #define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) 294 - #define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 295 - #define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 296 - #define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 297 - #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 298 - #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) 299 - #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 300 - #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) 301 - #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 302 - #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) 303 - #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 304 - #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) 305 - #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 306 - #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) 307 - #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 308 - #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) 309 - #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 310 - #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) 311 - 312 - /* CM_CORE.IVA_CM_CORE register offsets */ 313 - #define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 314 - #define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 315 - #define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 316 - #define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 317 - #define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) 318 - #define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 319 - #define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) 320 - 321 - /* CM_CORE.CAM_CM_CORE register offsets */ 322 - #define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 323 - #define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 324 - #define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 325 - #define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 326 - #define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) 327 - #define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 328 - #define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) 329 - #define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 330 - #define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) 331 - 332 - /* CM_CORE.DSS_CM_CORE register offsets */ 333 - #define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 334 - #define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 335 - #define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 336 - #define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 337 - #define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) 338 - #define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 339 - #define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) 340 - 341 - /* CM_CORE.GPU_CM_CORE register offsets */ 342 - #define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 343 - #define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 344 - #define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 345 - #define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 346 - #define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) 347 - 348 - /* CM_CORE.L3INIT_CM_CORE register offsets */ 349 - #define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 350 - #define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 351 - #define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 352 - #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 353 - #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) 354 - #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 355 - #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) 356 - #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 357 - #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) 358 - #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 359 - #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) 360 - #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 361 - #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) 362 - #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 363 - #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) 364 - #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 365 - #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) 366 - #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 367 - #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) 368 - #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 369 - #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) 370 - #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 371 - #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) 372 - #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 373 - #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) 374 - #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 375 - #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) 376 - 377 - /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ 378 - #define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 379 - #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 380 - #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) 381 60 382 61 #endif
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arch/arm/mach-omap2/cm2_7xx.h
··· 37 37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 38 38 #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 39 39 #define DRA7XX_CM_CORE_L4PER_INST 0x1700 40 - #define DRA7XX_CM_CORE_RESTORE_INST 0x1e18 41 40 42 41 /* CM_CORE clockdomain register offsets (from instance start) */ 43 42 #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 ··· 59 60 #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 60 61 #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc 61 62 #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 62 - 63 - /* CM_CORE */ 64 - 65 - /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ 66 - #define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000 67 - #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 68 - #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) 69 - #define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0 70 - 71 - /* CM_CORE.CKGEN_CM_CORE register offsets */ 72 - #define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000 73 - #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) 74 - #define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c 75 - #define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) 76 - #define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040 77 - #define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) 78 - #define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044 79 - #define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) 80 - #define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048 81 - #define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) 82 - #define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c 83 - #define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) 84 - #define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050 85 - #define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) 86 - #define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054 87 - #define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) 88 - #define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058 89 - #define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) 90 - #define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c 91 - #define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) 92 - #define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060 93 - #define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) 94 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064 95 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068 96 - #define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c 97 - #define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) 98 - #define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080 99 - #define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) 100 - #define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084 101 - #define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) 102 - #define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088 103 - #define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) 104 - #define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c 105 - #define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) 106 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4 107 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8 108 - #define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0 109 - #define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) 110 - #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc 111 - #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) 112 - #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100 113 - #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) 114 - #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104 115 - #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) 116 - #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108 117 - #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) 118 - #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c 119 - #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) 120 - #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110 121 - #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114 122 - #define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118 123 - #define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) 124 - #define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c 125 - #define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) 126 - #define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120 127 - #define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) 128 - #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124 129 - #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) 130 - 131 - /* CM_CORE.COREAON_CM_CORE register offsets */ 132 - #define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 133 - #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 134 - #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) 135 - #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 136 - #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) 137 - #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040 138 - #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) 139 - #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 140 - #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) 141 - #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058 142 - #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) 143 - #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068 144 - #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) 145 - #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078 146 - #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) 147 - #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088 148 - #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) 149 - #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098 150 - #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) 151 - #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0 152 - #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) 153 - #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0 154 - #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) 155 - #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0 156 - #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) 157 - #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0 158 - #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) 159 - 160 - /* CM_CORE.CORE_CM_CORE register offsets */ 161 - #define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 162 - #define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 163 - #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 164 - #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) 165 - #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028 166 - #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) 167 - #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030 168 - #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) 169 - #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050 170 - #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) 171 - #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058 172 - #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) 173 - #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060 174 - #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) 175 - #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068 176 - #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) 177 - #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070 178 - #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) 179 - #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078 180 - #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) 181 - #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080 182 - #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) 183 - #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088 184 - #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) 185 - #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090 186 - #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) 187 - #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098 188 - #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) 189 - #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0 190 - #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) 191 - #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8 192 - #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) 193 - #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0 194 - #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) 195 - #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8 196 - #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) 197 - #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0 198 - #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) 199 - #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8 200 - #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) 201 - #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0 202 - #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) 203 - #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8 204 - #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) 205 - #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0 206 - #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) 207 - #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8 208 - #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) 209 - #define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200 210 - #define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204 211 - #define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208 212 - #define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220 213 - #define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) 214 - #define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 215 - #define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304 216 - #define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 217 - #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 218 - #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) 219 - #define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 220 - #define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 221 - #define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) 222 - #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 223 - #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) 224 - #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 225 - #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) 226 - #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 227 - #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) 228 - #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 229 - #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) 230 - #define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500 231 - #define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) 232 - #define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520 233 - #define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 234 - #define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 235 - #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 236 - #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) 237 - #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 238 - #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) 239 - #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630 240 - #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) 241 - #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 242 - #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) 243 - #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 244 - #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) 245 - #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648 246 - #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) 247 - #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650 248 - #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) 249 - #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658 250 - #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) 251 - #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660 252 - #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) 253 - #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668 254 - #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) 255 - #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670 256 - #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) 257 - #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678 258 - #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) 259 - #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680 260 - #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) 261 - #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688 262 - #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) 263 - #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690 264 - #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) 265 - #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698 266 - #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) 267 - #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0 268 - #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) 269 - #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8 270 - #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) 271 - #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0 272 - #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) 273 - #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8 274 - #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) 275 - #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0 276 - #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) 277 - #define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 278 - #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720 279 - #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) 280 - #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 281 - #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) 282 - #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 283 - #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) 284 - #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 285 - #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) 286 - #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 287 - #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) 288 - 289 - /* CM_CORE.IVA_CM_CORE register offsets */ 290 - #define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 291 - #define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004 292 - #define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 293 - #define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 294 - #define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) 295 - #define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 296 - #define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) 297 - 298 - /* CM_CORE.CAM_CM_CORE register offsets */ 299 - #define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 300 - #define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004 301 - #define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020 302 - #define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) 303 - #define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028 304 - #define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) 305 - #define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030 306 - #define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) 307 - #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038 308 - #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) 309 - #define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040 310 - #define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) 311 - #define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048 312 - #define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) 313 - 314 - /* CM_CORE.DSS_CM_CORE register offsets */ 315 - #define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 316 - #define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004 317 - #define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 318 - #define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 319 - #define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) 320 - #define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 321 - #define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) 322 - #define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c 323 - #define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) 324 - 325 - /* CM_CORE.GPU_CM_CORE register offsets */ 326 - #define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 327 - #define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004 328 - #define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 329 - #define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 330 - #define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) 331 - 332 - /* CM_CORE.L3INIT_CM_CORE register offsets */ 333 - #define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 334 - #define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 335 - #define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 336 - #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 337 - #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) 338 - #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 339 - #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) 340 - #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040 341 - #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) 342 - #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048 343 - #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) 344 - #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050 345 - #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) 346 - #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058 347 - #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) 348 - #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 349 - #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) 350 - #define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 351 - #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) 352 - #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 353 - #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 354 - #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0 355 - #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) 356 - #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8 357 - #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) 358 - #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 359 - #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 360 - #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 361 - #define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0 362 - #define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) 363 - #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 364 - #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) 365 - #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 366 - #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) 367 - #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0 368 - #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) 369 - 370 - /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ 371 - #define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 372 - #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 373 - #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) 374 - 375 - /* CM_CORE.L4PER_CM_CORE register offsets */ 376 - #define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 377 - #define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 378 - #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c 379 - #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) 380 - #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014 381 - #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) 382 - #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018 383 - #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) 384 - #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020 385 - #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) 386 - #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028 387 - #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) 388 - #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030 389 - #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) 390 - #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038 391 - #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) 392 - #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040 393 - #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) 394 - #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048 395 - #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) 396 - #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050 397 - #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) 398 - #define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 399 - #define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) 400 - #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 401 - #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) 402 - #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 403 - #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) 404 - #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 405 - #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) 406 - #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 407 - #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) 408 - #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 409 - #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) 410 - #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 411 - #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) 412 - #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090 413 - #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) 414 - #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098 415 - #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) 416 - #define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 417 - #define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) 418 - #define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 419 - #define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) 420 - #define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 421 - #define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) 422 - #define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 423 - #define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) 424 - #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0 425 - #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) 426 - #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4 427 - #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) 428 - #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8 429 - #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) 430 - #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0 431 - #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) 432 - #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8 433 - #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) 434 - #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 435 - #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) 436 - #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 437 - #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) 438 - #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 439 - #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) 440 - #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 441 - #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) 442 - #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110 443 - #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) 444 - #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118 445 - #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) 446 - #define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120 447 - #define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) 448 - #define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128 449 - #define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) 450 - #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130 451 - #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) 452 - #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138 453 - #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) 454 - #define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 455 - #define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) 456 - #define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 457 - #define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) 458 - #define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 459 - #define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) 460 - #define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 461 - #define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) 462 - #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160 463 - #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) 464 - #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168 465 - #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) 466 - #define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170 467 - #define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) 468 - #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178 469 - #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) 470 - #define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 471 - #define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184 472 - #define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 473 - #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190 474 - #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) 475 - #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198 476 - #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) 477 - #define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 478 - #define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) 479 - #define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 480 - #define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) 481 - #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 482 - #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) 483 - #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8 484 - #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) 485 - #define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 486 - #define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) 487 - #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 488 - #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) 489 - #define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0 490 - #define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) 491 - #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8 492 - #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) 493 - #define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0 494 - #define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) 495 - #define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8 496 - #define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) 497 - #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0 498 - #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) 499 - #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8 500 - #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) 501 - #define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc 502 - #define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200 503 - #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204 504 - #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) 505 - #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208 506 - #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208) 507 - #define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c 508 - #define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210 509 - #define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214 510 63 511 64 #endif
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arch/arm/mach-omap2/cm33xx.h
··· 37 37 #define AM33XX_CM_GFX_MOD 0x0900 38 38 #define AM33XX_CM_CEFUSE_MOD 0x0A00 39 39 40 - /* CM */ 41 - 42 40 /* CM.PER_CM register offsets */ 43 41 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 44 42 #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) ··· 46 48 #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) 47 49 #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c 48 50 #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) 49 - #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 50 - #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) 51 - #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 52 - #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) 53 - #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c 54 - #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) 55 - #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 56 - #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) 57 - #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 58 - #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) 59 51 #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 60 52 #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) 61 - #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c 62 - #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) 63 - #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 64 - #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) 65 - #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 66 - #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) 67 - #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 68 - #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) 69 - #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c 70 - #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) 71 - #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 72 - #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) 73 - #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 74 - #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) 75 - #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 76 - #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) 77 - #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c 78 - #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) 79 - #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 80 - #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) 81 - #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 82 - #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) 83 - #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 84 - #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) 85 - #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 86 - #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) 87 - #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 88 - #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) 89 - #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 90 - #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) 91 - #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c 92 - #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) 93 - #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 94 - #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) 95 - #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 96 - #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) 97 - #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 98 - #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) 99 - #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c 100 - #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) 101 - #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 102 - #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) 103 - #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 104 - #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) 105 - #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 106 - #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) 107 - #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c 108 - #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) 109 - #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 110 - #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) 111 - #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 112 - #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) 113 - #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 114 - #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) 115 - #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c 116 - #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) 117 - #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 118 - #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) 119 - #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 120 - #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) 121 - #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 122 - #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) 123 - #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac 124 - #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) 125 - #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 126 - #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) 127 - #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 128 - #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) 129 - #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 130 - #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) 131 - #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc 132 - #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) 133 - #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 134 - #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) 135 - #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 136 - #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) 137 - #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc 138 - #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) 139 - #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 140 - #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) 141 - #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 142 - #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) 143 - #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 144 - #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) 145 - #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc 146 - #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) 147 - #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 148 - #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) 149 - #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 150 - #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) 151 - #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 152 - #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) 153 - #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec 154 - #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) 155 - #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 156 - #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) 157 - #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 158 - #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) 159 - #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 160 - #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) 161 - #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc 162 - #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) 163 - #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 164 - #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) 165 - #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 166 - #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) 167 - #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c 168 - #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) 169 - #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 170 - #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) 171 53 #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c 172 54 #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) 173 - #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 174 - #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) 175 - #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 176 - #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) 177 - #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 178 - #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) 179 55 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c 180 56 #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) 181 - #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 182 - #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) 183 - #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 184 - #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) 185 57 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 186 58 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) 187 59 #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 188 60 #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) 189 61 #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 190 62 #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) 191 - #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c 192 - #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) 193 63 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 194 64 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) 195 65 196 66 /* CM.WKUP_CM register offsets */ 197 67 #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 198 68 #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) 199 - #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 200 - #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) 201 - #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 202 - #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) 203 - #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c 204 - #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) 205 - #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 206 - #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) 207 - #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 208 - #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) 209 69 #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 210 70 #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) 211 - #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c 212 - #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) 213 - #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 214 - #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) 215 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 216 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) 217 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 218 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) 219 - #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c 220 - #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) 221 - #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 222 - #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) 223 - #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 224 - #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) 225 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 226 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) 227 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c 228 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) 229 - #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 230 - #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) 231 - #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 232 - #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) 233 - #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 234 - #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) 235 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c 236 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) 237 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 238 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) 239 - #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 240 - #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) 241 - #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 242 - #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) 243 - #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c 244 - #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) 245 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 246 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) 247 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 248 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) 249 - #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 250 - #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) 251 - #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c 252 - #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) 253 - #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 254 - #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) 255 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 256 - #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) 257 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 258 - #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) 259 - #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c 260 - #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) 261 - #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 262 - #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) 263 - #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 264 - #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) 265 - #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 266 - #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) 267 - #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c 268 - #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) 269 - #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 270 - #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) 271 - #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 272 - #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) 273 - #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 274 - #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) 275 - #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c 276 - #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) 277 - #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 278 - #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) 279 - #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 280 - #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) 281 - #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 282 - #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) 283 - #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac 284 - #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) 285 - #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 286 - #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) 287 - #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 288 - #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) 289 - #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 290 - #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) 291 - #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc 292 - #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) 293 - #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 294 - #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) 295 - #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 296 - #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) 297 - #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 298 - #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) 299 71 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc 300 72 #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) 301 - #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 302 - #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) 303 - #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 304 - #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) 305 - #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 306 - #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) 307 73 308 74 /* CM.DPLL_CM register offsets */ 309 - #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 310 - #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) 311 - #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 312 - #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) 313 - #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c 314 - #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) 315 - #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 316 - #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) 317 - #define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 318 - #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) 319 - #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 320 - #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) 321 - #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c 322 - #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) 323 - #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 324 - #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) 325 - #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 326 - #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) 327 - #define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c 328 75 #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) 329 - #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 330 - #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) 331 - #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 332 - #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) 333 - #define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 334 - #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) 335 - #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c 336 - #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) 337 76 338 77 /* CM.MPU_CM register offsets */ 339 78 #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 340 79 #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) 341 - #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 342 80 #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) 343 81 344 82 /* CM.DEVICE_CM register offsets */ 345 - #define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 346 - #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) 347 83 348 84 /* CM.RTC_CM register offsets */ 349 - #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 350 - #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) 351 85 #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 352 86 #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) 353 87 354 88 /* CM.GFX_CM register offsets */ 355 89 #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 356 90 #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) 357 - #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 358 - #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) 359 - #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 360 - #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) 361 91 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c 362 92 #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) 363 - #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 364 - #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) 365 - #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 366 - #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) 367 93 368 94 /* CM.CEFUSE_CM register offsets */ 369 95 #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 370 96 #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) 371 - #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 372 - #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) 373 97 374 98 375 99 #ifndef __ASSEMBLER__
+3 -3
arch/arm/mach-omap2/omap_hwmod.c
··· 812 812 } 813 813 814 814 /** 815 - * _init_main_clk - get a struct clk * for the the hwmod's main functional clk 815 + * _init_main_clk - get a struct clk * for the hwmod's main functional clk 816 816 * @oh: struct omap_hwmod * 817 817 * 818 818 * Called from _init_clocks(). Populates the @oh _clk (main ··· 862 862 } 863 863 864 864 /** 865 - * _init_interface_clks - get a struct clk * for the the hwmod's interface clks 865 + * _init_interface_clks - get a struct clk * for the hwmod's interface clks 866 866 * @oh: struct omap_hwmod * 867 867 * 868 868 * Called from _init_clocks(). Populates the @oh OCP slave interface ··· 901 901 } 902 902 903 903 /** 904 - * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks 904 + * _init_opt_clk - get a struct clk * for the hwmod's optional clocks 905 905 * @oh: struct omap_hwmod * 906 906 * 907 907 * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
-36
arch/arm/mach-omap2/pdata-quirks.c
··· 274 274 } 275 275 #endif /* CONFIG_ARCH_OMAP3 */ 276 276 277 - #ifdef CONFIG_SOC_OMAP5 278 - static void __init omap5_uevm_legacy_init(void) 279 - { 280 - } 281 - #endif 282 - 283 277 #ifdef CONFIG_SOC_DRA7XX 284 278 static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = { 285 279 .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint, 286 280 }; 287 - 288 - static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; 289 - static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; 290 - static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; 291 - 292 - static void __init dra7x_evm_mmc_quirk(void) 293 - { 294 - if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) { 295 - dra7_hsmmc_data_mmc1.version = "rev11"; 296 - dra7_hsmmc_data_mmc1.max_freq = 96000000; 297 - 298 - dra7_hsmmc_data_mmc2.version = "rev11"; 299 - dra7_hsmmc_data_mmc2.max_freq = 48000000; 300 - 301 - dra7_hsmmc_data_mmc3.version = "rev11"; 302 - dra7_hsmmc_data_mmc3.max_freq = 48000000; 303 - } 304 - } 305 281 #endif 306 282 307 283 static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk) ··· 484 508 "4a0d9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]), 485 509 #endif 486 510 #ifdef CONFIG_SOC_DRA7XX 487 - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc", 488 - &dra7_hsmmc_data_mmc1), 489 - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc", 490 - &dra7_hsmmc_data_mmc2), 491 - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", 492 - &dra7_hsmmc_data_mmc3), 493 511 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", 494 512 &dra7_ipu1_dsp_iommu_pdata), 495 513 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", ··· 518 548 { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, }, 519 549 { "openpandora,omap3-pandora-600mhz", omap3_pandora_legacy_init, }, 520 550 { "openpandora,omap3-pandora-1ghz", omap3_pandora_legacy_init, }, 521 - #endif 522 - #ifdef CONFIG_SOC_OMAP5 523 - { "ti,omap5-uevm", omap5_uevm_legacy_init, }, 524 - #endif 525 - #ifdef CONFIG_SOC_DRA7XX 526 - { "ti,dra7-evm", dra7x_evm_mmc_quirk, }, 527 551 #endif 528 552 { /* sentinel */ }, 529 553 };
+3 -3
arch/arm/mach-omap2/powerdomain.c
··· 626 626 * powerdomain @pwrdm will enter when the powerdomain enters retention. 627 627 * This will be either RETENTION or OFF, if supported. Returns 628 628 * -EINVAL if the powerdomain pointer is null or the target power 629 - * state is not not supported, or returns 0 upon success. 629 + * state is not supported, or returns 0 upon success. 630 630 */ 631 631 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 632 632 { ··· 658 658 * state. @bank will be a number from 0 to 3, and represents different 659 659 * types of memory, depending on the powerdomain. Returns -EINVAL if 660 660 * the powerdomain pointer is null or the target power state is not 661 - * not supported for this memory bank, -EEXIST if the target memory 661 + * supported for this memory bank, -EEXIST if the target memory 662 662 * bank does not exist or is not controllable, or returns 0 upon 663 663 * success. 664 664 */ ··· 696 696 * different types of memory, depending on the powerdomain. @pwrst 697 697 * will be either RETENTION or OFF, if supported. Returns -EINVAL if 698 698 * the powerdomain pointer is null or the target power state is not 699 - * not supported for this memory bank, -EEXIST if the target memory 699 + * supported for this memory bank, -EEXIST if the target memory 700 700 * bank does not exist or is not controllable, or returns 0 upon 701 701 * success. 702 702 */
-94
arch/arm/mach-omap2/prcm43xx.h
··· 32 32 /* Other PRM offsets */ 33 33 #define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024 34 34 35 - /* RM RSTCTRL offsets */ 36 - #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 37 - #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 38 - #define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 39 - 40 - /* RM RSTST offsets */ 41 - #define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 42 - #define AM43XX_RM_PER_RSTST_OFFSET 0x0014 43 - #define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 44 - 45 35 /* CM instances */ 46 36 #define AM43XX_CM_WKUP_INST 0x2800 47 - #define AM43XX_CM_DEVICE_INST 0x4100 48 - #define AM43XX_CM_DPLL_INST 0x4200 49 37 #define AM43XX_CM_MPU_INST 0x8300 50 38 #define AM43XX_CM_GFX_INST 0x8400 51 39 #define AM43XX_CM_RTC_INST 0x8500 ··· 62 74 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 63 75 64 76 /* CLK CTRL offsets */ 65 - #define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 66 - #define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 67 - #define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 68 - #define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 69 - #define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 70 - #define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 71 - #define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 72 - #define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 73 - #define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 74 - #define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 75 - #define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 76 - #define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 77 - #define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 78 - #define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 79 - #define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 80 - #define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 81 - #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 82 - #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 83 - #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 84 - #define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0 85 - #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 86 - #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 87 - #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 88 - #define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 89 - #define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 90 - #define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 91 - #define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 92 - #define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 93 - #define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 94 - #define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 95 - #define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 96 - #define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 97 - #define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 98 - #define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 99 - #define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 100 - #define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 101 - #define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 102 - #define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 103 - #define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 104 - #define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 105 - #define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 106 - #define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 107 - #define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 108 - #define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 109 - #define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 110 - #define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 111 - #define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 112 - #define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 113 - #define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 114 - #define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 115 - #define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 116 - #define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 117 - #define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 118 - #define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 119 - #define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 120 - #define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 121 77 #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 122 - #define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 123 - #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 124 - #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 125 - #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 126 - #define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030 127 - #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 128 - #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 129 - #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 130 - #define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 131 - #define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 132 - #define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 133 - #define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 134 - #define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 135 - #define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 136 - #define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 137 - #define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 138 - #define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 139 - #define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 140 - #define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 141 - #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 142 - #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 143 - #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 144 - #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 145 - #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 146 - #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068 147 - #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070 148 78 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 149 79 150 80 #endif
-40
arch/arm/mach-omap2/prm33xx.h
··· 35 35 #define AM33XX_PRM_GFX_MOD 0x1100 36 36 #define AM33XX_PRM_CEFUSE_MOD 0x1200 37 37 38 - /* PRM */ 39 - 40 - /* PRM.OCP_SOCKET_PRM register offsets */ 41 - #define AM33XX_REVISION_PRM_OFFSET 0x0000 42 - #define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) 43 - #define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 44 - #define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) 45 - #define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 46 - #define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) 47 - #define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c 48 - #define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) 49 - #define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 50 - #define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) 51 - 52 38 /* PRM.PER_PRM register offsets */ 53 - #define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 54 - #define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) 55 39 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 56 40 #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) 57 41 #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c 58 42 #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) 59 43 60 44 /* PRM.WKUP_PRM register offsets */ 61 - #define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 62 - #define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) 63 45 #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 64 46 #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) 65 47 #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 66 48 #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) 67 - #define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c 68 - #define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) 69 49 70 50 /* PRM.MPU_PRM register offsets */ 71 51 #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 72 52 #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) 73 53 #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 74 54 #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) 75 - #define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 76 - #define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) 77 55 78 56 /* PRM.DEVICE_PRM register offsets */ 79 57 #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 80 58 #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) 81 - #define AM33XX_PRM_RSTTIME_OFFSET 0x0004 82 - #define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) 83 - #define AM33XX_PRM_RSTST_OFFSET 0x0008 84 - #define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) 85 - #define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c 86 - #define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) 87 - #define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 88 - #define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) 89 - #define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 90 - #define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) 91 - #define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 92 - #define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) 93 - #define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c 94 - #define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) 95 59 96 60 /* PRM.RTC_PRM register offsets */ 97 61 #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 ··· 66 102 /* PRM.GFX_PRM register offsets */ 67 103 #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 68 104 #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) 69 - #define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 70 - #define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) 71 105 #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 72 106 #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) 73 - #define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 74 - #define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) 75 107 76 108 /* PRM.CEFUSE_PRM register offsets */ 77 109 #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
-630
arch/arm/mach-omap2/prm44xx.h
··· 51 51 #define OMAP4430_PRM_EMU_INST 0x1900 52 52 #define OMAP4430_PRM_EMU_CM_INST 0x1a00 53 53 #define OMAP4430_PRM_DEVICE_INST 0x1b00 54 - #define OMAP4430_PRM_INSTR_INST 0x1f00 55 54 56 55 /* PRM clockdomain register offsets (from instance start) */ 57 56 #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 58 57 #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 59 58 60 59 /* OMAP4 specific register offsets */ 61 - #define OMAP4_RM_RSTCTRL 0x0000 62 60 #define OMAP4_RM_RSTST 0x0004 63 - #define OMAP4_RM_RSTTIME 0x0008 64 61 #define OMAP4_PM_PWSTCTRL 0x0000 65 62 #define OMAP4_PM_PWSTST 0x0004 66 63 67 - 68 - /* PRM */ 69 - 70 64 /* PRM.OCP_SOCKET_PRM register offsets */ 71 65 #define OMAP4_REVISION_PRM_OFFSET 0x0000 72 - #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000) 73 66 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 74 67 #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) 75 68 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 76 - #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014) 77 69 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 78 70 #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) 79 - #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 80 - #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c) 81 - #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 82 - #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020) 83 - #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 84 - #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028) 85 - #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 86 - #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030) 87 - #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 88 - #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038) 89 - #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 90 - #define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040) 91 - 92 - /* PRM.CKGEN_PRM register offsets */ 93 - #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 94 - #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000) 95 - #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 96 - #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008) 97 - #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c 98 - #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c) 99 - #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 100 - #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010) 101 71 102 72 /* PRM.MPU_PRM register offsets */ 103 - #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 104 - #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000) 105 - #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 106 - #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004) 107 - #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 108 - #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014) 109 73 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 110 - #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024) 111 - 112 - /* PRM.TESLA_PRM register offsets */ 113 - #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 114 - #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000) 115 - #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 116 - #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004) 117 - #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 118 - #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010) 119 - #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 120 - #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014) 121 - #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 122 - #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024) 123 - 124 - /* PRM.ABE_PRM register offsets */ 125 - #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 126 - #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000) 127 - #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 128 - #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004) 129 - #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 130 - #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c) 131 - #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 132 - #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030) 133 - #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 134 - #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034) 135 - #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 136 - #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038) 137 - #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 138 - #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c) 139 - #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 140 - #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040) 141 - #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 142 - #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044) 143 - #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 144 - #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048) 145 - #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 146 - #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c) 147 - #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 148 - #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050) 149 - #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 150 - #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054) 151 - #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 152 - #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058) 153 - #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 154 - #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c) 155 - #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 156 - #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060) 157 - #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 158 - #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064) 159 - #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 160 - #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068) 161 - #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 162 - #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c) 163 - #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 164 - #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070) 165 - #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 166 - #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074) 167 - #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 168 - #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078) 169 - #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 170 - #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c) 171 - #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 172 - #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080) 173 - #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 174 - #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084) 175 - #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 176 - #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088) 177 - #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c 178 - #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c) 179 - 180 - /* PRM.ALWAYS_ON_PRM register offsets */ 181 - #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 182 - #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024) 183 - #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 184 - #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028) 185 - #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c 186 - #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c) 187 - #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 188 - #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030) 189 - #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 190 - #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034) 191 - #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 192 - #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038) 193 - #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c 194 - #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c) 195 - 196 - /* PRM.CORE_PRM register offsets */ 197 - #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 198 - #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000) 199 - #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 200 - #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004) 201 - #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 202 - #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024) 203 - #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 204 - #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124) 205 - #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c 206 - #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c) 207 - #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 208 - #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134) 209 - #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 210 - #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210) 211 - #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 212 - #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214) 213 - #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 214 - #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224) 215 - #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 216 - #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324) 217 - #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 218 - #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424) 219 - #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c 220 - #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c) 221 - #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 222 - #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434) 223 - #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c 224 - #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c) 225 - #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 226 - #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444) 227 - #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 228 - #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454) 229 - #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c 230 - #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c) 231 - #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 232 - #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) 233 - #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 234 - #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) 235 - #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c 236 - #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) 237 - #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 238 - #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) 239 - #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 240 - #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624) 241 - #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c 242 - #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c) 243 - #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 244 - #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634) 245 - #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 246 - #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c) 247 - #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 248 - #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724) 249 - #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 250 - #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c) 251 - #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 252 - #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744) 253 - 254 - /* PRM.IVAHD_PRM register offsets */ 255 - #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 256 - #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000) 257 - #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 258 - #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004) 259 - #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 260 - #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010) 261 - #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 262 - #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014) 263 - #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 264 - #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024) 265 - #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c 266 - #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c) 267 - 268 - /* PRM.CAM_PRM register offsets */ 269 - #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 270 - #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000) 271 - #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 272 - #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004) 273 - #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 274 - #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024) 275 - #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 276 - #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c) 277 - 278 - /* PRM.DSS_PRM register offsets */ 279 - #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 280 - #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000) 281 - #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 282 - #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004) 283 - #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 284 - #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020) 285 - #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 286 - #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024) 287 - #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c 288 - #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c) 289 - 290 - /* PRM.GFX_PRM register offsets */ 291 - #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 292 - #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000) 293 - #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 294 - #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004) 295 - #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 296 - #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024) 297 - 298 - /* PRM.L3INIT_PRM register offsets */ 299 - #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 300 - #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000) 301 - #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 302 - #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004) 303 - #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 304 - #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028) 305 - #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 306 - #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c) 307 - #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 308 - #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030) 309 - #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 310 - #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034) 311 - #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 312 - #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038) 313 - #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 314 - #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c) 315 - #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 316 - #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040) 317 - #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 318 - #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044) 319 - #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 320 - #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058) 321 - #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c 322 - #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c) 323 - #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 324 - #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060) 325 - #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 326 - #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064) 327 - #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 328 - #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068) 329 - #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c 330 - #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c) 331 - #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c 332 - #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c) 333 - #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 334 - #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084) 335 - #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 336 - #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088) 337 - #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 338 - #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c) 339 - #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 340 - #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094) 341 - #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 342 - #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098) 343 - #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c 344 - #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c) 345 - #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac 346 - #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac) 347 - #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 348 - #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0) 349 - #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 350 - #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4) 351 - #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 352 - #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8) 353 - #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc 354 - #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc) 355 - #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 356 - #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0) 357 - #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 358 - #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4) 359 - #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 360 - #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4) 361 - 362 - /* PRM.L4PER_PRM register offsets */ 363 - #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 364 - #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000) 365 - #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 366 - #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004) 367 - #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 368 - #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024) 369 - #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 370 - #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028) 371 - #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c 372 - #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c) 373 - #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 374 - #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030) 375 - #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 376 - #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034) 377 - #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 378 - #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038) 379 - #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c 380 - #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c) 381 - #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 382 - #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040) 383 - #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 384 - #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044) 385 - #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 386 - #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048) 387 - #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c 388 - #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c) 389 - #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 390 - #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050) 391 - #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 392 - #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054) 393 - #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 394 - #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c) 395 - #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 396 - #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060) 397 - #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 398 - #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064) 399 - #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 400 - #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068) 401 - #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 402 - #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c) 403 - #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 404 - #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070) 405 - #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 406 - #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074) 407 - #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 408 - #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078) 409 - #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 410 - #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c) 411 - #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 412 - #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080) 413 - #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 414 - #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084) 415 - #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 416 - #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c) 417 - #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 418 - #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090) 419 - #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 420 - #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094) 421 - #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 422 - #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098) 423 - #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c 424 - #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c) 425 - #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 426 - #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0) 427 - #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 428 - #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4) 429 - #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 430 - #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8) 431 - #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 432 - #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac) 433 - #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 434 - #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0) 435 - #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 436 - #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4) 437 - #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 438 - #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8) 439 - #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 440 - #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc) 441 - #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 442 - #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0) 443 - #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 444 - #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0) 445 - #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 446 - #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4) 447 - #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 448 - #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8) 449 - #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc 450 - #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc) 451 - #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 452 - #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0) 453 - #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 454 - #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4) 455 - #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec 456 - #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec) 457 - #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 458 - #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0) 459 - #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 460 - #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4) 461 - #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 462 - #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8) 463 - #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 464 - #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc) 465 - #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 466 - #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100) 467 - #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 468 - #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104) 469 - #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 470 - #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108) 471 - #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 472 - #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c) 473 - #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 474 - #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120) 475 - #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 476 - #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124) 477 - #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 478 - #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128) 479 - #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c 480 - #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c) 481 - #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 482 - #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134) 483 - #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 484 - #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138) 485 - #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c 486 - #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c) 487 - #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 488 - #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140) 489 - #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 490 - #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144) 491 - #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 492 - #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148) 493 - #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 494 - #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c) 495 - #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 496 - #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150) 497 - #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 498 - #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154) 499 - #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 500 - #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158) 501 - #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 502 - #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c) 503 - #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 504 - #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160) 505 - #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 506 - #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164) 507 - #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 508 - #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168) 509 - #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c 510 - #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c) 511 - #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 512 - #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4) 513 - #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 514 - #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac) 515 - #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 516 - #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4) 517 - #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc 518 - #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc) 519 - #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 520 - #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4) 521 - #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 522 - #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc) 523 - #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc 524 - #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc) 525 - 526 - /* PRM.CEFUSE_PRM register offsets */ 527 - #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 528 - #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000) 529 - #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 530 - #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004) 531 - #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 532 - #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024) 533 - 534 - /* PRM.WKUP_PRM register offsets */ 535 - #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 536 - #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024) 537 - #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c 538 - #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c) 539 - #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 540 - #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030) 541 - #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 542 - #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034) 543 - #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 544 - #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038) 545 - #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c 546 - #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c) 547 - #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 548 - #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040) 549 - #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 550 - #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044) 551 - #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 552 - #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048) 553 - #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c 554 - #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c) 555 - #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 556 - #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054) 557 - #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 558 - #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058) 559 - #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c 560 - #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c) 561 - #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 562 - #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064) 563 - #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 564 - #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078) 565 - #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c 566 - #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c) 567 - #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 568 - #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080) 569 - #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 570 - #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084) 571 - 572 - /* PRM.WKUP_CM register offsets */ 573 - #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 574 - #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000) 575 - #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 576 - #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020) 577 - #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 578 - #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028) 579 - #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 580 - #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030) 581 - #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 582 - #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038) 583 - #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 584 - #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040) 585 - #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 586 - #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048) 587 - #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 588 - #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050) 589 - #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 590 - #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058) 591 - #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 592 - #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060) 593 - #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 594 - #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078) 595 - #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 596 - #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080) 597 - #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 598 - #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088) 599 - 600 - /* PRM.EMU_PRM register offsets */ 601 - #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 602 - #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000) 603 - #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 604 - #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004) 605 - #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 606 - #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024) 607 - 608 - /* PRM.EMU_CM register offsets */ 609 - #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 610 - #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000) 611 - #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 612 - #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008) 613 - #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 614 - #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020) 615 74 616 75 /* PRM.DEVICE_PRM register offsets */ 617 76 #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 618 - #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000) 619 - #define OMAP4_PRM_RSTST_OFFSET 0x0004 620 - #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004) 621 - #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 622 - #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008) 623 - #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c 624 - #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c) 625 77 #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 626 - #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010) 627 - #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 628 - #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014) 629 - #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 630 - #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018) 631 - #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c 632 - #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c) 633 78 #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 634 - #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020) 635 - #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 636 - #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024) 637 79 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 638 - #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028) 639 80 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 640 - #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c) 641 81 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 642 - #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030) 643 82 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 644 - #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034) 645 83 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 646 - #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038) 647 84 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c 648 - #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c) 649 85 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 650 - #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040) 651 86 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 652 - #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044) 653 87 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 654 - #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048) 655 88 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 656 - #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c) 657 89 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 658 - #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050) 659 90 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 660 - #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054) 661 91 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 662 - #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058) 663 92 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c 664 - #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c) 665 93 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 666 - #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060) 667 94 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 668 - #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064) 669 95 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 670 - #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068) 671 96 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 672 - #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c) 673 97 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 674 - #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070) 675 98 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 676 - #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074) 677 99 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 678 - #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078) 679 100 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c 680 - #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c) 681 101 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 682 - #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080) 683 102 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 684 - #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084) 685 103 #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 686 - #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088) 687 104 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c 688 - #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c) 689 105 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 690 - #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090) 691 106 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 692 - #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094) 693 107 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 694 - #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098) 695 108 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c 696 - #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c) 697 109 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 698 - #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) 699 110 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 700 - #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) 701 111 #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 702 - #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) 703 112 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac 704 - #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) 705 - #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 706 - #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0) 707 - #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 708 - #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4) 709 - #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 710 - #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8) 711 - #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc 712 - #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc) 713 - #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 714 - #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0) 715 - #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 716 - #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4) 717 - #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 718 - #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8) 719 - #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc 720 - #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc) 721 - #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 722 - #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0) 723 - #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 724 - #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4) 725 - #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 726 - #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8) 727 - #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc 728 - #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc) 729 - #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 730 - #define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0) 731 - #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 732 - #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4) 733 - #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 734 - #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8) 735 - #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec 736 - #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) 737 - #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 738 - #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) 739 - #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 740 - #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) 741 - #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 742 - #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 743 113 744 114 #endif
-358
arch/arm/mach-omap2/prm54xx.h
··· 46 46 #define OMAP54XX_PRM_EMU_INST 0x1a00 47 47 #define OMAP54XX_PRM_EMU_CM_INST 0x1b00 48 48 #define OMAP54XX_PRM_DEVICE_INST 0x1c00 49 - #define OMAP54XX_PRM_INSTR_INST 0x1f00 50 49 51 50 /* PRM clockdomain register offsets (from instance start) */ 52 51 #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 53 52 #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 54 53 55 - /* PRM */ 56 - 57 - /* PRM.OCP_SOCKET_PRM register offsets */ 58 - #define OMAP54XX_REVISION_PRM_OFFSET 0x0000 59 - #define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 60 - #define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 61 - #define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 62 - #define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 63 - #define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020 64 - #define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028 65 - #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 66 - #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 67 - #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 68 - #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) 69 - #define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 70 - #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 71 - #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 72 - #define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098 73 - #define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c 74 - #define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0 75 - #define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4 76 - 77 - /* PRM.CKGEN_PRM register offsets */ 78 - #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 79 - #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) 80 - #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 81 - #define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) 82 - #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 83 - #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) 84 - #define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 85 - #define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) 86 - 87 - /* PRM.MPU_PRM register offsets */ 88 - #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 89 - #define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004 90 - #define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 91 - 92 - /* PRM.DSP_PRM register offsets */ 93 - #define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000 94 - #define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004 95 - #define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010 96 - #define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014 97 - #define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024 98 - 99 - /* PRM.ABE_PRM register offsets */ 100 - #define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000 101 - #define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004 102 - #define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 103 - #define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030 104 - #define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034 105 - #define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 106 - #define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 107 - #define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 108 - #define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 109 - #define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 110 - #define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 111 - #define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 112 - #define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 113 - #define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 114 - #define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 115 - #define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060 116 - #define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064 117 - #define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 118 - #define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 119 - #define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 120 - #define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 121 - #define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 122 - #define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 123 - #define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 124 - #define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 125 - #define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088 126 - #define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c 127 - 128 - /* PRM.COREAON_PRM register offsets */ 129 - #define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028 130 - #define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c 131 - #define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030 132 - #define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034 133 - #define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038 134 - #define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c 135 - 136 - /* PRM.CORE_PRM register offsets */ 137 - #define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 138 - #define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004 139 - #define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 140 - #define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124 141 - #define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c 142 - #define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134 143 - #define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210 144 - #define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214 145 - #define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224 146 - #define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 147 - #define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 148 - #define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 149 - #define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 150 - #define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 151 - #define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 152 - #define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524 153 - #define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c 154 - #define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534 155 - #define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 156 - #define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 157 - #define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 158 - #define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 159 - #define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 160 - #define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724 161 - #define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 162 - #define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 163 - #define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824 164 - #define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c 165 - #define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834 166 - #define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928 167 - #define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c 168 - #define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930 169 - #define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934 170 - #define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938 171 - #define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c 172 - #define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940 173 - #define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944 174 - #define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948 175 - #define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c 176 - #define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950 177 - #define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954 178 - #define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c 179 - #define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960 180 - #define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964 181 - #define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968 182 - #define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c 183 - #define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970 184 - #define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974 185 - #define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978 186 - #define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c 187 - #define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980 188 - #define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984 189 - #define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c 190 - #define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0 191 - #define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4 192 - #define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8 193 - #define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac 194 - #define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0 195 - #define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4 196 - #define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8 197 - #define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc 198 - #define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0 199 - #define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0 200 - #define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4 201 - #define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8 202 - #define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc 203 - #define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00 204 - #define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04 205 - #define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08 206 - #define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c 207 - #define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10 208 - #define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14 209 - #define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18 210 - #define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c 211 - #define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20 212 - #define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24 213 - #define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28 214 - #define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c 215 - #define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40 216 - #define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44 217 - #define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48 218 - #define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c 219 - #define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50 220 - #define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54 221 - #define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58 222 - #define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c 223 - #define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60 224 - #define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64 225 - #define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68 226 - #define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c 227 - #define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70 228 - #define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74 229 - #define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78 230 - #define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c 231 - #define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4 232 - #define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac 233 - #define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4 234 - #define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc 235 - #define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4 236 - #define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc 237 - #define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc 238 - 239 - /* PRM.IVA_PRM register offsets */ 240 - #define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 241 - #define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004 242 - #define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010 243 - #define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014 244 - #define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 245 - #define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 246 - 247 - /* PRM.CAM_PRM register offsets */ 248 - #define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 249 - #define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004 250 - #define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 251 - #define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 252 - #define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034 253 - 254 - /* PRM.DSS_PRM register offsets */ 255 - #define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 256 - #define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004 257 - #define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 258 - #define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 259 - #define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 260 - 261 - /* PRM.GPU_PRM register offsets */ 262 - #define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 263 - #define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004 264 - #define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 265 - 266 - /* PRM.L3INIT_PRM register offsets */ 267 - #define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 268 - #define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 269 - #define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 270 - #define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 271 - #define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 272 - #define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 273 - #define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 274 - #define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 275 - #define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040 276 - #define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044 277 - #define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058 278 - #define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c 279 - #define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068 280 - #define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c 281 - #define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 282 - #define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 283 - #define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 284 - #define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 285 - #define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 286 - #define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0 287 - #define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4 288 - 289 - /* PRM.CUSTEFUSE_PRM register offsets */ 290 - #define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 291 - #define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 292 - #define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 293 - 294 - /* PRM.WKUPAON_PRM register offsets */ 295 - #define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024 296 - #define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c 297 - #define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030 298 - #define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034 299 - #define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038 300 - #define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c 301 - #define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040 302 - #define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044 303 - #define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048 304 - #define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c 305 - #define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054 306 - #define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064 307 - #define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078 308 - #define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c 309 - 310 - /* PRM.WKUPAON_CM register offsets */ 311 - #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 312 - #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 313 - #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) 314 - #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 315 - #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) 316 - #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 317 - #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) 318 - #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 319 - #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) 320 - #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 321 - #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) 322 - #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 323 - #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) 324 - #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 325 - #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) 326 - #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 327 - #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) 328 - #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 329 - #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) 330 - #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 331 - #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) 332 - #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 333 - #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) 334 - 335 - /* PRM.EMU_PRM register offsets */ 336 - #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 337 - #define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004 338 - #define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 339 - 340 - /* PRM.EMU_CM register offsets */ 341 - #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 342 - #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 343 - #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 344 - #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) 345 - #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 346 - #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) 347 - 348 54 /* PRM.DEVICE_PRM register offsets */ 349 - #define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000 350 - #define OMAP54XX_PRM_RSTST_OFFSET 0x0004 351 - #define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008 352 - #define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c 353 - #define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010 354 - #define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014 355 - #define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018 356 - #define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c 357 - #define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020 358 - #define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 359 - #define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 360 - #define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 361 - #define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 362 55 #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 363 56 #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 364 57 #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 365 - #define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040 366 - #define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044 367 - #define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 368 - #define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 369 - #define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 370 - #define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 371 - #define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058 372 - #define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c 373 - #define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 374 - #define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 375 - #define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 376 - #define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 377 - #define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070 378 - #define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074 379 - #define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078 380 - #define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c 381 - #define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080 382 - #define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084 383 - #define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088 384 - #define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c 385 - #define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090 386 - #define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 387 - #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098 388 - #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c 389 - #define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 390 - #define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4 391 - #define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8 392 - #define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac 393 - #define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0 394 - #define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4 395 - #define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8 396 - #define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc 397 - #define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 398 - #define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 399 - #define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 400 - #define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 401 - #define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 402 - #define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4 403 - #define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8 404 - #define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 405 - #define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 406 - #define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4 407 - #define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8 408 - #define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 409 - #define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 410 - #define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 411 - #define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 412 - #define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 413 - #define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 414 - #define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110 415 - #define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114 416 58 417 59 #endif
-613
arch/arm/mach-omap2/prm7xx.h
··· 56 56 #define DRA7XX_PRM_RTC_INST 0x1c60 57 57 #define DRA7XX_PRM_VPE_INST 0x1c80 58 58 #define DRA7XX_PRM_DEVICE_INST 0x1d00 59 - #define DRA7XX_PRM_INSTR_INST 0x1f00 60 59 61 60 /* PRM clockdomain register offsets (from instance start) */ 62 61 #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 63 62 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 64 63 65 - /* PRM */ 66 - 67 - /* PRM.OCP_SOCKET_PRM register offsets */ 68 - #define DRA7XX_REVISION_PRM_OFFSET 0x0000 69 - #define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 70 - #define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 71 - #define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 72 - #define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 73 - #define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 74 - #define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 75 - #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 76 - #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 77 - #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 78 - #define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) 79 - #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 80 - #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 81 - #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c 82 - #define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 83 - #define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 84 - #define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 85 - #define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c 86 - #define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 87 - #define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 88 - #define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 89 - #define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c 90 - #define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 91 - #define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 92 - #define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 93 - #define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec 94 - #define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 95 - 96 64 /* PRM.CKGEN_PRM register offsets */ 97 - #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 98 - #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) 99 - #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 100 - #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) 101 - #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 102 - #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) 103 - #define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 104 65 #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 105 - #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 106 - #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) 107 - #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 108 - #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) 109 - #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c 110 - #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) 111 - #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 112 - #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) 113 - #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 114 - #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) 115 - #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 116 - #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) 117 - #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c 118 - #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) 119 - #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 120 - #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) 121 - #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 122 - #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) 123 - #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 124 - #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) 125 - #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 126 - #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) 127 - #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 128 - #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) 129 - #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 130 - #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) 131 - #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c 132 - #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) 133 - #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 134 - #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) 135 - #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 136 - #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) 137 - #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 138 - #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) 139 - #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c 140 - #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) 141 - #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 142 - #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) 143 - #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 144 - #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) 145 - #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 146 - #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) 147 - #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c 148 - #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) 149 - #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 150 - #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) 151 - #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 152 - #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) 153 - #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 154 - #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) 155 - #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 156 - #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) 157 - #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 158 - #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) 159 - #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 160 - #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) 161 - #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c 162 - #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) 163 - #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 164 - #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) 165 - #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 166 - #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) 167 - #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 168 - #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) 169 - #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c 170 - #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) 171 - #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 172 - #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) 173 - #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 174 - #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) 175 - #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 176 - #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) 177 - #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac 178 - #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) 179 - #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 180 - #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) 181 - #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 182 - #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) 183 - #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 184 - #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) 185 - #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc 186 - #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) 187 - #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 188 - #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) 189 - #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 190 - #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) 191 - #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 192 - #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) 193 - #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc 194 - #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) 195 - #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 196 - #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) 197 - #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 198 - #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) 199 - #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 200 - #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) 201 - #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc 202 - #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) 203 - #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 204 - #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) 205 - 206 - /* PRM.MPU_PRM register offsets */ 207 - #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 208 - #define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 209 - #define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 210 - 211 - /* PRM.DSP1_PRM register offsets */ 212 - #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 213 - #define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 214 - #define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 215 - #define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 216 - #define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 217 - 218 - /* PRM.IPU_PRM register offsets */ 219 - #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 220 - #define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 221 - #define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 222 - #define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 223 - #define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 224 - #define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 225 - #define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 226 - #define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 227 - #define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c 228 - #define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 229 - #define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 230 - #define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 231 - #define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c 232 - #define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 233 - #define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 234 - #define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 235 - #define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c 236 - #define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 237 - #define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 238 - 239 - /* PRM.COREAON_PRM register offsets */ 240 - #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 241 - #define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 242 - #define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 243 - #define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 244 - #define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 245 - #define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 246 - #define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 247 - #define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 248 - #define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 249 - #define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 250 - #define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 251 - #define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 252 - #define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 253 - #define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 254 - 255 - /* PRM.CORE_PRM register offsets */ 256 - #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 257 - #define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 258 - #define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 259 - #define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c 260 - #define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 261 - #define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 262 - #define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 263 - #define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 264 - #define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c 265 - #define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 266 - #define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 267 - #define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c 268 - #define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 269 - #define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 270 - #define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 271 - #define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c 272 - #define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 273 - #define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 274 - #define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c 275 - #define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 276 - #define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c 277 - #define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 278 - #define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac 279 - #define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 280 - #define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc 281 - #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 282 - #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc 283 - #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 284 - #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc 285 - #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 286 - #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc 287 - #define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 288 - #define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 289 - #define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 290 - #define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 291 - #define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 292 - #define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 293 - #define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 294 - #define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 295 - #define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 296 - #define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 297 - #define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 298 - #define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 299 - #define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 300 - #define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 301 - #define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 302 - #define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c 303 - #define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 304 - #define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c 305 - #define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 306 - #define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c 307 - #define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 308 - #define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c 309 - #define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 310 - #define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c 311 - #define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 312 - #define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c 313 - #define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 314 - #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac 315 - #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 316 - #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc 317 - #define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 318 - #define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 319 - #define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 320 - #define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 321 - 322 - /* PRM.IVA_PRM register offsets */ 323 - #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 324 - #define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 325 - #define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 326 - #define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 327 - #define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 328 - #define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 329 - 330 - /* PRM.CAM_PRM register offsets */ 331 - #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 332 - #define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 333 - #define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 334 - #define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 335 - #define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 336 - #define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c 337 - #define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 338 - #define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 339 - #define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c 340 - #define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 341 - #define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c 342 - 343 - /* PRM.DSS_PRM register offsets */ 344 - #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 345 - #define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 346 - #define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 347 - #define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 348 - #define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 349 - #define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 350 - #define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c 351 - 352 - /* PRM.GPU_PRM register offsets */ 353 - #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 354 - #define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 355 - #define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 356 - 357 - /* PRM.L3INIT_PRM register offsets */ 358 - #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 359 - #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 360 - #define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 361 - #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 362 - #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 363 - #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 364 - #define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 365 - #define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 366 - #define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 367 - #define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 368 - #define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c 369 - #define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 370 - #define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 371 - #define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c 372 - #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 373 - #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 374 - #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 375 - #define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 376 - #define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 377 - #define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 378 - #define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc 379 - #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 380 - #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 381 - #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 382 - #define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 383 - #define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 384 - 385 - /* PRM.L4PER_PRM register offsets */ 386 - #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 387 - #define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 388 - #define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c 389 - #define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 390 - #define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c 391 - #define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 392 - #define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 393 - #define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c 394 - #define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 395 - #define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 396 - #define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 397 - #define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c 398 - #define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 399 - #define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 400 - #define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 401 - #define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c 402 - #define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 403 - #define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 404 - #define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 405 - #define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 406 - #define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 407 - #define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 408 - #define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 409 - #define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 410 - #define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 411 - #define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 412 - #define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 413 - #define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 414 - #define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 415 - #define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 416 - #define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 417 - #define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c 418 - #define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 419 - #define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 420 - #define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 421 - #define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 422 - #define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 423 - #define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 424 - #define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 425 - #define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 426 - #define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 427 - #define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 428 - #define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 429 - #define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc 430 - #define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 431 - #define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 432 - #define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 433 - #define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc 434 - #define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 435 - #define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 436 - #define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 437 - #define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 438 - #define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 439 - #define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 440 - #define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 441 - #define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 442 - #define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 443 - #define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 444 - #define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 445 - #define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c 446 - #define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 447 - #define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 448 - #define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 449 - #define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c 450 - #define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 451 - #define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 452 - #define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 453 - #define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c 454 - #define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 455 - #define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 456 - #define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 457 - #define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 458 - #define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 459 - #define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 460 - #define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 461 - #define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 462 - #define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 463 - #define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 464 - #define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 465 - #define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c 466 - #define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 467 - #define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 468 - #define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 469 - #define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c 470 - #define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 471 - #define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 472 - #define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 473 - #define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c 474 - #define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 475 - #define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 476 - #define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 477 - #define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c 478 - #define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 479 - #define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 480 - #define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 481 - #define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc 482 - #define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 483 - #define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 484 - #define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 485 - #define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 486 - #define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc 487 - #define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 488 - #define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 489 - #define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 490 - #define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec 491 - #define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 492 - #define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 493 - #define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc 494 - 495 - /* PRM.CUSTEFUSE_PRM register offsets */ 496 - #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 497 - #define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 498 - #define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 499 - 500 - /* PRM.WKUPAON_PRM register offsets */ 501 - #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 502 - #define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 503 - #define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 504 - #define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c 505 - #define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 506 - #define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 507 - #define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 508 - #define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c 509 - #define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 510 - #define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 511 - #define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 512 - #define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 513 - #define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 514 - #define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 515 - #define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 516 - #define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c 517 - #define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 518 - #define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 519 - #define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 520 - #define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c 521 - #define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 522 - #define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 523 - #define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 524 - #define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 525 - #define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 526 - #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 527 - #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 528 - 529 - /* PRM.WKUPAON_CM register offsets */ 530 - #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 531 - #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 532 - #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) 533 - #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 534 - #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) 535 - #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 536 - #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) 537 - #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 538 - #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) 539 - #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 540 - #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) 541 - #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 542 - #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) 543 - #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 544 - #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) 545 - #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 546 - #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) 547 - #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 548 - #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) 549 - #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 550 - #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) 551 - #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 552 - #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) 553 - #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 554 - #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) 555 - #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 556 - #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) 557 - #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 558 - #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) 559 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 560 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) 561 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 562 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) 563 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 564 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) 565 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 566 - #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) 567 - #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 568 - #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) 569 - #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 570 - #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) 571 - 572 - /* PRM.EMU_PRM register offsets */ 573 - #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 574 - #define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 575 - #define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 576 - 577 - /* PRM.EMU_CM register offsets */ 578 - #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 579 - #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 580 - #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) 581 - #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 582 - #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c 583 - #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) 584 - 585 - /* PRM.DSP2_PRM register offsets */ 586 - #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 587 - #define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 588 - #define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 589 - #define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 590 - #define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 591 - 592 - /* PRM.EVE1_PRM register offsets */ 593 - #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 594 - #define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 595 - #define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 596 - #define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 597 - #define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 598 - #define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 599 - 600 - /* PRM.EVE2_PRM register offsets */ 601 - #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 602 - #define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 603 - #define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 604 - #define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 605 - #define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 606 - #define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 607 - 608 - /* PRM.EVE3_PRM register offsets */ 609 - #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 610 - #define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 611 - #define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 612 - #define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 613 - #define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 614 - #define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 615 - 616 - /* PRM.EVE4_PRM register offsets */ 617 - #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 618 - #define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 619 - #define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 620 - #define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 621 - #define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 622 - #define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 623 - 624 - /* PRM.RTC_PRM register offsets */ 625 - #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 626 - #define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 627 - 628 - /* PRM.VPE_PRM register offsets */ 629 - #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 630 - #define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 631 - #define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 632 - #define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 633 - 634 - /* PRM.DEVICE_PRM register offsets */ 635 - #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 636 - #define DRA7XX_PRM_RSTST_OFFSET 0x0004 637 - #define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 638 - #define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c 639 - #define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 640 - #define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 641 - #define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 642 - #define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c 643 - #define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 644 - #define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 645 - #define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 646 - #define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 647 - #define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 648 - #define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 649 - #define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 650 - #define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 651 - #define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc 652 - #define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 653 - #define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 654 - #define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 655 - #define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 656 - #define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 657 - #define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 658 - #define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 659 - #define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 660 - #define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 661 - #define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 662 - #define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 663 - #define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 664 - #define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 665 - #define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 666 - #define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 667 - #define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 668 - #define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 669 - #define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 670 - #define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 671 - #define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 672 - #define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c 673 - #define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 674 - #define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 675 - #define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 676 - #define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c 677 - #define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 678 - #define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 679 66 680 67 #endif
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arch/arm/mach-omap2/scrm44xx.h
··· 22 22 OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) 23 23 24 24 /* Registers offset */ 25 - #define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000 26 - #define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000) 27 - #define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100 28 25 #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100) 29 - #define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104 30 - #define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104) 31 - #define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110 32 - #define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110) 33 - #define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118 34 - #define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118) 35 - #define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c 36 - #define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c) 37 - #define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200 38 - #define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200) 39 - #define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204 40 - #define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204) 41 - #define OMAP4_SCRM_PWRREQ_OFFSET 0x0208 42 - #define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208) 43 - #define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210 44 - #define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210) 45 - #define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214 46 - #define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214) 47 - #define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218 48 - #define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218) 49 - #define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c 50 - #define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c) 51 - #define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220 52 - #define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220) 53 - #define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224 54 - #define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224) 55 - #define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234 56 - #define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234) 57 - #define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310 58 - #define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310) 59 - #define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314 60 - #define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314) 61 - #define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318 62 - #define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318) 63 - #define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c 64 - #define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c) 65 - #define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320 66 - #define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320) 67 - #define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324 68 - #define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324) 69 - #define OMAP4_SCRM_RSTTIME_OFFSET 0x0400 70 - #define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400) 71 - #define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418 72 - #define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418) 73 - #define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c 74 - #define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c) 75 - #define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 76 - #define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420) 77 - #define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510 78 - #define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510) 79 - #define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514 80 - #define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514) 81 - #define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518 82 - #define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518) 83 - #define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c 84 - #define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c) 85 - 86 - /* Registers shifts and masks */ 87 - 88 - /* REVISION_SCRM */ 89 - #define OMAP4_REV_SHIFT 0 90 - #define OMAP4_REV_MASK (0xff << 0) 91 26 92 27 /* CLKSETUPTIME */ 93 28 #define OMAP4_DOWNTIME_SHIFT 16 94 29 #define OMAP4_DOWNTIME_MASK (0x3f << 16) 95 30 #define OMAP4_SETUPTIME_SHIFT 0 96 31 #define OMAP4_SETUPTIME_MASK (0xfff << 0) 97 - 98 - /* PMICSETUPTIME */ 99 - #define OMAP4_WAKEUPTIME_SHIFT 16 100 - #define OMAP4_WAKEUPTIME_MASK (0x3f << 16) 101 - #define OMAP4_SLEEPTIME_SHIFT 0 102 - #define OMAP4_SLEEPTIME_MASK (0x3f << 0) 103 - 104 - /* ALTCLKSRC */ 105 - #define OMAP4_ENABLE_EXT_SHIFT 3 106 - #define OMAP4_ENABLE_EXT_MASK (1 << 3) 107 - #define OMAP4_ENABLE_INT_SHIFT 2 108 - #define OMAP4_ENABLE_INT_MASK (1 << 2) 109 - #define OMAP4_ALTCLKSRC_MODE_SHIFT 0 110 - #define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0) 111 - 112 - /* MODEMCLKM */ 113 - #define OMAP4_CLK_32KHZ_SHIFT 0 114 - #define OMAP4_CLK_32KHZ_MASK (1 << 0) 115 - 116 - /* D2DCLKM */ 117 - #define OMAP4_SYSCLK_SHIFT 1 118 - #define OMAP4_SYSCLK_MASK (1 << 1) 119 - 120 - /* EXTCLKREQ */ 121 - #define OMAP4_POLARITY_SHIFT 0 122 - #define OMAP4_POLARITY_MASK (1 << 0) 123 - 124 - /* AUXCLKREQ0 */ 125 - #define OMAP4_MAPPING_SHIFT 2 126 - #define OMAP4_MAPPING_MASK (0x7 << 2) 127 - #define OMAP4_MAPPING_WIDTH 3 128 - #define OMAP4_ACCURACY_SHIFT 1 129 - #define OMAP4_ACCURACY_MASK (1 << 1) 130 - 131 - /* AUXCLK0 */ 132 - #define OMAP4_CLKDIV_SHIFT 16 133 - #define OMAP4_CLKDIV_MASK (0xf << 16) 134 - #define OMAP4_CLKDIV_WIDTH 4 135 - #define OMAP4_DISABLECLK_SHIFT 9 136 - #define OMAP4_DISABLECLK_MASK (1 << 9) 137 - #define OMAP4_ENABLE_SHIFT 8 138 - #define OMAP4_ENABLE_MASK (1 << 8) 139 - #define OMAP4_SRCSELECT_SHIFT 1 140 - #define OMAP4_SRCSELECT_MASK (0x3 << 1) 141 - 142 - /* RSTTIME */ 143 - #define OMAP4_RSTTIME_SHIFT 0 144 - #define OMAP4_RSTTIME_MASK (0xf << 0) 145 - 146 - /* MODEMRSTCTRL */ 147 - #define OMAP4_WARMRST_SHIFT 1 148 - #define OMAP4_WARMRST_MASK (1 << 1) 149 - #define OMAP4_COLDRST_SHIFT 0 150 - #define OMAP4_COLDRST_MASK (1 << 0) 151 - 152 - /* EXTPWRONRSTCTRL */ 153 - #define OMAP4_PWRONRST_SHIFT 1 154 - #define OMAP4_PWRONRST_MASK (1 << 1) 155 - #define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0 156 - #define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0) 157 - 158 - /* EXTWARMRSTST */ 159 - #define OMAP4_EXTWARMRSTST_SHIFT 0 160 - #define OMAP4_EXTWARMRSTST_MASK (1 << 0) 161 - 162 - /* APEWARMRSTST */ 163 - #define OMAP4_APEWARMRSTST_SHIFT 1 164 - #define OMAP4_APEWARMRSTST_MASK (1 << 1) 165 - 166 - /* MODEMWARMRSTST */ 167 - #define OMAP4_MODEMWARMRSTST_SHIFT 2 168 - #define OMAP4_MODEMWARMRSTST_MASK (1 << 2) 169 - 170 - /* D2DWARMRSTST */ 171 - #define OMAP4_D2DWARMRSTST_SHIFT 3 172 - #define OMAP4_D2DWARMRSTST_MASK (1 << 3) 173 32 174 33 #endif
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arch/arm/mach-omap2/scrm54xx.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only */ 2 - /* 3 - * OMAP54XX SCRM registers and bitfields 4 - * 5 - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 - * 7 - * Benoit Cousson (b-cousson@ti.com) 8 - * 9 - * This file is automatically generated from the OMAP hardware databases. 10 - * We respectfully ask that any modifications to this file be coordinated 11 - * with the public linux-omap@vger.kernel.org mailing list and the 12 - * authors above to ensure that the autogeneration scripts are kept 13 - * up-to-date with the file contents. 14 - */ 15 - 16 - #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H 17 - #define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H 18 - 19 - #define OMAP5_SCRM_BASE 0x4ae0a000 20 - 21 - #define OMAP54XX_SCRM_REGADDR(reg) \ 22 - OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) 23 - 24 - /* SCRM */ 25 - 26 - /* SCRM.SCRM register offsets */ 27 - #define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 28 - #define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) 29 - #define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 30 - #define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) 31 - #define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 32 - #define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) 33 - #define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 34 - #define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) 35 - #define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 36 - #define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) 37 - #define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c 38 - #define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) 39 - #define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 40 - #define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) 41 - #define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 42 - #define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) 43 - #define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 44 - #define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) 45 - #define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 46 - #define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) 47 - #define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 48 - #define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) 49 - #define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 50 - #define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) 51 - #define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c 52 - #define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) 53 - #define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 54 - #define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) 55 - #define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 56 - #define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) 57 - #define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 58 - #define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) 59 - #define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 60 - #define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) 61 - #define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 62 - #define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) 63 - #define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 64 - #define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) 65 - #define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c 66 - #define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) 67 - #define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 68 - #define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) 69 - #define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 70 - #define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) 71 - #define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 72 - #define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) 73 - #define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 74 - #define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) 75 - #define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c 76 - #define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) 77 - #define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 78 - #define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) 79 - #define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 80 - #define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) 81 - #define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 82 - #define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) 83 - #define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 84 - #define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) 85 - #define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c 86 - #define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) 87 - 88 - /* 89 - * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, 90 - * AUXCLKREQ5, D2DCLKREQ 91 - */ 92 - #define OMAP5_ACCURACY_SHIFT 1 93 - #define OMAP5_ACCURACY_WIDTH 0x1 94 - #define OMAP5_ACCURACY_MASK (1 << 1) 95 - 96 - /* Used by APEWARMRSTST */ 97 - #define OMAP5_APEWARMRSTST_SHIFT 1 98 - #define OMAP5_APEWARMRSTST_WIDTH 0x1 99 - #define OMAP5_APEWARMRSTST_MASK (1 << 1) 100 - 101 - /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 102 - #define OMAP5_CLKDIV_SHIFT 16 103 - #define OMAP5_CLKDIV_WIDTH 0x4 104 - #define OMAP5_CLKDIV_MASK (0xf << 16) 105 - 106 - /* Used by D2DCLKM, MODEMCLKM */ 107 - #define OMAP5_CLK_32KHZ_SHIFT 0 108 - #define OMAP5_CLK_32KHZ_WIDTH 0x1 109 - #define OMAP5_CLK_32KHZ_MASK (1 << 0) 110 - 111 - /* Used by D2DRSTCTRL, MODEMRSTCTRL */ 112 - #define OMAP5_COLDRST_SHIFT 0 113 - #define OMAP5_COLDRST_WIDTH 0x1 114 - #define OMAP5_COLDRST_MASK (1 << 0) 115 - 116 - /* Used by D2DWARMRSTST */ 117 - #define OMAP5_D2DWARMRSTST_SHIFT 3 118 - #define OMAP5_D2DWARMRSTST_WIDTH 0x1 119 - #define OMAP5_D2DWARMRSTST_MASK (1 << 3) 120 - 121 - /* Used by AUXCLK0 */ 122 - #define OMAP5_DISABLECLK_SHIFT 9 123 - #define OMAP5_DISABLECLK_WIDTH 0x1 124 - #define OMAP5_DISABLECLK_MASK (1 << 9) 125 - 126 - /* Used by CLKSETUPTIME */ 127 - #define OMAP5_DOWNTIME_SHIFT 16 128 - #define OMAP5_DOWNTIME_WIDTH 0x6 129 - #define OMAP5_DOWNTIME_MASK (0x3f << 16) 130 - 131 - /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 132 - #define OMAP5_ENABLE_SHIFT 8 133 - #define OMAP5_ENABLE_WIDTH 0x1 134 - #define OMAP5_ENABLE_MASK (1 << 8) 135 - 136 - /* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ 137 - #define OMAP5_ENABLE_0_0_SHIFT 0 138 - #define OMAP5_ENABLE_0_0_WIDTH 0x1 139 - #define OMAP5_ENABLE_0_0_MASK (1 << 0) 140 - 141 - /* Used by ALTCLKSRC */ 142 - #define OMAP5_ENABLE_EXT_SHIFT 3 143 - #define OMAP5_ENABLE_EXT_WIDTH 0x1 144 - #define OMAP5_ENABLE_EXT_MASK (1 << 3) 145 - 146 - /* Used by ALTCLKSRC */ 147 - #define OMAP5_ENABLE_INT_SHIFT 2 148 - #define OMAP5_ENABLE_INT_WIDTH 0x1 149 - #define OMAP5_ENABLE_INT_MASK (1 << 2) 150 - 151 - /* Used by EXTWARMRSTST */ 152 - #define OMAP5_EXTWARMRSTST_SHIFT 0 153 - #define OMAP5_EXTWARMRSTST_WIDTH 0x1 154 - #define OMAP5_EXTWARMRSTST_MASK (1 << 0) 155 - 156 - /* 157 - * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, 158 - * AUXCLKREQ5 159 - */ 160 - #define OMAP5_MAPPING_SHIFT 2 161 - #define OMAP5_MAPPING_WIDTH 0x3 162 - #define OMAP5_MAPPING_MASK (0x7 << 2) 163 - 164 - /* Used by ALTCLKSRC */ 165 - #define OMAP5_MODE_SHIFT 0 166 - #define OMAP5_MODE_WIDTH 0x2 167 - #define OMAP5_MODE_MASK (0x3 << 0) 168 - 169 - /* Used by MODEMWARMRSTST */ 170 - #define OMAP5_MODEMWARMRSTST_SHIFT 2 171 - #define OMAP5_MODEMWARMRSTST_WIDTH 0x1 172 - #define OMAP5_MODEMWARMRSTST_MASK (1 << 2) 173 - 174 - /* 175 - * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, 176 - * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, 177 - * D2DCLKREQ, EXTCLKREQ, PWRREQ 178 - */ 179 - #define OMAP5_POLARITY_SHIFT 0 180 - #define OMAP5_POLARITY_WIDTH 0x1 181 - #define OMAP5_POLARITY_MASK (1 << 0) 182 - 183 - /* Used by EXTPWRONRSTCTRL */ 184 - #define OMAP5_PWRONRST_SHIFT 1 185 - #define OMAP5_PWRONRST_WIDTH 0x1 186 - #define OMAP5_PWRONRST_MASK (1 << 1) 187 - 188 - /* Used by REVISION_SCRM */ 189 - #define OMAP5_REV_SHIFT 0 190 - #define OMAP5_REV_WIDTH 0x8 191 - #define OMAP5_REV_MASK (0xff << 0) 192 - 193 - /* Used by RSTTIME */ 194 - #define OMAP5_RSTTIME_SHIFT 0 195 - #define OMAP5_RSTTIME_WIDTH 0x4 196 - #define OMAP5_RSTTIME_MASK (0xf << 0) 197 - 198 - /* Used by CLKSETUPTIME */ 199 - #define OMAP5_SETUPTIME_SHIFT 0 200 - #define OMAP5_SETUPTIME_WIDTH 0xc 201 - #define OMAP5_SETUPTIME_MASK (0xfff << 0) 202 - 203 - /* Used by PMICSETUPTIME */ 204 - #define OMAP5_SLEEPTIME_SHIFT 0 205 - #define OMAP5_SLEEPTIME_WIDTH 0x6 206 - #define OMAP5_SLEEPTIME_MASK (0x3f << 0) 207 - 208 - /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 209 - #define OMAP5_SRCSELECT_SHIFT 1 210 - #define OMAP5_SRCSELECT_WIDTH 0x2 211 - #define OMAP5_SRCSELECT_MASK (0x3 << 1) 212 - 213 - /* Used by D2DCLKM */ 214 - #define OMAP5_SYSCLK_SHIFT 1 215 - #define OMAP5_SYSCLK_WIDTH 0x1 216 - #define OMAP5_SYSCLK_MASK (1 << 1) 217 - 218 - /* Used by PMICSETUPTIME */ 219 - #define OMAP5_WAKEUPTIME_SHIFT 16 220 - #define OMAP5_WAKEUPTIME_WIDTH 0x6 221 - #define OMAP5_WAKEUPTIME_MASK (0x3f << 16) 222 - 223 - /* Used by D2DRSTCTRL, MODEMRSTCTRL */ 224 - #define OMAP5_WARMRST_SHIFT 1 225 - #define OMAP5_WARMRST_WIDTH 0x1 226 - #define OMAP5_WARMRST_MASK (1 << 1) 227 - 228 - #endif
+18 -4
arch/arm/mach-s3c/irq-s3c24xx.c
··· 361 361 static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) 362 362 { 363 363 do { 364 - if (likely(s3c_intc[0])) 365 - if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) 366 - continue; 364 + /* 365 + * For platform based machines, neither ERR nor NULL can happen here. 366 + * The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds: 367 + * 368 + * s3c_intc[0] = s3c24xx_init_intc() 369 + * 370 + * If this fails, the next calls to s3c24xx_init_intc() won't be executed. 371 + * 372 + * For DT machine, s3c_init_intc_of() could set the IRQ handler without 373 + * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no 374 + * such code path, so again the s3c_intc[0] will have a valid pointer if 375 + * set_handle_irq() is called. 376 + * 377 + * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something. 378 + */ 379 + if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) 380 + continue; 367 381 368 - if (s3c_intc[2]) 382 + if (!IS_ERR_OR_NULL(s3c_intc[2])) 369 383 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) 370 384 continue; 371 385
+1 -1
arch/arm/mach-s3c/mach-mini6410.c
··· 262 262 static int __init mini6410_features_setup(char *str) 263 263 { 264 264 if (str) 265 - strlcpy(mini6410_features_str, str, 265 + strscpy(mini6410_features_str, str, 266 266 sizeof(mini6410_features_str)); 267 267 return 1; 268 268 }
+8
arch/arm/mach-stm32/Kconfig
··· 48 48 select ARM_ERRATA_814220 49 49 default y 50 50 51 + config MACH_STM32MP13 52 + bool "STMicroelectronics STM32MP13x" 53 + select ARM_ERRATA_814220 54 + default y 55 + help 56 + Support for STM32MP13 SoCs: 57 + STM32MP131, STM32MP133, STM32MP135 58 + 51 59 endif # ARMv7-A 52 60 53 61 endif
+3
arch/arm/mach-stm32/board-dt.c
··· 18 18 "st,stm32f769", 19 19 "st,stm32h743", 20 20 "st,stm32h750", 21 + "st,stm32mp131", 22 + "st,stm32mp133", 23 + "st,stm32mp135", 21 24 "st,stm32mp157", 22 25 NULL 23 26 };
+1 -3
arch/arm/mach-sunxi/platsmp.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * SMP support for Allwinner SoCs 3 4 * ··· 9 8 * Based on code 10 9 * Copyright (C) 2012-2013 Allwinner Ltd. 11 10 * 12 - * This file is licensed under the terms of the GNU General Public 13 - * License version 2. This program is licensed "as is" without any 14 - * warranty of any kind, whether express or implied. 15 11 */ 16 12 17 13 #include <linux/delay.h>
+1 -3
arch/arm/mach-sunxi/sunxi.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 3 * Device Tree support for Allwinner A1X SoCs 3 4 * ··· 6 5 * 7 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 7 * 9 - * This file is licensed under the terms of the GNU General Public 10 - * License version 2. This program is licensed "as is" without any 11 - * warranty of any kind, whether express or implied. 12 8 */ 13 9 14 10 #include <linux/clocksource.h>