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kernel os linux

phy: dphy: add support to calculate the timing based on hs_clk_rate

For MIPI-CSI sender use-case it is common to specify the allowed
link-frequencies which should be used for the MIPI link and is
half the hs-clock rate.

This commit adds a helper to calculate the D-PHY timing based on the
hs-clock rate so we don't need to calculate the timings within the
driver.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>

authored by

Marco Felsch and committed by
Sakari Ailus
22168675 7afa5db0

+21 -4
+18 -4
drivers/phy/phy-core-mipi-dphy.c
··· 20 20 static int phy_mipi_dphy_calc_config(unsigned long pixel_clock, 21 21 unsigned int bpp, 22 22 unsigned int lanes, 23 + unsigned long long hs_clk_rate, 23 24 struct phy_configure_opts_mipi_dphy *cfg) 24 25 { 25 - unsigned long long hs_clk_rate; 26 26 unsigned long long ui; 27 27 28 28 if (!cfg) 29 29 return -EINVAL; 30 30 31 - hs_clk_rate = pixel_clock * bpp; 32 - do_div(hs_clk_rate, lanes); 31 + if (!hs_clk_rate) { 32 + hs_clk_rate = pixel_clock * bpp; 33 + do_div(hs_clk_rate, lanes); 34 + } 33 35 34 36 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 35 37 do_div(ui, hs_clk_rate); ··· 83 81 unsigned int lanes, 84 82 struct phy_configure_opts_mipi_dphy *cfg) 85 83 { 86 - return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, cfg); 84 + return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, 0, cfg); 87 85 88 86 } 89 87 EXPORT_SYMBOL(phy_mipi_dphy_get_default_config); 88 + 89 + int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate, 90 + unsigned int lanes, 91 + struct phy_configure_opts_mipi_dphy *cfg) 92 + { 93 + if (!hs_clk_rate) 94 + return -EINVAL; 95 + 96 + return phy_mipi_dphy_calc_config(0, 0, lanes, hs_clk_rate, cfg); 97 + 98 + } 99 + EXPORT_SYMBOL(phy_mipi_dphy_get_default_config_for_hsclk); 90 100 91 101 /* 92 102 * Validate D-PHY configuration according to MIPI D-PHY specification
+3
include/linux/phy/phy-mipi-dphy.h
··· 279 279 unsigned int bpp, 280 280 unsigned int lanes, 281 281 struct phy_configure_opts_mipi_dphy *cfg); 282 + int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate, 283 + unsigned int lanes, 284 + struct phy_configure_opts_mipi_dphy *cfg); 282 285 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg); 283 286 284 287 #endif /* __PHY_MIPI_DPHY_H_ */