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kernel
os
linux
media: ccs-pll: Document the CCS PLL flags
Document the CCS PLL flags with short comments. The CCS spec has more
information on them while the added documentation helps finding the
relevant information in the CCS spec.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
authored by
Sakari Ailus
and committed by
Hans Verkuil
220ea143
de651469
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-4
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-1
drivers/media/i2c/ccs-pll.c
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drivers/media/i2c/ccs-pll.c
···
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{
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dev_dbg(dev, "PLL flags%s%s%s%s%s%s%s%s%s%s%s\n",
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pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "",
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pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
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pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "",
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pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
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pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
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pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
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" ext-ip-pll-divider" : "",
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drivers/media/i2c/ccs-pll.h
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drivers/media/i2c/ccs-pll.h
···
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#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
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#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
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/* Old SMIA and implementation specific flags */
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/* op pix clock is for all lanes in total normally */
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/* Old SMIA and implementation specific flags. */
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/* OP PIX clock is for all lanes in total normally. */
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#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
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#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
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/* If set, the PLL multipliers are required to be even. */
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#define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER BIT(3)
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/* CCS PLL flags */
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/* The sensor doesn't have OP clocks at all. */
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#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
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/* System speed model if this flag is unset. */
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#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
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/* If set, the pre-PLL divider may have odd values, too. */
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#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
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/*
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* If set, the OP PIX clock doesn't have to exactly match with data rate, it may
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* be higher. See "OP Domain Formulas" in MIPI CCS 1.1 spec.
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*/
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#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
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/* If set, the VT domain may run faster than the OP domain. */
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#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
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/* If set, the VT domain may run slower than the OP domain. */
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#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
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/* If set, the PLL tree has two PLLs instead of one. */
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#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
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/*
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* If set, the OP SYS clock is a dual data rate clock, transferring two bits per
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* cycle instead of one.
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*/
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#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
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/*
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* If set, the OP PIX clock is a dual data rate clock, transferring two pixels
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* per cycle instead of one.
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*/
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#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
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/**