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[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S
Patch from Gen FUKATSU
Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.
Signed-off-by: Gen Fukatsu
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by Gen FUKATSU and committed by Russell King 217874fe a06f5466
+8
-1
arch/arm/mm/cache-v6.S
+8
-1
arch/arm/mm/cache-v6.S
···
18
#define HARVARD_CACHE
19
#define CACHE_LINE_SIZE 32
20
#define D_CACHE_LINE_SIZE 32
21
22
/*
23
* v6_flush_cache_all()
···
99
mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
100
#endif
101
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
102
-
add r0, r0, #CACHE_LINE_SIZE
103
cmp r0, r1
104
blo 1b
105
#ifdef HARVARD_CACHE
···
18
#define HARVARD_CACHE
19
#define CACHE_LINE_SIZE 32
20
#define D_CACHE_LINE_SIZE 32
21
+
#define BTB_FLUSH_SIZE 8
22
23
/*
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* v6_flush_cache_all()
···
98
mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
99
#endif
100
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
101
+
add r0, r0, #BTB_FLUSH_SIZE
102
+
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
103
+
add r0, r0, #BTB_FLUSH_SIZE
104
+
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
105
+
add r0, r0, #BTB_FLUSH_SIZE
106
+
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
107
+
add r0, r0, #BTB_FLUSH_SIZE
108
cmp r0, r1
109
blo 1b
110
#ifdef HARVARD_CACHE