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drm/amd/display: Fix spelling mistake: "dram_clk_chanage" -> "dram_clk_change"

There is a spelling mistake in the struct field dram_clk_chanage. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Colin Ian King and committed by
Alex Deucher 2165359b 66efff51

+20 -20
+4 -4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
··· 55 55 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); 56 56 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); 57 57 } 58 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); 58 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); 59 59 60 60 s = &wm->sets[1]; 61 61 s->wm_set = 1; ··· 65 65 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); 66 66 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); 67 67 } 68 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); 68 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); 69 69 70 70 s = &wm->sets[2]; 71 71 s->wm_set = 2; ··· 75 75 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); 76 76 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); 77 77 } 78 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); 78 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); 79 79 80 80 s = &wm->sets[3]; 81 81 s->wm_set = 3; ··· 85 85 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); 86 86 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); 87 87 } 88 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 88 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 89 89 } 90 90 91 91 void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
+1 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
··· 159 159 DTN_INFO_MICRO_SEC(s->pte_meta_urgent); 160 160 DTN_INFO_MICRO_SEC(s->sr_enter); 161 161 DTN_INFO_MICRO_SEC(s->sr_exit); 162 - DTN_INFO_MICRO_SEC(s->dram_clk_chanage); 162 + DTN_INFO_MICRO_SEC(s->dram_clk_change); 163 163 DTN_INFO("\n"); 164 164 } 165 165
+2 -2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
··· 83 83 memset(&wm, 0, sizeof(struct dcn_hubbub_wm)); 84 84 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); 85 85 86 - chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n"); 86 + chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_change\n"); 87 87 remaining_buffer -= chars_printed; 88 88 pBuf += chars_printed; 89 89 ··· 98 98 (s->pte_meta_urgent * frac) / ref_clk_mhz / frac, (s->pte_meta_urgent * frac) / ref_clk_mhz % frac, 99 99 (s->sr_enter * frac) / ref_clk_mhz / frac, (s->sr_enter * frac) / ref_clk_mhz % frac, 100 100 (s->sr_exit * frac) / ref_clk_mhz / frac, (s->sr_exit * frac) / ref_clk_mhz % frac, 101 - (s->dram_clk_chanage * frac) / ref_clk_mhz / frac, (s->dram_clk_chanage * frac) / ref_clk_mhz % frac); 101 + (s->dram_clk_change * frac) / ref_clk_mhz / frac, (s->dram_clk_change * frac) / ref_clk_mhz % frac); 102 102 remaining_buffer -= chars_printed; 103 103 pBuf += chars_printed; 104 104 }
+4 -4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
··· 500 500 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); 501 501 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); 502 502 } 503 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); 503 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); 504 504 505 505 s = &wm->sets[1]; 506 506 s->wm_set = 1; ··· 511 511 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); 512 512 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); 513 513 } 514 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); 514 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); 515 515 516 516 s = &wm->sets[2]; 517 517 s->wm_set = 2; ··· 522 522 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); 523 523 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); 524 524 } 525 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); 525 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); 526 526 527 527 s = &wm->sets[3]; 528 528 s->wm_set = 3; ··· 533 533 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); 534 534 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); 535 535 } 536 - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 536 + s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 537 537 } 538 538 539 539 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
+4 -4
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
··· 635 635 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); 636 636 637 637 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 638 - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage); 638 + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_change); 639 639 640 640 s = &wm->sets[1]; 641 641 s->wm_set = 1; ··· 649 649 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); 650 650 651 651 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 652 - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage); 652 + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_change); 653 653 654 654 s = &wm->sets[2]; 655 655 s->wm_set = 2; ··· 663 663 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); 664 664 665 665 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 666 - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage); 666 + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_change); 667 667 668 668 s = &wm->sets[3]; 669 669 s->wm_set = 3; ··· 677 677 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); 678 678 679 679 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 680 - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage); 680 + DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_change); 681 681 } 682 682 683 683 static void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
+4 -4
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
··· 865 865 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); 866 866 867 867 REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 868 - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_chanage); 868 + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_change); 869 869 870 870 REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 871 871 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain); ··· 885 885 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); 886 886 887 887 REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 888 - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_chanage); 888 + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_change); 889 889 890 890 REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 891 891 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain); ··· 905 905 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); 906 906 907 907 REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 908 - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_chanage); 908 + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_change); 909 909 910 910 REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 911 911 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain); ··· 925 925 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); 926 926 927 927 REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 928 - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_chanage); 928 + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_change); 929 929 930 930 REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 931 931 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain);
+1 -1
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
··· 46 46 uint32_t pte_meta_urgent; 47 47 uint32_t sr_enter; 48 48 uint32_t sr_exit; 49 - uint32_t dram_clk_chanage; 49 + uint32_t dram_clk_change; 50 50 uint32_t usr_retrain; 51 51 uint32_t fclk_pstate_change; 52 52 };