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linux
phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe
Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241122023314.1616353-3-quic_ziyuzhan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Krishna chaitanya chundru
and committed by
Vinod Koul
21364b0f
1e889f2b
+106
+105
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+105
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
728
728
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
729
729
};
730
730
731
+
static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = {
732
+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
733
+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
734
+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
735
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
736
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
737
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
738
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
739
+
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
740
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
741
+
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
742
+
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
743
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
744
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
745
+
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
746
+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9),
747
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4),
748
+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
749
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
750
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
751
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
752
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
753
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd),
754
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04),
755
+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35),
756
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
757
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
758
+
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4),
759
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
760
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30),
761
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
762
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
763
+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
764
+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
765
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
766
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
767
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
768
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
769
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
770
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
771
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
772
+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
773
+
};
774
+
775
+
static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = {
776
+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
777
+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
778
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
779
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
780
+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
781
+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
782
+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
783
+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
784
+
};
785
+
786
+
static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = {
787
+
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
788
+
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
789
+
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
790
+
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
791
+
};
792
+
793
+
static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = {
794
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
795
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
796
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
797
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
798
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
799
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
800
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
801
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
802
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7),
803
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
804
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
805
+
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
806
+
};
807
+
731
808
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
732
809
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
733
810
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
···
3209
3132
.pipe_clock_rate = 250000000,
3210
3133
};
3211
3134
3135
+
static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
3136
+
.lanes = 1,
3137
+
3138
+
.offsets = &qmp_pcie_offsets_v2,
3139
+
3140
+
.tbls = {
3141
+
.serdes = qcs615_pcie_serdes_tbl,
3142
+
.serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl),
3143
+
.tx = qcs615_pcie_tx_tbl,
3144
+
.tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl),
3145
+
.rx = qcs615_pcie_rx_tbl,
3146
+
.rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl),
3147
+
.pcs = qcs615_pcie_pcs_tbl,
3148
+
.pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl),
3149
+
},
3150
+
.reset_list = sdm845_pciephy_reset_l,
3151
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3152
+
.vreg_list = qmp_phy_vreg_l,
3153
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3154
+
.regs = pciephy_v2_regs_layout,
3155
+
3156
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3157
+
.phy_status = PHYSTATUS,
3158
+
};
3159
+
3212
3160
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3213
3161
.lanes = 1,
3214
3162
···
4713
4611
}, {
4714
4612
.compatible = "qcom,msm8998-qmp-pcie-phy",
4715
4613
.data = &msm8998_pciephy_cfg,
4614
+
}, {
4615
+
.compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
4616
+
.data = &qcs615_pciephy_cfg,
4716
4617
}, {
4717
4618
.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
4718
4619
.data = &sa8775p_qmp_gen4x2_pciephy_cfg,
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
···
34
34
#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */
35
35
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
36
36
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
37
+
#define QPHY_V2_PCS_SIGDET_CNTRL 0x1b0
37
38
#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
38
39
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
39
40
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0