tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[SCSI] qla2xxx: Update firmware-dump procedure for ISP24xx.

Small changes to register retrieval and order as per latest
firmware specification.

Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>

authored by andrew.vasquez@qlogic.com and committed by James Bottomley 210d5350 e978010c

+55 -54
unified split
+53 -52
drivers/scsi/qla2xxx/qla_dbg.c
··· 1003 fw = (struct qla24xx_fw_dump *) ha->fw_dump24; 1004 1005 rval = QLA_SUCCESS; 1006 - fw->hccr = RD_REG_DWORD(&reg->hccr); 1007 1008 /* Pause RISC. */ 1009 - if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) { 1010 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | 1011 HCCRX_CLR_HOST_INT); 1012 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ ··· 1021 } 1022 } 1023 1024 - /* Disable interrupts. */ 1025 - WRT_REG_DWORD(&reg->ictrl, 0); 1026 - RD_REG_DWORD(&reg->ictrl); 1027 - 1028 if (rval == QLA_SUCCESS) { 1029 /* Host interface registers. */ 1030 dmp_reg = (uint32_t __iomem *)(reg + 0); 1031 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1032 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++); 1033 1034 /* Mailbox registers. */ 1035 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); ··· 1345 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1346 for (cnt = 0; cnt < 16; cnt++) 1347 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1348 - 1349 - WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1350 - RD_REG_DWORD(&reg->iobase_addr); 1351 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1352 - WRT_REG_DWORD(dmp_reg, 0xB0000000); 1353 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1354 - fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg); 1355 - 1356 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1357 - WRT_REG_DWORD(dmp_reg, 0xB0100000); 1358 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1359 - fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg); 1360 - 1361 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1362 - WRT_REG_DWORD(dmp_reg, 0xB0200000); 1363 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1364 - fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg); 1365 - 1366 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1367 - WRT_REG_DWORD(dmp_reg, 0xB0300000); 1368 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1369 - fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg); 1370 - 1371 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1372 - WRT_REG_DWORD(dmp_reg, 0xB0400000); 1373 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1374 - fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg); 1375 - 1376 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1377 - WRT_REG_DWORD(dmp_reg, 0xB0500000); 1378 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1379 - fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg); 1380 - 1381 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1382 - WRT_REG_DWORD(dmp_reg, 0xB0600000); 1383 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1384 - fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg); 1385 1386 /* Local memory controller registers. */ 1387 iter_reg = fw->lmc_reg; ··· 1678 ha->fw_major_version, ha->fw_minor_version, 1679 ha->fw_subminor_version, ha->fw_attributes); 1680 1681 - qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr); 1682 1683 qla_uprintf(&uiter, "\nHost Interface Registers"); 1684 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) { ··· 1686 qla_uprintf(&uiter, "\n"); 1687 1688 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]); 1689 } 1690 1691 qla_uprintf(&uiter, "\n\nMailbox Registers"); ··· 1862 qla_uprintf(&uiter, "\n"); 1863 1864 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]); 1865 - } 1866 - 1867 - qla_uprintf(&uiter, "\n\nShadow Registers"); 1868 - for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) { 1869 - if (cnt % 8 == 0) 1870 - qla_uprintf(&uiter, "\n"); 1871 - 1872 - qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]); 1873 } 1874 1875 qla_uprintf(&uiter, "\n\nLMC Registers");
··· 1003 fw = (struct qla24xx_fw_dump *) ha->fw_dump24; 1004 1005 rval = QLA_SUCCESS; 1006 + fw->host_status = RD_REG_DWORD(&reg->host_status); 1007 1008 /* Pause RISC. */ 1009 + if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 1010 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | 1011 HCCRX_CLR_HOST_INT); 1012 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ ··· 1021 } 1022 } 1023 1024 if (rval == QLA_SUCCESS) { 1025 /* Host interface registers. */ 1026 dmp_reg = (uint32_t __iomem *)(reg + 0); 1027 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1028 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++); 1029 + 1030 + /* Disable interrupts. */ 1031 + WRT_REG_DWORD(&reg->ictrl, 0); 1032 + RD_REG_DWORD(&reg->ictrl); 1033 + 1034 + /* Shadow registers. */ 1035 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1036 + RD_REG_DWORD(&reg->iobase_addr); 1037 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1038 + WRT_REG_DWORD(dmp_reg, 0xB0000000); 1039 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1040 + fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg); 1041 + 1042 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1043 + WRT_REG_DWORD(dmp_reg, 0xB0100000); 1044 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1045 + fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg); 1046 + 1047 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1048 + WRT_REG_DWORD(dmp_reg, 0xB0200000); 1049 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1050 + fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg); 1051 + 1052 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1053 + WRT_REG_DWORD(dmp_reg, 0xB0300000); 1054 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1055 + fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg); 1056 + 1057 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1058 + WRT_REG_DWORD(dmp_reg, 0xB0400000); 1059 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1060 + fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg); 1061 + 1062 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1063 + WRT_REG_DWORD(dmp_reg, 0xB0500000); 1064 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1065 + fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg); 1066 + 1067 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 1068 + WRT_REG_DWORD(dmp_reg, 0xB0600000); 1069 + dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 1070 + fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg); 1071 1072 /* Mailbox registers. */ 1073 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); ··· 1307 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1308 for (cnt = 0; cnt < 16; cnt++) 1309 *iter_reg++ = RD_REG_DWORD(dmp_reg++); 1310 1311 /* Local memory controller registers. */ 1312 iter_reg = fw->lmc_reg; ··· 1677 ha->fw_major_version, ha->fw_minor_version, 1678 ha->fw_subminor_version, ha->fw_attributes); 1679 1680 + qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status); 1681 1682 qla_uprintf(&uiter, "\nHost Interface Registers"); 1683 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) { ··· 1685 qla_uprintf(&uiter, "\n"); 1686 1687 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]); 1688 + } 1689 + 1690 + qla_uprintf(&uiter, "\n\nShadow Registers"); 1691 + for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) { 1692 + if (cnt % 8 == 0) 1693 + qla_uprintf(&uiter, "\n"); 1694 + 1695 + qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]); 1696 } 1697 1698 qla_uprintf(&uiter, "\n\nMailbox Registers"); ··· 1853 qla_uprintf(&uiter, "\n"); 1854 1855 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]); 1856 } 1857 1858 qla_uprintf(&uiter, "\n\nLMC Registers");
+2 -2
drivers/scsi/qla2xxx/qla_dbg.h
··· 227 #define FW_DUMP_SIZE_24XX 0x2B0000 228 229 struct qla24xx_fw_dump { 230 - uint32_t hccr; 231 uint32_t host_reg[32]; 232 uint16_t mailbox_reg[32]; 233 uint32_t xseq_gp_reg[128]; 234 uint32_t xseq_0_reg[16]; ··· 251 uint32_t rcvt0_data_dma_reg[32]; 252 uint32_t rcvt1_data_dma_reg[32]; 253 uint32_t risc_gp_reg[128]; 254 - uint32_t shadow_reg[7]; 255 uint32_t lmc_reg[112]; 256 uint32_t fpm_hdw_reg[192]; 257 uint32_t fb_hdw_reg[176];
··· 227 #define FW_DUMP_SIZE_24XX 0x2B0000 228 229 struct qla24xx_fw_dump { 230 + uint32_t host_status; 231 uint32_t host_reg[32]; 232 + uint32_t shadow_reg[7]; 233 uint16_t mailbox_reg[32]; 234 uint32_t xseq_gp_reg[128]; 235 uint32_t xseq_0_reg[16]; ··· 250 uint32_t rcvt0_data_dma_reg[32]; 251 uint32_t rcvt1_data_dma_reg[32]; 252 uint32_t risc_gp_reg[128]; 253 uint32_t lmc_reg[112]; 254 uint32_t fpm_hdw_reg[192]; 255 uint32_t fb_hdw_reg[176];